42b333721611bb72c0a1aa44d9119b529de86027
[platform/kernel/u-boot.git] / include / configs / B4860QDS.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
4  */
5
6 #ifndef __CONFIG_H
7 #define __CONFIG_H
8
9 /*
10  * B4860 QDS board configuration file
11  */
12 #ifdef CONFIG_RAMBOOT_PBL
13 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
14 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
15 #ifndef CONFIG_NAND
16 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
17 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
18 #else
19 #define CONFIG_SPL_FLUSH_IMAGE
20 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
21 #define CONFIG_SPL_PAD_TO               0x40000
22 #define CONFIG_SPL_MAX_SIZE             0x28000
23 #define RESET_VECTOR_OFFSET             0x27FFC
24 #define BOOT_PAGE_OFFSET                0x27000
25 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
26 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
27 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
28 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
29 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
30 #define CONFIG_SPL_NAND_BOOT
31 #ifdef CONFIG_SPL_BUILD
32 #define CONFIG_SPL_SKIP_RELOCATE
33 #define CONFIG_SPL_COMMON_INIT_DDR
34 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
35 #endif
36 #endif
37 #endif
38
39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
40 /* Set 1M boot space */
41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
43                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
45 #endif
46
47 /* High Level Configuration Options */
48 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
49
50 #ifndef CONFIG_RESET_VECTOR_ADDRESS
51 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
52 #endif
53
54 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
55 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
56 #define CONFIG_PCIE1                    /* PCIE controller 1 */
57 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
58 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
59
60 #ifndef CONFIG_ARCH_B4420
61 #define CONFIG_SYS_SRIO
62 #define CONFIG_SRIO1                    /* SRIO port 1 */
63 #define CONFIG_SRIO2                    /* SRIO port 2 */
64 #define CONFIG_SRIO_PCIE_BOOT_MASTER
65 #endif
66
67 /* I2C bus multiplexer */
68 #define I2C_MUX_PCA_ADDR                0x77
69
70 /* VSC Crossbar switches */
71 #define CONFIG_VSC_CROSSBAR
72 #define I2C_CH_DEFAULT                  0x8
73 #define I2C_CH_VSC3316                  0xc
74 #define I2C_CH_VSC3308                  0xd
75
76 #define VSC3316_TX_ADDRESS              0x70
77 #define VSC3316_RX_ADDRESS              0x71
78 #define VSC3308_TX_ADDRESS              0x02
79 #define VSC3308_RX_ADDRESS              0x03
80
81 /* IDT clock synthesizers */
82 #define CONFIG_IDT8T49N222A
83 #define I2C_CH_IDT                     0x9
84
85 #define IDT_SERDES1_ADDRESS            0x6E
86 #define IDT_SERDES2_ADDRESS            0x6C
87
88 /* Voltage monitor on channel 2*/
89 #define I2C_MUX_CH_VOL_MONITOR          0xa
90 #define I2C_VOL_MONITOR_ADDR            0x40
91 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
92 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
93 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
94
95 #define CONFIG_ZM7300
96 #define I2C_MUX_CH_DPM                  0xa
97 #define I2C_DPM_ADDR                    0x28
98
99 #define CONFIG_ENV_OVERWRITE
100
101 #if defined(CONFIG_SPIFLASH)
102 #define CONFIG_ENV_SPI_BUS              0
103 #define CONFIG_ENV_SPI_CS               0
104 #define CONFIG_ENV_SPI_MAX_HZ           10000000
105 #define CONFIG_ENV_SPI_MODE             0
106 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
107 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
108 #define CONFIG_ENV_SECT_SIZE            0x10000
109 #elif defined(CONFIG_SDCARD)
110 #define CONFIG_SYS_MMC_ENV_DEV          0
111 #define CONFIG_ENV_SIZE                 0x2000
112 #define CONFIG_ENV_OFFSET               (512 * 1097)
113 #elif defined(CONFIG_NAND)
114 #define CONFIG_ENV_SIZE                 0x2000
115 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
116 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
117 #define CONFIG_ENV_ADDR         0xffe20000
118 #define CONFIG_ENV_SIZE         0x2000
119 #elif defined(CONFIG_ENV_IS_NOWHERE)
120 #define CONFIG_ENV_SIZE         0x2000
121 #else
122 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
123 #define CONFIG_ENV_SIZE         0x2000
124 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
125 #endif
126
127 #ifndef __ASSEMBLY__
128 unsigned long get_board_sys_clk(void);
129 unsigned long get_board_ddr_clk(void);
130 #endif
131 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
132 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
133
134 /*
135  * These can be toggled for performance analysis, otherwise use default.
136  */
137 #define CONFIG_SYS_CACHE_STASHING
138 #define CONFIG_BTB                      /* toggle branch predition */
139 #define CONFIG_DDR_ECC
140 #ifdef CONFIG_DDR_ECC
141 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
142 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
143 #endif
144
145 #define CONFIG_ENABLE_36BIT_PHYS
146
147 #ifdef CONFIG_PHYS_64BIT
148 #define CONFIG_ADDR_MAP
149 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
150 #endif
151
152 #if 0
153 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
154 #endif
155 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
156 #define CONFIG_SYS_MEMTEST_END          0x00400000
157
158 /*
159  *  Config the L3 Cache as L3 SRAM
160  */
161 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
162 #define CONFIG_SYS_L3_SIZE              256 << 10
163 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
164 #ifdef CONFIG_NAND
165 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
166 #endif
167 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
168 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
169 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
170
171 #ifdef CONFIG_PHYS_64BIT
172 #define CONFIG_SYS_DCSRBAR              0xf0000000
173 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
174 #endif
175
176 /* EEPROM */
177 #define CONFIG_ID_EEPROM
178 #define CONFIG_SYS_I2C_EEPROM_NXID
179 #define CONFIG_SYS_EEPROM_BUS_NUM       0
180 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
181 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
182 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
183 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
184
185 /*
186  * DDR Setup
187  */
188 #define CONFIG_VERY_BIG_RAM
189 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
190 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
191
192 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
193 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
194
195 #define CONFIG_DDR_SPD
196 #define CONFIG_SYS_DDR_RAW_TIMING
197
198 #define CONFIG_SYS_SPD_BUS_NUM  0
199 #define SPD_EEPROM_ADDRESS1     0x51
200 #define SPD_EEPROM_ADDRESS2     0x53
201
202 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
203 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
204
205 /*
206  * IFC Definitions
207  */
208 #define CONFIG_SYS_FLASH_BASE   0xe0000000
209 #ifdef CONFIG_PHYS_64BIT
210 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
211 #else
212 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
213 #endif
214
215 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
216 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
217                                 + 0x8000000) | \
218                                 CSPR_PORT_SIZE_16 | \
219                                 CSPR_MSEL_NOR | \
220                                 CSPR_V)
221 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
222 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
223                                 CSPR_PORT_SIZE_16 | \
224                                 CSPR_MSEL_NOR | \
225                                 CSPR_V)
226 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
227 /* NOR Flash Timing Params */
228 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
229 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
230                                 FTIM0_NOR_TEADC(0x04) | \
231                                 FTIM0_NOR_TEAHC(0x20))
232 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
233                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
234                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
235 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
236                                 FTIM2_NOR_TCH(0x0E) | \
237                                 FTIM2_NOR_TWPH(0x0E) | \
238                                 FTIM2_NOR_TWP(0x1c))
239 #define CONFIG_SYS_NOR_FTIM3    0x0
240
241 #define CONFIG_SYS_FLASH_QUIET_TEST
242 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
243
244 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
245 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
246 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
247 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
248
249 #define CONFIG_SYS_FLASH_EMPTY_INFO
250 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
251                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
252
253 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
254 #define CONFIG_FSL_QIXIS_V2
255 #define QIXIS_BASE              0xffdf0000
256 #ifdef CONFIG_PHYS_64BIT
257 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
258 #else
259 #define QIXIS_BASE_PHYS         QIXIS_BASE
260 #endif
261 #define QIXIS_LBMAP_SWITCH              0x01
262 #define QIXIS_LBMAP_MASK                0x0f
263 #define QIXIS_LBMAP_SHIFT               0
264 #define QIXIS_LBMAP_DFLTBANK            0x00
265 #define QIXIS_LBMAP_ALTBANK             0x02
266 #define QIXIS_RST_CTL_RESET             0x31
267 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
268 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
269 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
270
271 #define CONFIG_SYS_CSPR3_EXT    (0xf)
272 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
273                                 | CSPR_PORT_SIZE_8 \
274                                 | CSPR_MSEL_GPCM \
275                                 | CSPR_V)
276 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
277 #define CONFIG_SYS_CSOR3        0x0
278 /* QIXIS Timing parameters for IFC CS3 */
279 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
280                                         FTIM0_GPCM_TEADC(0x0e) | \
281                                         FTIM0_GPCM_TEAHC(0x0e))
282 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
283                                         FTIM1_GPCM_TRAD(0x1f))
284 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
285                                         FTIM2_GPCM_TCH(0x8) | \
286                                         FTIM2_GPCM_TWP(0x1f))
287 #define CONFIG_SYS_CS3_FTIM3            0x0
288
289 /* NAND Flash on IFC */
290 #define CONFIG_NAND_FSL_IFC
291 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
292 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
293 #define CONFIG_SYS_NAND_BASE            0xff800000
294 #ifdef CONFIG_PHYS_64BIT
295 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
296 #else
297 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
298 #endif
299
300 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
301 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
302                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
303                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
304                                 | CSPR_V)
305 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
306
307 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
308                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
309                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
310                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
311                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
312                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
313                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
314
315 #define CONFIG_SYS_NAND_ONFI_DETECTION
316
317 /* ONFI NAND Flash mode0 Timing Params */
318 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
319                                         FTIM0_NAND_TWP(0x18)   | \
320                                         FTIM0_NAND_TWCHT(0x07) | \
321                                         FTIM0_NAND_TWH(0x0a))
322 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
323                                         FTIM1_NAND_TWBE(0x39)  | \
324                                         FTIM1_NAND_TRR(0x0e)   | \
325                                         FTIM1_NAND_TRP(0x18))
326 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
327                                         FTIM2_NAND_TREH(0x0a) | \
328                                         FTIM2_NAND_TWHRE(0x1e))
329 #define CONFIG_SYS_NAND_FTIM3           0x0
330
331 #define CONFIG_SYS_NAND_DDR_LAW         11
332
333 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
334 #define CONFIG_SYS_MAX_NAND_DEVICE      1
335
336 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
337
338 #if defined(CONFIG_NAND)
339 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
340 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
341 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
342 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
343 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
344 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
345 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
346 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
347 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
348 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
349 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
350 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
351 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
352 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
353 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
354 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
355 #else
356 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
357 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
358 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
359 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
360 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
361 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
362 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
363 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
364 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
365 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
366 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
367 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
368 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
369 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
370 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
371 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
372 #endif
373 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
374 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
375 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
376 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
377 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
378 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
379 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
380 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
381
382 #ifdef CONFIG_SPL_BUILD
383 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
384 #else
385 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
386 #endif
387
388 #if defined(CONFIG_RAMBOOT_PBL)
389 #define CONFIG_SYS_RAMBOOT
390 #endif
391
392 #define CONFIG_HWCONFIG
393
394 /* define to use L1 as initial stack */
395 #define CONFIG_L1_INIT_RAM
396 #define CONFIG_SYS_INIT_RAM_LOCK
397 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
398 #ifdef CONFIG_PHYS_64BIT
399 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
400 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
401 /* The assembler doesn't like typecast */
402 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
403         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
404           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
405 #else
406 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
407 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
408 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
409 #endif
410 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
411
412 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
413                                         GENERATED_GBL_DATA_SIZE)
414 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
415
416 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
417 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
418
419 /* Serial Port - controlled on board with jumper J8
420  * open - index 2
421  * shorted - index 1
422  */
423 #define CONFIG_SYS_NS16550_SERIAL
424 #define CONFIG_SYS_NS16550_REG_SIZE     1
425 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
426
427 #define CONFIG_SYS_BAUDRATE_TABLE       \
428         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
429
430 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
431 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
432 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
433 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
434
435 /* I2C */
436 #define CONFIG_SYS_I2C
437 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
438 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
439 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
440 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
441 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
442 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
443 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
444
445 /*
446  * RTC configuration
447  */
448 #define RTC
449 #define CONFIG_RTC_DS3231               1
450 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
451
452 /*
453  * RapidIO
454  */
455 #ifdef CONFIG_SYS_SRIO
456 #ifdef CONFIG_SRIO1
457 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
458 #ifdef CONFIG_PHYS_64BIT
459 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
460 #else
461 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
462 #endif
463 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
464 #endif
465
466 #ifdef CONFIG_SRIO2
467 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
468 #ifdef CONFIG_PHYS_64BIT
469 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
470 #else
471 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
472 #endif
473 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
474 #endif
475 #endif
476
477 /*
478  * for slave u-boot IMAGE instored in master memory space,
479  * PHYS must be aligned based on the SIZE
480  */
481 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
482 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
483 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
484 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
485 /*
486  * for slave UCODE and ENV instored in master memory space,
487  * PHYS must be aligned based on the SIZE
488  */
489 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
490 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
491 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
492
493 /* slave core release by master*/
494 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
495 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
496
497 /*
498  * SRIO_PCIE_BOOT - SLAVE
499  */
500 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
501 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
502 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
503                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
504 #endif
505
506 /*
507  * eSPI - Enhanced SPI
508  */
509 #define CONFIG_SF_DEFAULT_SPEED         10000000
510 #define CONFIG_SF_DEFAULT_MODE          0
511
512 /*
513  * MAPLE
514  */
515 #ifdef CONFIG_PHYS_64BIT
516 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
517 #else
518 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
519 #endif
520
521 /*
522  * General PCI
523  * Memory space is mapped 1-1, but I/O space must start from 0.
524  */
525
526 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
527 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
528 #ifdef CONFIG_PHYS_64BIT
529 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
530 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
531 #else
532 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
533 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
534 #endif
535 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
536 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
537 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
538 #ifdef CONFIG_PHYS_64BIT
539 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
540 #else
541 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
542 #endif
543 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
544
545 /* Qman/Bman */
546 #ifndef CONFIG_NOBQFMAN
547 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
548 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
549 #ifdef CONFIG_PHYS_64BIT
550 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
551 #else
552 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
553 #endif
554 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
555 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
556 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
557 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
558 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
559 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
560                                         CONFIG_SYS_BMAN_CENA_SIZE)
561 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
562 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
563 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
564 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
565 #ifdef CONFIG_PHYS_64BIT
566 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
567 #else
568 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
569 #endif
570 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
571 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
572 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
573 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
574 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
575 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
576                                         CONFIG_SYS_QMAN_CENA_SIZE)
577 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
578 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
579
580 #define CONFIG_SYS_DPAA_FMAN
581
582 #define CONFIG_SYS_DPAA_RMAN
583
584 /* Default address of microcode for the Linux Fman driver */
585 #if defined(CONFIG_SPIFLASH)
586 /*
587  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
588  * env, so we got 0x110000.
589  */
590 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
591 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
592 #elif defined(CONFIG_SDCARD)
593 /*
594  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
595  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
596  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
597  */
598 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
599 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
600 #elif defined(CONFIG_NAND)
601 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
602 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
603 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
604 /*
605  * Slave has no ucode locally, it can fetch this from remote. When implementing
606  * in two corenet boards, slave's ucode could be stored in master's memory
607  * space, the address can be mapped from slave TLB->slave LAW->
608  * slave SRIO or PCIE outbound window->master inbound window->
609  * master LAW->the ucode address in master's memory space.
610  */
611 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
612 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
613 #else
614 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
615 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
616 #endif
617 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
618 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
619 #endif /* CONFIG_NOBQFMAN */
620
621 #ifdef CONFIG_SYS_DPAA_FMAN
622 #define CONFIG_FMAN_ENET
623 #define CONFIG_PHYLIB_10G
624 #define CONFIG_PHY_VITESSE
625 #define CONFIG_PHY_TERANETICS
626 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
627 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
628 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
629 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
630 #endif
631
632 #ifdef CONFIG_PCI
633 #define CONFIG_PCI_INDIRECT_BRIDGE
634
635 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
636 #endif  /* CONFIG_PCI */
637
638 #ifdef CONFIG_FMAN_ENET
639 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
640 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
641
642 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
643 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
644 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
645
646 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
647 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
648 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
649 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
650
651 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
652 #endif
653
654 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
655
656 /*
657  * Environment
658  */
659 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
660 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
661
662 /*
663 * USB
664 */
665 #define CONFIG_HAS_FSL_DR_USB
666
667 #ifdef CONFIG_HAS_FSL_DR_USB
668 #ifdef CONFIG_USB_EHCI_HCD
669 #define CONFIG_USB_EHCI_FSL
670 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
671 #endif
672 #endif
673
674 /*
675  * Miscellaneous configurable options
676  */
677 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
678
679 /*
680  * For booting Linux, the board info and command line data
681  * have to be in the first 64 MB of memory, since this is
682  * the maximum mapped by the Linux kernel during initialization.
683  */
684 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
685 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
686
687 #ifdef CONFIG_CMD_KGDB
688 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
689 #endif
690
691 /*
692  * Environment Configuration
693  */
694 #define CONFIG_ROOTPATH         "/opt/nfsroot"
695 #define CONFIG_BOOTFILE         "uImage"
696 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
697
698 /* default location for tftp and bootm */
699 #define CONFIG_LOADADDR         1000000
700
701 #define __USB_PHY_TYPE  ulpi
702
703 #ifdef CONFIG_ARCH_B4860
704 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
705                         "bank_intlv=cs0_cs1;"   \
706                         "en_cpc:cpc2;"
707 #else
708 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
709 #endif
710
711 #define CONFIG_EXTRA_ENV_SETTINGS                               \
712         HWCONFIG                                                \
713         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
714         "netdev=eth0\0"                                         \
715         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
716         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
717         "tftpflash=tftpboot $loadaddr $uboot && "               \
718         "protect off $ubootaddr +$filesize && "                 \
719         "erase $ubootaddr +$filesize && "                       \
720         "cp.b $loadaddr $ubootaddr $filesize && "               \
721         "protect on $ubootaddr +$filesize && "                  \
722         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
723         "consoledev=ttyS0\0"                                    \
724         "ramdiskaddr=2000000\0"                                 \
725         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
726         "fdtaddr=1e00000\0"                                     \
727         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
728         "bdev=sda3\0"
729
730 /* For emulation this causes u-boot to jump to the start of the proof point
731    app code automatically */
732 #define CONFIG_PROOF_POINTS                     \
733  "setenv bootargs root=/dev/$bdev rw "          \
734  "console=$consoledev,$baudrate $othbootargs;"  \
735  "cpu 1 release 0x29000000 - - -;"              \
736  "cpu 2 release 0x29000000 - - -;"              \
737  "cpu 3 release 0x29000000 - - -;"              \
738  "cpu 4 release 0x29000000 - - -;"              \
739  "cpu 5 release 0x29000000 - - -;"              \
740  "cpu 6 release 0x29000000 - - -;"              \
741  "cpu 7 release 0x29000000 - - -;"              \
742  "go 0x29000000"
743
744 #define CONFIG_HVBOOT   \
745  "setenv bootargs config-addr=0x60000000; "     \
746  "bootm 0x01000000 - 0x00f00000"
747
748 #define CONFIG_ALU                              \
749  "setenv bootargs root=/dev/$bdev rw "          \
750  "console=$consoledev,$baudrate $othbootargs;"  \
751  "cpu 1 release 0x01000000 - - -;"              \
752  "cpu 2 release 0x01000000 - - -;"              \
753  "cpu 3 release 0x01000000 - - -;"              \
754  "cpu 4 release 0x01000000 - - -;"              \
755  "cpu 5 release 0x01000000 - - -;"              \
756  "cpu 6 release 0x01000000 - - -;"              \
757  "cpu 7 release 0x01000000 - - -;"              \
758  "go 0x01000000"
759
760 #define CONFIG_LINUX                            \
761  "setenv bootargs root=/dev/ram rw "            \
762  "console=$consoledev,$baudrate $othbootargs;"  \
763  "setenv ramdiskaddr 0x02000000;"               \
764  "setenv fdtaddr 0x01e00000;"                   \
765  "setenv loadaddr 0x1000000;"                   \
766  "bootm $loadaddr $ramdiskaddr $fdtaddr"
767
768 #define CONFIG_HDBOOT                                   \
769         "setenv bootargs root=/dev/$bdev rw "           \
770         "console=$consoledev,$baudrate $othbootargs;"   \
771         "tftp $loadaddr $bootfile;"                     \
772         "tftp $fdtaddr $fdtfile;"                       \
773         "bootm $loadaddr - $fdtaddr"
774
775 #define CONFIG_NFSBOOTCOMMAND                   \
776         "setenv bootargs root=/dev/nfs rw "     \
777         "nfsroot=$serverip:$rootpath "          \
778         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
779         "console=$consoledev,$baudrate $othbootargs;"   \
780         "tftp $loadaddr $bootfile;"             \
781         "tftp $fdtaddr $fdtfile;"               \
782         "bootm $loadaddr - $fdtaddr"
783
784 #define CONFIG_RAMBOOTCOMMAND                           \
785         "setenv bootargs root=/dev/ram rw "             \
786         "console=$consoledev,$baudrate $othbootargs;"   \
787         "tftp $ramdiskaddr $ramdiskfile;"               \
788         "tftp $loadaddr $bootfile;"                     \
789         "tftp $fdtaddr $fdtfile;"                       \
790         "bootm $loadaddr $ramdiskaddr $fdtaddr"
791
792 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
793
794 #include <asm/fsl_secure_boot.h>
795
796 #endif  /* __CONFIG_H */