1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
10 * B4860 QDS board configuration file
12 #ifdef CONFIG_RAMBOOT_PBL
13 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
14 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19 #define CONFIG_SPL_FLUSH_IMAGE
20 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
21 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
22 #define CONFIG_SPL_PAD_TO 0x40000
23 #define CONFIG_SPL_MAX_SIZE 0x28000
24 #define RESET_VECTOR_OFFSET 0x27FFC
25 #define BOOT_PAGE_OFFSET 0x27000
26 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
27 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
28 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
29 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
30 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
31 #define CONFIG_SPL_NAND_BOOT
32 #ifdef CONFIG_SPL_BUILD
33 #define CONFIG_SPL_SKIP_RELOCATE
34 #define CONFIG_SPL_COMMON_INIT_DDR
35 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
40 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
41 /* Set 1M boot space */
42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
44 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
45 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
48 /* High Level Configuration Options */
49 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
50 #define CONFIG_MP /* support multiple processors */
52 #ifndef CONFIG_RESET_VECTOR_ADDRESS
53 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
56 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
57 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
58 #define CONFIG_PCIE1 /* PCIE controller 1 */
59 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
60 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
62 #ifndef CONFIG_ARCH_B4420
63 #define CONFIG_SYS_SRIO
64 #define CONFIG_SRIO1 /* SRIO port 1 */
65 #define CONFIG_SRIO2 /* SRIO port 2 */
66 #define CONFIG_SRIO_PCIE_BOOT_MASTER
69 /* I2C bus multiplexer */
70 #define I2C_MUX_PCA_ADDR 0x77
72 /* VSC Crossbar switches */
73 #define CONFIG_VSC_CROSSBAR
74 #define I2C_CH_DEFAULT 0x8
75 #define I2C_CH_VSC3316 0xc
76 #define I2C_CH_VSC3308 0xd
78 #define VSC3316_TX_ADDRESS 0x70
79 #define VSC3316_RX_ADDRESS 0x71
80 #define VSC3308_TX_ADDRESS 0x02
81 #define VSC3308_RX_ADDRESS 0x03
83 /* IDT clock synthesizers */
84 #define CONFIG_IDT8T49N222A
85 #define I2C_CH_IDT 0x9
87 #define IDT_SERDES1_ADDRESS 0x6E
88 #define IDT_SERDES2_ADDRESS 0x6C
90 /* Voltage monitor on channel 2*/
91 #define I2C_MUX_CH_VOL_MONITOR 0xa
92 #define I2C_VOL_MONITOR_ADDR 0x40
93 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
94 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
95 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
98 #define I2C_MUX_CH_DPM 0xa
99 #define I2C_DPM_ADDR 0x28
101 #define CONFIG_ENV_OVERWRITE
103 #ifndef CONFIG_MTD_NOR_FLASH
105 #define CONFIG_FLASH_CFI_DRIVER
106 #define CONFIG_SYS_FLASH_CFI
107 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
110 #if defined(CONFIG_SPIFLASH)
111 #define CONFIG_SYS_EXTRA_ENV_RELOC
112 #define CONFIG_ENV_SPI_BUS 0
113 #define CONFIG_ENV_SPI_CS 0
114 #define CONFIG_ENV_SPI_MAX_HZ 10000000
115 #define CONFIG_ENV_SPI_MODE 0
116 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
117 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
118 #define CONFIG_ENV_SECT_SIZE 0x10000
119 #elif defined(CONFIG_SDCARD)
120 #define CONFIG_SYS_EXTRA_ENV_RELOC
121 #define CONFIG_SYS_MMC_ENV_DEV 0
122 #define CONFIG_ENV_SIZE 0x2000
123 #define CONFIG_ENV_OFFSET (512 * 1097)
124 #elif defined(CONFIG_NAND)
125 #define CONFIG_SYS_EXTRA_ENV_RELOC
126 #define CONFIG_ENV_SIZE 0x2000
127 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
128 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
129 #define CONFIG_ENV_ADDR 0xffe20000
130 #define CONFIG_ENV_SIZE 0x2000
131 #elif defined(CONFIG_ENV_IS_NOWHERE)
132 #define CONFIG_ENV_SIZE 0x2000
134 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
135 #define CONFIG_ENV_SIZE 0x2000
136 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
140 unsigned long get_board_sys_clk(void);
141 unsigned long get_board_ddr_clk(void);
143 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
144 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
147 * These can be toggled for performance analysis, otherwise use default.
149 #define CONFIG_SYS_CACHE_STASHING
150 #define CONFIG_BTB /* toggle branch predition */
151 #define CONFIG_DDR_ECC
152 #ifdef CONFIG_DDR_ECC
153 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
154 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
157 #define CONFIG_ENABLE_36BIT_PHYS
159 #ifdef CONFIG_PHYS_64BIT
160 #define CONFIG_ADDR_MAP
161 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
165 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
167 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
168 #define CONFIG_SYS_MEMTEST_END 0x00400000
171 * Config the L3 Cache as L3 SRAM
173 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
174 #define CONFIG_SYS_L3_SIZE 256 << 10
175 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
177 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
179 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
180 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
181 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
182 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
184 #ifdef CONFIG_PHYS_64BIT
185 #define CONFIG_SYS_DCSRBAR 0xf0000000
186 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
190 #define CONFIG_ID_EEPROM
191 #define CONFIG_SYS_I2C_EEPROM_NXID
192 #define CONFIG_SYS_EEPROM_BUS_NUM 0
193 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
194 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
195 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
196 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
201 #define CONFIG_VERY_BIG_RAM
202 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
203 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
205 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
206 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
208 #define CONFIG_DDR_SPD
209 #define CONFIG_SYS_DDR_RAW_TIMING
210 #ifndef CONFIG_SPL_BUILD
211 #define CONFIG_FSL_DDR_INTERACTIVE
214 #define CONFIG_SYS_SPD_BUS_NUM 0
215 #define SPD_EEPROM_ADDRESS1 0x51
216 #define SPD_EEPROM_ADDRESS2 0x53
218 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
219 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
224 #define CONFIG_SYS_FLASH_BASE 0xe0000000
225 #ifdef CONFIG_PHYS_64BIT
226 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
228 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
231 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
232 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
234 CSPR_PORT_SIZE_16 | \
237 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
238 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
239 CSPR_PORT_SIZE_16 | \
242 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
243 /* NOR Flash Timing Params */
244 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
245 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
246 FTIM0_NOR_TEADC(0x04) | \
247 FTIM0_NOR_TEAHC(0x20))
248 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
249 FTIM1_NOR_TRAD_NOR(0x1A) |\
250 FTIM1_NOR_TSEQRAD_NOR(0x13))
251 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
252 FTIM2_NOR_TCH(0x0E) | \
253 FTIM2_NOR_TWPH(0x0E) | \
255 #define CONFIG_SYS_NOR_FTIM3 0x0
257 #define CONFIG_SYS_FLASH_QUIET_TEST
258 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
260 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
261 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
262 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
263 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
265 #define CONFIG_SYS_FLASH_EMPTY_INFO
266 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
267 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
269 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
270 #define CONFIG_FSL_QIXIS_V2
271 #define QIXIS_BASE 0xffdf0000
272 #ifdef CONFIG_PHYS_64BIT
273 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
275 #define QIXIS_BASE_PHYS QIXIS_BASE
277 #define QIXIS_LBMAP_SWITCH 0x01
278 #define QIXIS_LBMAP_MASK 0x0f
279 #define QIXIS_LBMAP_SHIFT 0
280 #define QIXIS_LBMAP_DFLTBANK 0x00
281 #define QIXIS_LBMAP_ALTBANK 0x02
282 #define QIXIS_RST_CTL_RESET 0x31
283 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
284 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
285 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
287 #define CONFIG_SYS_CSPR3_EXT (0xf)
288 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
292 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
293 #define CONFIG_SYS_CSOR3 0x0
294 /* QIXIS Timing parameters for IFC CS3 */
295 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
296 FTIM0_GPCM_TEADC(0x0e) | \
297 FTIM0_GPCM_TEAHC(0x0e))
298 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
299 FTIM1_GPCM_TRAD(0x1f))
300 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
301 FTIM2_GPCM_TCH(0x8) | \
302 FTIM2_GPCM_TWP(0x1f))
303 #define CONFIG_SYS_CS3_FTIM3 0x0
305 /* NAND Flash on IFC */
306 #define CONFIG_NAND_FSL_IFC
307 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
308 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
309 #define CONFIG_SYS_NAND_BASE 0xff800000
310 #ifdef CONFIG_PHYS_64BIT
311 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
313 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
316 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
317 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
318 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
319 | CSPR_MSEL_NAND /* MSEL = NAND */ \
321 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
323 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
324 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
325 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
326 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
327 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
328 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
329 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
331 #define CONFIG_SYS_NAND_ONFI_DETECTION
333 /* ONFI NAND Flash mode0 Timing Params */
334 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
335 FTIM0_NAND_TWP(0x18) | \
336 FTIM0_NAND_TWCHT(0x07) | \
337 FTIM0_NAND_TWH(0x0a))
338 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
339 FTIM1_NAND_TWBE(0x39) | \
340 FTIM1_NAND_TRR(0x0e) | \
341 FTIM1_NAND_TRP(0x18))
342 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
343 FTIM2_NAND_TREH(0x0a) | \
344 FTIM2_NAND_TWHRE(0x1e))
345 #define CONFIG_SYS_NAND_FTIM3 0x0
347 #define CONFIG_SYS_NAND_DDR_LAW 11
349 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
350 #define CONFIG_SYS_MAX_NAND_DEVICE 1
352 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
354 #if defined(CONFIG_NAND)
355 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
356 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
357 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
358 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
359 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
360 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
361 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
362 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
363 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
364 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
365 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
366 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
367 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
368 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
369 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
370 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
372 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
373 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
374 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
375 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
376 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
377 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
378 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
379 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
380 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
381 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
382 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
383 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
384 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
385 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
386 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
387 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
389 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
390 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
391 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
392 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
393 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
394 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
395 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
396 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
398 #ifdef CONFIG_SPL_BUILD
399 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
401 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
404 #if defined(CONFIG_RAMBOOT_PBL)
405 #define CONFIG_SYS_RAMBOOT
408 #define CONFIG_MISC_INIT_R
410 #define CONFIG_HWCONFIG
412 /* define to use L1 as initial stack */
413 #define CONFIG_L1_INIT_RAM
414 #define CONFIG_SYS_INIT_RAM_LOCK
415 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
416 #ifdef CONFIG_PHYS_64BIT
417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
419 /* The assembler doesn't like typecast */
420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
421 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
422 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
428 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
430 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
431 GENERATED_GBL_DATA_SIZE)
432 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
434 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
435 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
437 /* Serial Port - controlled on board with jumper J8
441 #define CONFIG_SYS_NS16550_SERIAL
442 #define CONFIG_SYS_NS16550_REG_SIZE 1
443 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
445 #define CONFIG_SYS_BAUDRATE_TABLE \
446 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
448 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
449 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
450 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
451 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
454 #define CONFIG_SYS_I2C
455 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
456 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
457 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
458 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
459 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
460 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
461 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
467 #define CONFIG_RTC_DS3231 1
468 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
473 #ifdef CONFIG_SYS_SRIO
475 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
476 #ifdef CONFIG_PHYS_64BIT
477 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
479 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
481 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
485 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
486 #ifdef CONFIG_PHYS_64BIT
487 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
489 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
491 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
496 * for slave u-boot IMAGE instored in master memory space,
497 * PHYS must be aligned based on the SIZE
499 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
500 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
501 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
502 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
504 * for slave UCODE and ENV instored in master memory space,
505 * PHYS must be aligned based on the SIZE
507 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
508 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
509 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
511 /* slave core release by master*/
512 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
513 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
516 * SRIO_PCIE_BOOT - SLAVE
518 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
519 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
520 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
521 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
525 * eSPI - Enhanced SPI
527 #define CONFIG_SF_DEFAULT_SPEED 10000000
528 #define CONFIG_SF_DEFAULT_MODE 0
533 #ifdef CONFIG_PHYS_64BIT
534 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
536 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
541 * Memory space is mapped 1-1, but I/O space must start from 0.
544 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
545 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
546 #ifdef CONFIG_PHYS_64BIT
547 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
548 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
550 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
551 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
553 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
554 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
555 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
556 #ifdef CONFIG_PHYS_64BIT
557 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
559 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
561 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
564 #ifndef CONFIG_NOBQFMAN
565 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
566 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
567 #ifdef CONFIG_PHYS_64BIT
568 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
570 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
572 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
573 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
574 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
575 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
576 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
577 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
578 CONFIG_SYS_BMAN_CENA_SIZE)
579 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
580 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
581 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
582 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
583 #ifdef CONFIG_PHYS_64BIT
584 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
586 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
588 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
589 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
590 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
591 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
592 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
593 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
594 CONFIG_SYS_QMAN_CENA_SIZE)
595 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
596 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
598 #define CONFIG_SYS_DPAA_FMAN
600 #define CONFIG_SYS_DPAA_RMAN
602 /* Default address of microcode for the Linux Fman driver */
603 #if defined(CONFIG_SPIFLASH)
605 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
606 * env, so we got 0x110000.
608 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
609 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
610 #elif defined(CONFIG_SDCARD)
612 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
613 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
614 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
616 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
617 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
618 #elif defined(CONFIG_NAND)
619 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
620 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
621 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
623 * Slave has no ucode locally, it can fetch this from remote. When implementing
624 * in two corenet boards, slave's ucode could be stored in master's memory
625 * space, the address can be mapped from slave TLB->slave LAW->
626 * slave SRIO or PCIE outbound window->master inbound window->
627 * master LAW->the ucode address in master's memory space.
629 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
630 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
632 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
633 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
635 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
636 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
637 #endif /* CONFIG_NOBQFMAN */
639 #ifdef CONFIG_SYS_DPAA_FMAN
640 #define CONFIG_FMAN_ENET
641 #define CONFIG_PHYLIB_10G
642 #define CONFIG_PHY_VITESSE
643 #define CONFIG_PHY_TERANETICS
644 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
645 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
646 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
647 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
651 #define CONFIG_PCI_INDIRECT_BRIDGE
653 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
654 #endif /* CONFIG_PCI */
656 #ifdef CONFIG_FMAN_ENET
657 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
658 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
660 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
661 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
662 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
664 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
665 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
666 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
667 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
669 #define CONFIG_MII /* MII PHY management */
670 #define CONFIG_ETHPRIME "FM1@DTSEC1"
673 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
678 #define CONFIG_LOADS_ECHO /* echo on for serial download */
679 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
684 #define CONFIG_HAS_FSL_DR_USB
686 #ifdef CONFIG_HAS_FSL_DR_USB
687 #ifdef CONFIG_USB_EHCI_HCD
688 #define CONFIG_USB_EHCI_FSL
689 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
694 * Miscellaneous configurable options
696 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
699 * For booting Linux, the board info and command line data
700 * have to be in the first 64 MB of memory, since this is
701 * the maximum mapped by the Linux kernel during initialization.
703 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
704 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
706 #ifdef CONFIG_CMD_KGDB
707 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
711 * Environment Configuration
713 #define CONFIG_ROOTPATH "/opt/nfsroot"
714 #define CONFIG_BOOTFILE "uImage"
715 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
717 /* default location for tftp and bootm */
718 #define CONFIG_LOADADDR 1000000
720 #define __USB_PHY_TYPE ulpi
722 #ifdef CONFIG_ARCH_B4860
723 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \
724 "bank_intlv=cs0_cs1;" \
727 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
730 #define CONFIG_EXTRA_ENV_SETTINGS \
732 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
734 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
735 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
736 "tftpflash=tftpboot $loadaddr $uboot && " \
737 "protect off $ubootaddr +$filesize && " \
738 "erase $ubootaddr +$filesize && " \
739 "cp.b $loadaddr $ubootaddr $filesize && " \
740 "protect on $ubootaddr +$filesize && " \
741 "cmp.b $loadaddr $ubootaddr $filesize\0" \
742 "consoledev=ttyS0\0" \
743 "ramdiskaddr=2000000\0" \
744 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
745 "fdtaddr=1e00000\0" \
746 "fdtfile=b4860qds/b4860qds.dtb\0" \
749 /* For emulation this causes u-boot to jump to the start of the proof point
750 app code automatically */
751 #define CONFIG_PROOF_POINTS \
752 "setenv bootargs root=/dev/$bdev rw " \
753 "console=$consoledev,$baudrate $othbootargs;" \
754 "cpu 1 release 0x29000000 - - -;" \
755 "cpu 2 release 0x29000000 - - -;" \
756 "cpu 3 release 0x29000000 - - -;" \
757 "cpu 4 release 0x29000000 - - -;" \
758 "cpu 5 release 0x29000000 - - -;" \
759 "cpu 6 release 0x29000000 - - -;" \
760 "cpu 7 release 0x29000000 - - -;" \
763 #define CONFIG_HVBOOT \
764 "setenv bootargs config-addr=0x60000000; " \
765 "bootm 0x01000000 - 0x00f00000"
768 "setenv bootargs root=/dev/$bdev rw " \
769 "console=$consoledev,$baudrate $othbootargs;" \
770 "cpu 1 release 0x01000000 - - -;" \
771 "cpu 2 release 0x01000000 - - -;" \
772 "cpu 3 release 0x01000000 - - -;" \
773 "cpu 4 release 0x01000000 - - -;" \
774 "cpu 5 release 0x01000000 - - -;" \
775 "cpu 6 release 0x01000000 - - -;" \
776 "cpu 7 release 0x01000000 - - -;" \
779 #define CONFIG_LINUX \
780 "setenv bootargs root=/dev/ram rw " \
781 "console=$consoledev,$baudrate $othbootargs;" \
782 "setenv ramdiskaddr 0x02000000;" \
783 "setenv fdtaddr 0x01e00000;" \
784 "setenv loadaddr 0x1000000;" \
785 "bootm $loadaddr $ramdiskaddr $fdtaddr"
787 #define CONFIG_HDBOOT \
788 "setenv bootargs root=/dev/$bdev rw " \
789 "console=$consoledev,$baudrate $othbootargs;" \
790 "tftp $loadaddr $bootfile;" \
791 "tftp $fdtaddr $fdtfile;" \
792 "bootm $loadaddr - $fdtaddr"
794 #define CONFIG_NFSBOOTCOMMAND \
795 "setenv bootargs root=/dev/nfs rw " \
796 "nfsroot=$serverip:$rootpath " \
797 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
798 "console=$consoledev,$baudrate $othbootargs;" \
799 "tftp $loadaddr $bootfile;" \
800 "tftp $fdtaddr $fdtfile;" \
801 "bootm $loadaddr - $fdtaddr"
803 #define CONFIG_RAMBOOTCOMMAND \
804 "setenv bootargs root=/dev/ram rw " \
805 "console=$consoledev,$baudrate $othbootargs;" \
806 "tftp $ramdiskaddr $ramdiskfile;" \
807 "tftp $loadaddr $bootfile;" \
808 "tftp $fdtaddr $fdtfile;" \
809 "bootm $loadaddr $ramdiskaddr $fdtaddr"
811 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
813 #include <asm/fsl_secure_boot.h>
815 #endif /* __CONFIG_H */