3 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
5 * Copyright 2004, 2007 Freescale Semiconductor.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * atum8548 board configuration file
29 * Please refer to doc/README.atum8548 for more info.
35 /* Debug Options, Disable in production
37 #define CONFIG_PANIC_HANG 1
41 /* CPLD Configuration Options */
42 #define MPC85xx_ATUM_CLKOCR 0x80000002
44 /* High Level Configuration Options */
45 #define CONFIG_BOOKE 1 /* BOOKE */
46 #define CONFIG_E500 1 /* BOOKE e500 family */
47 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
48 #define CONFIG_MPC8548 1 /* MPC8548 specific */
50 #define CONFIG_PCI 1 /* enable any pci type devices */
51 #define CONFIG_PCI1 1 /* PCI controller 1 */
52 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
53 #define CONFIG_PCI2 1 /* PCI controller 2 */
54 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
56 #define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
57 #define CONFIG_ENV_OVERWRITE
59 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
61 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
63 #define CONFIG_SYS_CLK_FREQ 33000000
66 * These can be toggled for performance analysis, otherwise use default.
68 #define CONFIG_L2_CACHE /* toggle L2 cache */
69 #define CONFIG_BTB /* toggle branch predition */
72 * Only possible on E500 Version 2 or newer cores.
74 #define CONFIG_ENABLE_36BIT_PHYS 1
76 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
78 #define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
79 #define CONFIG_ENABLE_36BIT_PHYS 1
80 #undef CONFIG_SYS_DRAM_TEST
81 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
82 #define CONFIG_SYS_MEMTEST_END 0x00400000
85 * Base addresses -- Note these are effective addresses where the
86 * actual resources get mapped (not physical addresses)
88 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
89 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
90 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
91 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
93 #define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
96 #define CONFIG_FSL_DDR2
97 #undef CONFIG_FSL_DDR_INTERACTIVE
98 #define CONFIG_DDR_ECC /* only for ECC DDR module */
99 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
100 #define CONFIG_DDR_SPD
102 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
103 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
107 #define CONFIG_VERY_BIG_RAM
109 #define CONFIG_NUM_DDR_CONTROLLERS 1
110 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
111 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
113 /* I2C addresses of SPD EEPROMs */
114 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
116 /* Manually set up DDR parameters */
117 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
118 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
119 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102
120 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
121 #define CONFIG_SYS_DDR_TIMING_1 0x38355322
122 #define CONFIG_SYS_DDR_TIMING_2 0x039048c7
123 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
124 #define CONFIG_SYS_DDR_MODE 0x00000432
125 #define CONFIG_SYS_DDR_INTERVAL 0x05150100
126 #define DDR_SDRAM_CFG 0x43000000
128 #undef CONFIG_CLOCKS_IN_MHZ
131 * Local Bus Definitions
135 * FLASH on the Local Bus
136 * based on flash chip S29GL01GP
137 * One bank, 128M, using the CFI driver.
138 * Boot from BR0 bank at 0xf800_0000
141 * Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
142 * Port Size = 16 bits = BRx[19:20] = 10
143 * Use GPCM = BRx[24:26] = 000
144 * Valid = BRx[31] = 1
146 * 0 4 8 12 16 20 24 28
147 * 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0
150 * Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
151 * Reserved ORx[17:18] = 00
153 * ACS = half cycle delay = ORx[21:22] = 11
154 * SCY = 6 = ORx[24:27] = 0110
155 * TRLX = use relaxed timing = ORx[29] = 1
156 * EAD = use external address latch delay = OR[31] = 1
158 * 0 4 8 12 16 20 24 28
159 * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx
162 #define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */
163 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
165 #define CONFIG_SYS_BR0_PRELIM 0xf8001001
167 #define CONFIG_SYS_OR0_PRELIM 0xf8000E65
169 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
170 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
171 #undef CONFIG_SYS_FLASH_CHECKSUM
172 #define CONFIG_SYS_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */
173 #define CONFIG_SYS_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
176 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
178 #define CONFIG_FLASH_CFI_DRIVER 1
179 #define CONFIG_SYS_FLASH_CFI 1
180 #define CONFIG_SYS_FLASH_EMPTY_INFO
183 * Flash on the LocalBus
185 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
188 #define CONFIG_SYS_INIT_RAM_LOCK 1
189 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
190 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
192 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
194 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
195 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
196 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
198 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
199 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
202 #define CONFIG_CONS_INDEX 1
203 #undef CONFIG_SERIAL_SOFTWARE_FIFO
204 #define CONFIG_SYS_NS16550
205 #define CONFIG_SYS_NS16550_SERIAL
206 #define CONFIG_SYS_NS16550_REG_SIZE 1
207 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
209 #define CONFIG_SYS_BAUDRATE_TABLE \
210 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
213 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
215 /* Use the HUSH parser */
216 #define CONFIG_SYS_HUSH_PARSER
217 #ifdef CONFIG_SYS_HUSH_PARSER
218 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
221 /* pass open firmware flat tree */
222 #define CONFIG_OF_LIBFDT 1
223 #define CONFIG_OF_BOARD_SETUP 1
228 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
229 #define CONFIG_HARD_I2C /* I2C with hardware support*/
230 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
231 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
232 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
233 #define CONFIG_SYS_I2C_SLAVE 0x7F
234 #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
235 #define CONFIG_SYS_I2C_OFFSET 0x3000
239 * Memory space is mapped 1-1, but I/O space must start from 0.
241 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
243 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
244 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
245 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
246 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
247 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
248 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
251 #define CONFIG_SYS_PCI2_MEM_BUS 0xC0000000
252 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS
253 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
254 #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
255 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
256 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
260 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
261 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
262 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
263 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
264 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
265 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
269 #if !defined(CONFIG_PCI_PNP)
270 #define PCI_ENET0_IOADDR 0xe0000000
271 #define PCI_ENET0_MEMADDR 0xe0000000
272 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
275 #if defined(CONFIG_PCI)
277 #define CONFIG_NET_MULTI
278 #define CONFIG_PCI_PNP /* do pci plug-and-play */
280 #undef CONFIG_EEPRO100
283 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
285 #endif /* CONFIG_PCI */
287 #if defined(CONFIG_TSEC_ENET)
289 #ifndef CONFIG_NET_MULTI
290 #define CONFIG_NET_MULTI 1
293 #define CONFIG_MII 1 /* MII PHY management */
294 #define CONFIG_TSEC1 1
295 #define CONFIG_TSEC1_NAME "eTSEC0"
296 #define CONFIG_TSEC2 1
297 #define CONFIG_TSEC2_NAME "eTSEC1"
298 #define CONFIG_TSEC3 1
299 #define CONFIG_TSEC3_NAME "eTSEC2"
300 #define CONFIG_TSEC4 1
301 #define CONFIG_TSEC4_NAME "eTSEC3"
302 #undef CONFIG_MPC85XX_FEC
304 #define TSEC1_PHY_ADDR 0
305 #define TSEC2_PHY_ADDR 1
306 #define TSEC3_PHY_ADDR 2
307 #define TSEC4_PHY_ADDR 3
309 #define TSEC1_PHYIDX 0
310 #define TSEC2_PHYIDX 0
311 #define TSEC3_PHYIDX 0
312 #define TSEC4_PHYIDX 0
313 #define TSEC1_FLAGS TSEC_GIGABIT
314 #define TSEC2_FLAGS TSEC_GIGABIT
315 #define TSEC3_FLAGS TSEC_GIGABIT
316 #define TSEC4_FLAGS TSEC_GIGABIT
318 /* Options are: eTSEC[0-3] */
319 #define CONFIG_ETHPRIME "eTSEC2"
320 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
321 #endif /* CONFIG_TSEC_ENET */
326 #define CONFIG_ENV_IS_IN_FLASH 1
327 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
328 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
329 #define CONFIG_ENV_SIZE 0x2000
331 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
332 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
337 #define CONFIG_BOOTP_BOOTFILESIZE
338 #define CONFIG_BOOTP_BOOTPATH
339 #define CONFIG_BOOTP_GATEWAY
340 #define CONFIG_BOOTP_HOSTNAME
344 * Command line configuration.
346 #include <config_cmd_default.h>
348 #define CONFIG_CMD_PING
349 #define CONFIG_CMD_I2C
350 #define CONFIG_CMD_MII
352 #if defined(CONFIG_PCI)
353 #define CONFIG_CMD_PCI
357 #undef CONFIG_WATCHDOG /* watchdog disabled */
360 * Miscellaneous configurable options
362 #define CONFIG_SYS_LONGHELP /* undef to save memory */
363 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
364 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
365 #if defined(CONFIG_CMD_KGDB)
366 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
368 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
370 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
371 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
372 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
373 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
376 * For booting Linux, the board info and command line data
377 * have to be in the first 8 MB of memory, since this is
378 * the maximum mapped by the Linux kernel during initialization.
380 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
383 * Internal Definitions
387 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
388 #define BOOTFLAG_WARM 0x02 /* Software reboot */
390 #if defined(CONFIG_CMD_KGDB)
391 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
392 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
396 * Environment Configuration
399 /* The mac addresses for all ethernet interface */
400 #if defined(CONFIG_TSEC_ENET)
401 #define CONFIG_HAS_ETH0
402 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
403 #define CONFIG_HAS_ETH1
404 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
405 #define CONFIG_HAS_ETH2
406 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
407 #define CONFIG_HAS_ETH3
408 #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
411 #define CONFIG_IPADDR 10.101.43.142
413 #define CONFIG_HOSTNAME atum
414 #define CONFIG_ROOTPATH /nfsroot
415 #define CONFIG_BOOTFILE /tftpboot/uImage.atum
416 #define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */
418 #define CONFIG_SERVERIP 10.101.43.10
419 #define CONFIG_GATEWAYIP 10.101.45.1
420 #define CONFIG_NETMASK 255.255.248.0
422 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
424 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
425 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
427 #define CONFIG_BAUDRATE 115200
429 #define CONFIG_NFSBOOTCOMMAND \
430 "setenv bootargs root=/dev/nfs rw " \
431 "nfsroot=$serverip:$rootpath " \
432 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
433 "console=$consoledev,$baudrate $othbootargs;" \
434 "tftp $loadaddr $bootfile;" \
435 "tftp $dtbaddr $dtbfile;" \
436 "bootm $loadaddr - $dtbaddr"
439 #define CONFIG_RAMBOOTCOMMAND \
440 "setenv bootargs root=/dev/ram rw " \
441 "console=$consoledev,$baudrate $othbootargs;" \
442 "tftp $ramdiskaddr $ramdiskfile;" \
443 "tftp $loadaddr $bootfile;" \
444 "tftp $dtbaddr $dtbfile;" \
445 "bootm $loadaddr $ramdiskaddr $dtbaddr"
447 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
449 #endif /* __CONFIG_H */