2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_APCG405 1 /* ...on a APC405 board */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
43 #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
45 #define CONFIG_BOARD_TYPES 1 /* support board types */
47 #define CONFIG_BAUDRATE 9600
48 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
50 #undef CONFIG_BOOTARGS
51 #define CONFIG_RAMBOOTCOMMAND \
52 "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \
53 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
54 "bootm ffc00000 ffca0000"
55 #define CONFIG_NFSBOOTCOMMAND \
56 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
59 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
61 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
62 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
64 #define CONFIG_MII 1 /* MII PHY management */
65 #define CONFIG_PHY_ADDR 0 /* PHY address */
66 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
68 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
72 * Command line configuration.
74 #include <config_cmd_default.h>
76 #define CONFIG_CMD_DHCP
77 #define CONFIG_CMD_PCI
78 #define CONFIG_CMD_IRQ
79 #define CONFIG_CMD_IDE
80 #define CONFIG_CMD_FAT
81 #define CONFIG_CMD_ELF
82 #define CONFIG_CMD_DATE
83 #define CONFIG_CMD_I2C
84 #define CONFIG_CMD_MII
85 #define CONFIG_CMD_PING
86 #define CONFIG_CMD_EEPROM
88 #define CONFIG_MAC_PARTITION
89 #define CONFIG_DOS_PARTITION
91 #define CONFIG_SUPPORT_VFAT
93 #undef CONFIG_WATCHDOG /* watchdog disabled */
95 #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
96 #define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
98 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
101 * Miscellaneous configurable options
103 #define CFG_LONGHELP /* undef to save memory */
104 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
106 #undef CFG_HUSH_PARSER /* use "hush" command parser */
107 #ifdef CFG_HUSH_PARSER
108 #define CFG_PROMPT_HUSH_PS2 "> "
111 #if defined(CONFIG_CMD_KGDB)
112 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
114 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
116 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
117 #define CFG_MAXARGS 16 /* max number of command args */
118 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
120 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
122 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
124 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
125 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
127 #if 1 /* test-only */
128 #define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
130 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
131 #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
132 #define CFG_BASE_BAUD 691200
135 /* The following table includes the supported baudrates */
136 #define CFG_BAUDRATE_TABLE \
137 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
138 57600, 115200, 230400, 460800, 921600 }
140 #define CFG_LOAD_ADDR 0x100000 /* default load address */
141 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
143 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
145 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
147 /* Only interrupt boot if space is pressed */
148 /* If a long serial cable is connected but */
149 /* other end is dead, garbage will be read */
150 #define CONFIG_AUTOBOOT_KEYED 1
151 #define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
152 #define CONFIG_AUTOBOOT_DELAY_STR "d"
153 #define CONFIG_AUTOBOOT_STOP_STR " "
155 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
157 #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
159 /*-----------------------------------------------------------------------
161 *-----------------------------------------------------------------------
163 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
164 #define PCI_HOST_FORCE 1 /* configure as pci host */
165 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
167 #define CONFIG_PCI /* include pci support */
168 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
169 #define CONFIG_PCI_PNP /* do pci plug-and-play */
170 /* resource configuration */
172 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
174 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
176 #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
177 #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
178 #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
179 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
180 #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
181 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
182 #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
183 #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
184 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
186 /*-----------------------------------------------------------------------
188 *-----------------------------------------------------------------------
190 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
191 #undef CONFIG_IDE_LED /* no led for ide supported */
192 #define CONFIG_IDE_RESET 1 /* reset for ide supported */
194 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
195 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
197 #define CFG_ATA_BASE_ADDR 0xF0100000
198 #define CFG_ATA_IDE0_OFFSET 0x0000
200 #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
201 #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
202 #define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
204 /*-----------------------------------------------------------------------
205 * Start addresses for the final memory configuration
206 * (Set up by the startup code)
207 * Please note that CFG_SDRAM_BASE _must_ start at 0
209 #define CFG_SDRAM_BASE 0x00000000
210 #define CFG_MONITOR_BASE 0xFFF80000
211 #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
212 #define CFG_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */
215 * For booting Linux, the board info and command line data
216 * have to be in the first 8 MB of memory, since this is
217 * the maximum mapped by the Linux kernel during initialization.
219 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
221 /*-----------------------------------------------------------------------
224 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
225 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
226 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
227 #undef CFG_FLASH_PROTECTION /* don't use hardware protection */
228 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
229 #define CFG_FLASH_BASE 0xFE000000 /* test-only...*/
230 #define CFG_FLASH_INCREMENT 0x01000000 /* test-only */
232 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
234 #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
235 #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */
237 /*-----------------------------------------------------------------------
238 * Environment Variable setup
240 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
241 #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
242 #define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
243 /* total size of a CAT24WC16 is 2048 bytes */
245 #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
246 #define CFG_NVRAM_SIZE 242 /* NVRAM size */
248 /*-----------------------------------------------------------------------
249 * I2C EEPROM (CAT24WC16) for environment
251 #define CONFIG_HARD_I2C /* I2c with hardware support */
252 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
253 #define CFG_I2C_SLAVE 0x7F
255 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
256 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
257 /* mask of address bits that overflow into the "EEPROM chip address" */
258 #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
259 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
260 /* 16 byte page write mode using*/
261 /* last 4 bits of the address */
262 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
263 #define CFG_EEPROM_PAGE_WRITE_ENABLE
265 /*-----------------------------------------------------------------------
266 * Cache Configuration
268 #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
269 /* have only 8kB, 16kB is save here */
270 #define CFG_CACHELINE_SIZE 32 /* ... */
271 #if defined(CONFIG_CMD_KGDB)
272 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
275 /*-----------------------------------------------------------------------
276 * External Bus Controller (EBC) Setup
278 #define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
279 #define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
280 #define CAN_BA 0xF0000000 /* CAN Base Address */
281 #define DUART0_BA 0xF0000400 /* DUART Base Address */
282 #define DUART1_BA 0xF0000408 /* DUART Base Address */
283 #define RTC_BA 0xF0000500 /* RTC Base Address */
284 #define PS2_BA 0xF0000600 /* PS/2 Base Address */
285 #define CF_BA 0xF0100000 /* CompactFlash Base Address */
286 #define FPGA_BA 0xF0100100 /* FPGA internal Base Address */
287 #define FUJI_BA 0xF0100200 /* Fuji internal Base Address */
288 #define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */
289 #define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */
290 #define VGA_BA 0xF1000000 /* Epson VGA Base Address */
292 #define CFG_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */
294 /* Memory Bank 0 (Flash Bank 0) initialization */
295 #define CFG_EBC_PB0AP 0x92015480
296 #define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
298 /* Memory Bank 1 (Flash Bank 1) initialization */
299 #define CFG_EBC_PB1AP 0x92015480
300 #define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
302 /* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization */
303 #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
304 #define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
306 /* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
307 #define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
308 #define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
310 /* Memory Bank 4 (PCMCIA Slot 1) initialization */
311 #define CFG_EBC_PB4AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
312 #define CFG_EBC_PB4CR PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
314 /* Memory Bank 5 (Epson VGA) initialization */
315 #define CFG_EBC_PB5AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
316 #define CFG_EBC_PB5CR VGA_BA | 0x5A000 /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
318 /* Memory Bank 6 (PCMCIA Slot 2) initialization */
319 #define CFG_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
320 #define CFG_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
322 /*-----------------------------------------------------------------------
326 /* FPGA internal regs */
327 #define CFG_FPGA_CTRL 0x008
328 #define CFG_FPGA_CTRL2 0x00a
330 /* FPGA Control Reg */
331 #define CFG_FPGA_CTRL_CF_RESET 0x0001
332 #define CFG_FPGA_CTRL_WDI 0x0002
333 #define CFG_FPGA_CTRL_PS2_RESET 0x0020
335 #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
336 #define CFG_FPGA_MAX_SIZE 80*1024 /* 80kByte is enough for XC2S50 */
338 /* FPGA program pin configuration */
339 #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
340 #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
341 #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
342 #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
343 #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
345 /*-----------------------------------------------------------------------
349 #define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
350 #define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
352 #define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */
354 /* Image information... */
355 #define CONFIG_LCD_USED CONFIG_LCD_BIG
356 #define CFG_LCD_HEADER_NAME "../common/s1d13806_640_480_16bpp.h"
357 #define CFG_LCD_LOGO_NAME "logo_640_480_24bpp.c"
359 #define CFG_LCD_MEM CFG_LCD_BIG_MEM
360 #define CFG_LCD_REG CFG_LCD_BIG_REG
362 #define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
364 /*-----------------------------------------------------------------------
365 * Definitions for initial stack pointer and data area (in data cache)
368 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
369 #define CFG_TEMP_STACK_OCM 1
371 /* On Chip Memory location */
372 #define CFG_OCM_DATA_ADDR 0xF8000000
373 #define CFG_OCM_DATA_SIZE 0x1000
375 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
376 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
377 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
378 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
379 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
382 * Internal Definitions
386 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
387 #define BOOTFLAG_WARM 0x02 /* Software reboot */
389 #endif /* __CONFIG_H */