2 * (C) Copyright 2001, 2002, 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* ------------------------------------------------------------------------- */
26 * Configuration settings for the A-3000 board (Artis Microsystems Inc.).
27 * http://artismicro.com
30 /* ------------------------------------------------------------------------- */
33 * board/config.h - configuration options, board specific
40 * High Level Configuration Options
44 #define CONFIG_MPC824X 1
45 #define CONFIG_MPC8245 1
46 #define CONFIG_A3000 1
49 #define CONFIG_CONS_INDEX 1
50 #define CONFIG_BAUDRATE 9600
51 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
53 #define CONFIG_BOOTDELAY 5
57 * Command line configuration.
59 #include <config_cmd_default.h>
63 * Miscellaneous configurable options
65 #undef CFG_LONGHELP /* undef to save memory */
66 #define CFG_PROMPT "A3000> " /* Monitor Command Prompt */
67 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
71 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
72 #define CFG_MAXARGS 8 /* Max number of command args */
73 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
74 #define CFG_LOAD_ADDR 0x00400000 /* Default load address */
76 /*-----------------------------------------------------------------------
78 *-----------------------------------------------------------------------
80 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
81 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
82 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
83 #define CFG_I2C_SLAVE 0x7F
85 /*-----------------------------------------------------------------------
87 *-----------------------------------------------------------------------
89 #define CONFIG_PCI /* include pci support */
91 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
93 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
95 /* #define CONFIG_TULIP */
96 /* #define CONFIG_EEPRO100 */
97 #define CONFIG_NATSEMI
99 #define PCI_ENET0_IOADDR 0x80000000
100 #define PCI_ENET0_MEMADDR 0x80000000
101 #define PCI_ENET1_IOADDR 0x81000000
102 #define PCI_ENET1_MEMADDR 0x81000000
103 #define PCI_ENET2_IOADDR 0x82000000
104 #define PCI_ENET2_MEMADDR 0x82000000
105 #define PCI_ENET3_IOADDR 0x83000000
106 #define PCI_ENET3_MEMADDR 0x83000000
109 /*-----------------------------------------------------------------------
110 * Start addresses for the final memory configuration
111 * (Set up by the startup code)
112 * Please note that CFG_SDRAM_BASE _must_ start at 0
114 #define CFG_SDRAM_BASE 0x00000000
116 #define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */
117 #define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
118 #define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM
119 #define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM }
121 /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
122 * reset vector is actually located at FFB00100, but the 8245
125 #define CFG_RESET_ADDRESS 0xFFF00100
127 #define CFG_EUMB_ADDR 0xFC000000
129 #define CFG_MONITOR_BASE TEXT_BASE
130 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
131 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
133 #define CFG_MEMTEST_START 0x00004000 /* memtest works on */
134 #define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
136 /* Maximum amount of RAM.
138 #define CFG_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */
141 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
148 * NS16550 Configuration
151 #define CFG_NS16550_SERIAL
153 #define CFG_NS16550_REG_SIZE 1
155 #define CFG_NS16550_CLK get_bus_freq(0)
157 #define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
158 #define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
160 /*-----------------------------------------------------------------------
161 * Definitions for initial stack pointer and data area
164 /* #define CFG_MONITOR_BASE TEXT_BASE */
165 /*#define CFG_GBL_DATA_SIZE 256*/
166 #define CFG_GBL_DATA_SIZE 128
167 #define CFG_INIT_RAM_ADDR 0x40000000
168 #define CFG_INIT_RAM_END 0x1000
169 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
173 * Low Level Configuration Settings
174 * (address mappings, register initial values, etc.)
175 * You should know what you are doing if you make changes here.
176 * For the detail description refer to the MPC8240 user's manual.
179 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
182 /* Bit-field values for MCCR1.
185 #define CFG_ROMFAL 11
186 #define CFG_DBUS_SIZE 0x3
188 /* Bit-field values for MCCR2.
190 #define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */
191 #define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
193 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
195 #define CFG_BSTOPRE 121
197 /* Bit-field values for MCCR3.
199 #define CFG_REFREC 8 /* Refresh to activate interval */
201 /* Bit-field values for MCCR4.
203 #define CFG_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */
204 #define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
205 #define CFG_ACTORW 3 /* FIXME was 2 */
206 #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
207 #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
208 #define CFG_REGISTERD_TYPE_BUFFER 1
210 #define CFG_REGDIMM 0
212 #define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
214 #define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
216 /* Memory bank settings.
217 * Only bits 20-29 are actually used from these vales to set the
218 * start/end addresses. The upper two bits will always be 0, and the lower
219 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
220 * address. Refer to the MPC8240 book.
223 #define CFG_BANK0_START 0x00000000
224 #define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
225 #define CFG_BANK0_ENABLE 1
226 #define CFG_BANK1_START 0x3ff00000
227 #define CFG_BANK1_END 0x3fffffff
228 #define CFG_BANK1_ENABLE 0
229 #define CFG_BANK2_START 0x3ff00000
230 #define CFG_BANK2_END 0x3fffffff
231 #define CFG_BANK2_ENABLE 0
232 #define CFG_BANK3_START 0x3ff00000
233 #define CFG_BANK3_END 0x3fffffff
234 #define CFG_BANK3_ENABLE 0
235 #define CFG_BANK4_START 0x3ff00000
236 #define CFG_BANK4_END 0x3fffffff
237 #define CFG_BANK4_ENABLE 0
238 #define CFG_BANK5_START 0x3ff00000
239 #define CFG_BANK5_END 0x3fffffff
240 #define CFG_BANK5_ENABLE 0
241 #define CFG_BANK6_START 0x3ff00000
242 #define CFG_BANK6_END 0x3fffffff
243 #define CFG_BANK6_ENABLE 0
244 #define CFG_BANK7_START 0x3ff00000
245 #define CFG_BANK7_END 0x3fffffff
246 #define CFG_BANK7_ENABLE 0
248 #define CFG_ODCR 0xff
250 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
251 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
253 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
254 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
256 #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
257 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
259 #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
260 #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
262 #define CFG_DBAT0L CFG_IBAT0L
263 #define CFG_DBAT0U CFG_IBAT0U
264 #define CFG_DBAT1L CFG_IBAT1L
265 #define CFG_DBAT1U CFG_IBAT1U
266 #define CFG_DBAT2L CFG_IBAT2L
267 #define CFG_DBAT2U CFG_IBAT2U
268 #define CFG_DBAT3L CFG_IBAT3L
269 #define CFG_DBAT3U CFG_IBAT3U
272 * For booting Linux, the board info and command line data
273 * have to be in the first 8 MB of memory, since this is
274 * the maximum mapped by the Linux kernel during initialization.
276 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
278 /*-----------------------------------------------------------------------
281 #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
282 #define CFG_MAX_FLASH_SECT 128 /* Max number of sectors per flash */
284 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
285 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
288 /* Warining: environment is not EMBEDDED in the U-Boot code.
289 * It's stored in flash separately.
291 #define CFG_ENV_IS_IN_FLASH 1
292 #define CFG_ENV_ADDR 0xFFFE0000
293 #define CFG_ENV_SIZE 0x00020000 /* Size of the Environment */
294 #define CFG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */
296 /*-----------------------------------------------------------------------
297 * Cache Configuration
299 #define CFG_CACHELINE_SIZE 32
300 #if defined(CONFIG_CMD_KGDB)
301 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
305 * Internal Definitions
309 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
310 #define BOOTFLAG_WARM 0x02 /* Software reboot */
312 #endif /* __CONFIG_H */