1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
12 * Structure for the cache controller
15 phys_addr_t base; /* Base physical address of cache device. */
20 * get_info() - Get basic cache info
22 * @dev: Device to check (UCLASS_CACHE)
23 * @info: Place to put info
24 * @return 0 if OK, -ve on error
26 int (*get_info)(struct udevice *dev, struct cache_info *info);
29 * enable() - Enable cache
31 * @dev: Device to check (UCLASS_CACHE)
32 * @return 0 if OK, -ve on error
34 int (*enable)(struct udevice *dev);
37 * disable() - Flush and disable cache
39 * @dev: Device to check (UCLASS_CACHE)
40 * @return 0 if OK, -ve on error
42 int (*disable)(struct udevice *dev);
45 #define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
48 * cache_get_info() - Get information about a cache controller
50 * @dev: Device to check (UCLASS_CACHE)
51 * @info: Returns cache info
52 * Return: 0 if OK, -ve on error
54 int cache_get_info(struct udevice *dev, struct cache_info *info);
57 * cache_enable() - Enable cache
59 * @dev: Device to check (UCLASS_CACHE)
60 * Return: 0 if OK, -ve on error
62 int cache_enable(struct udevice *dev);
65 * cache_disable() - Flush and disable cache
67 * @dev: Device to check (UCLASS_CACHE)
68 * Return: 0 if OK, -ve on error
70 int cache_disable(struct udevice *dev);