1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
10 * Structure for the cache controller
13 phys_addr_t base; /* Base physical address of cache device. */
18 * get_info() - Get basic cache info
20 * @dev: Device to check (UCLASS_CACHE)
21 * @info: Place to put info
22 * @return 0 if OK, -ve on error
24 int (*get_info)(struct udevice *dev, struct cache_info *info);
27 * enable() - Enable cache
29 * @dev: Device to check (UCLASS_CACHE)
30 * @return 0 if OK, -ve on error
32 int (*enable)(struct udevice *dev);
35 * disable() - Flush and disable cache
37 * @dev: Device to check (UCLASS_CACHE)
38 * @return 0 if OK, -ve on error
40 int (*disable)(struct udevice *dev);
43 #define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
46 * cache_get_info() - Get information about a cache controller
48 * @dev: Device to check (UCLASS_CACHE)
49 * @info: Returns cache info
50 * @return 0 if OK, -ve on error
52 int cache_get_info(struct udevice *dev, struct cache_info *info);
55 * cache_enable() - Enable cache
57 * @dev: Device to check (UCLASS_CACHE)
58 * @return 0 if OK, -ve on error
60 int cache_enable(struct udevice *dev);
63 * cache_disable() - Flush and disable cache
65 * @dev: Device to check (UCLASS_CACHE)
66 * @return 0 if OK, -ve on error
68 int cache_disable(struct udevice *dev);