1 #ifndef _ASM_CPU_SH7710_H_
2 #define _ASM_CPU_SH7710_H_
4 #define CACHE_OC_NUM_WAYS 4
5 #define CCR_CACHE_INIT 0x0000000D
7 /* MMU and Cache control */
8 #define MMUCR 0xFFFFFFE0
12 #define PACR 0xA4050100
13 #define PBCR 0xA4050102
14 #define PCCR 0xA4050104
15 #define PETCR 0xA4050106
17 /* Port Data Registers */
18 #define PADR 0xA4050120
19 #define PBDR 0xA4050122
20 #define PCDR 0xA4050124
23 #define CMNCR 0xA4FD0000
24 #define CS0BCR 0xA4FD0004
25 #define CS2BCR 0xA4FD0008
26 #define CS3BCR 0xA4FD000C
27 #define CS4BCR 0xA4FD0010
28 #define CS5ABCR 0xA4FD0014
29 #define CS5BBCR 0xA4FD0018
30 #define CS6ABCR 0xA4FD001C
31 #define CS6BBCR 0xA4FD0020
32 #define CS0WCR 0xA4FD0024
33 #define CS2WCR 0xA4FD0028
34 #define CS3WCR 0xA4FD002C
35 #define CS4WCR 0xA4FD0030
36 #define CS5AWCR 0xA4FD0034
37 #define CS5BWCR 0xA4FD0038
38 #define CS6AWCR 0xA4FD003C
39 #define CS6BWCR 0xA4FD0040
41 /* SDRAM controller */
42 #define SDCR 0xA4FD0044
43 #define RTCSR 0xA4FD0048
44 #define RTCNT 0xA4FD004C
45 #define RTCOR 0xA4FD0050
48 #define SCSMR_0 0xA4400000
49 #define SCIF0_BASE SCSMR_0
50 #define SCSMR_0 0xA4410000
51 #define SCIF1_BASE SCSMR_1
54 #define TSTR0 0xA412FE92
56 #define TCNT0 0xa412FE98
57 #define TCR0 0xa412FE9C
59 /* On chip oscillator circuits */
60 #define FRQCR 0xA415FF80
61 #define WTCNT 0xA415FF84
62 #define WTCSR 0xA415FF86
64 #endif /* _ASM_CPU_SH7710_H_ */