2 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
5 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #ifndef _PPC4xx_UIC_H_
27 #define _PPC4xx_UIC_H_
30 * Define the number of UIC's
32 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
33 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
36 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
39 #elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
40 defined(CONFIG_440EP) || defined(CONFIG_440GR)
46 #define IRQ_MAX UIC_MAX * 32
51 #define UIC_SR 0x0 /* UIC status */
52 #define UIC_ER 0x2 /* UIC enable */
53 #define UIC_CR 0x3 /* UIC critical */
54 #define UIC_PR 0x4 /* UIC polarity */
55 #define UIC_TR 0x5 /* UIC triggering */
56 #define UIC_MSR 0x6 /* UIC masked status */
57 #define UIC_VR 0x7 /* UIC vector */
58 #define UIC_VCR 0x8 /* UIC vector configuration */
61 * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's
62 * are cascaded on. With this trick we can use the common UIC code for 440GX
65 #if defined(CONFIG_440GX)
66 #define UIC0_DCR_BASE 0x200
67 #define UIC1_DCR_BASE 0xc0
68 #define UIC2_DCR_BASE 0xd0
69 #define UIC3_DCR_BASE 0x210
71 #define UIC0_DCR_BASE 0xc0
72 #define UIC1_DCR_BASE 0xd0
73 #define UIC2_DCR_BASE 0xe0
74 #define UIC3_DCR_BASE 0xf0
77 #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
78 #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
79 #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
80 #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
81 #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
82 #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
83 #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
84 #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
86 #define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
87 #define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
88 #define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
89 #define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
90 #define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
91 #define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
92 #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
93 #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
95 #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
96 #define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
97 #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
98 #define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
99 #define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
100 #define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
101 #define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
102 #define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
103 #define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
105 #define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
106 #define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
107 #define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
108 #define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
109 #define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
110 #define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
111 #define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
112 #define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
113 #define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
115 /* The following is for compatibility with 405 code */
121 #define uicmsr uic0msr
123 #define uicvcr uic0vcr
126 * Now the interrupt vector definitions. They are different for most of
127 * the 4xx variants, so we need some more #ifdef's here. No mask
128 * definitions anymore here. For this please use the UIC_MASK macro below.
130 * Note: Please only define the interrupts really used in U-Boot here.
131 * Those are the cascading and EMAC/MAL related interrupt.
134 #if defined(CONFIG_405EP) || defined(CONFIG_405GP)
135 #define VECNUM_MAL_SERR 10
136 #define VECNUM_MAL_TXEOB 11
137 #define VECNUM_MAL_RXEOB 12
138 #define VECNUM_MAL_TXDE 13
139 #define VECNUM_MAL_RXDE 14
140 #define VECNUM_ETH0 15
141 #define VECNUM_ETH1_OFFS 2
142 #define VECNUM_EIRQ6 29
143 #endif /* defined(CONFIG_405EP) */
145 #if defined(CONFIG_405EZ)
146 #define VECNUM_USBDEV 15
147 #define VECNUM_ETH0 16
148 #define VECNUM_MAL_SERR 18
149 #define VECNUM_MAL_TXDE 18
150 #define VECNUM_MAL_RXDE 18
151 #define VECNUM_MAL_TXEOB 19
152 #define VECNUM_MAL_RXEOB 21
153 #endif /* CONFIG_405EX */
155 #if defined(CONFIG_405EX)
157 #define VECNUM_MAL_TXEOB 10
158 #define VECNUM_MAL_RXEOB 11
159 #define VECNUM_ETH0 24
160 #define VECNUM_ETH1_OFFS 1
161 #define VECNUM_UIC2NCI 28
162 #define VECNUM_UIC2CI 29
163 #define VECNUM_UIC1NCI 30
164 #define VECNUM_UIC1CI 31
167 #define VECNUM_MAL_SERR (32 + 0)
168 #define VECNUM_MAL_TXDE (32 + 1)
169 #define VECNUM_MAL_RXDE (32 + 2)
170 #endif /* CONFIG_405EX */
172 #if defined(CONFIG_440GP) || \
173 defined(CONFIG_440EP) || defined(CONFIG_440GR)
175 #define VECNUM_MAL_TXEOB 10
176 #define VECNUM_MAL_RXEOB 11
177 #define VECNUM_UIC1NCI 30
178 #define VECNUM_UIC1CI 31
181 #define VECNUM_MAL_SERR (32 + 0)
182 #define VECNUM_MAL_TXDE (32 + 1)
183 #define VECNUM_MAL_RXDE (32 + 2)
184 #define VECNUM_USBDEV (32 + 23)
185 #define VECNUM_ETH0 (32 + 28)
186 #define VECNUM_ETH1_OFFS 2
187 #endif /* CONFIG_440GP */
189 #if defined(CONFIG_440GX)
190 /* UICB 0 (440GX only) */
192 * All those defines below are off-by-one, so that the common UIC code
193 * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc.
195 #define VECNUM_UIC1CI 0
196 #define VECNUM_UIC1NCI 1
197 #define VECNUM_UIC2CI 2
198 #define VECNUM_UIC2NCI 3
199 #define VECNUM_UIC3CI 4
200 #define VECNUM_UIC3NCI 5
202 /* UIC 0, used as UIC1 on 440GX because of UICB0 */
203 #define VECNUM_MAL_TXEOB (32 + 10)
204 #define VECNUM_MAL_RXEOB (32 + 11)
206 /* UIC 1, used as UIC2 on 440GX because of UICB0 */
207 #define VECNUM_MAL_SERR (64 + 0)
208 #define VECNUM_MAL_TXDE (64 + 1)
209 #define VECNUM_MAL_RXDE (64 + 2)
210 #define VECNUM_ETH0 (64 + 28)
211 #define VECNUM_ETH1_OFFS 2
212 #endif /* CONFIG_440GX */
214 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
216 #define VECNUM_MAL_TXEOB 10
217 #define VECNUM_MAL_RXEOB 11
218 #define VECNUM_USBDEV 20
219 #define VECNUM_ETH0 24
220 #define VECNUM_ETH1_OFFS 1
221 #define VECNUM_UIC2NCI 28
222 #define VECNUM_UIC2CI 29
223 #define VECNUM_UIC1NCI 30
224 #define VECNUM_UIC1CI 31
227 #define VECNUM_MAL_SERR (32 + 0)
228 #define VECNUM_MAL_TXDE (32 + 1)
229 #define VECNUM_MAL_RXDE (32 + 2)
232 #define VECNUM_EIRQ2 (64 + 3)
233 #endif /* CONFIG_440EPX */
235 #if defined(CONFIG_440SP)
237 #define VECNUM_UIC1NCI 30
238 #define VECNUM_UIC1CI 31
241 #define VECNUM_MAL_SERR (32 + 1)
242 #define VECNUM_MAL_TXDE (32 + 2)
243 #define VECNUM_MAL_RXDE (32 + 3)
244 #define VECNUM_MAL_TXEOB (32 + 6)
245 #define VECNUM_MAL_RXEOB (32 + 7)
246 #define VECNUM_ETH0 (32 + 28)
247 #endif /* CONFIG_440SP */
249 #if defined(CONFIG_440SPE)
251 #define VECNUM_UIC2NCI 10
252 #define VECNUM_UIC2CI 11
253 #define VECNUM_UIC3NCI 16
254 #define VECNUM_UIC3CI 17
255 #define VECNUM_UIC1NCI 30
256 #define VECNUM_UIC1CI 31
259 #define VECNUM_MAL_SERR (32 + 1)
260 #define VECNUM_MAL_TXDE (32 + 2)
261 #define VECNUM_MAL_RXDE (32 + 3)
262 #define VECNUM_MAL_TXEOB (32 + 6)
263 #define VECNUM_MAL_RXEOB (32 + 7)
264 #define VECNUM_ETH0 (32 + 28)
265 #endif /* CONFIG_440SPE */
267 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
269 #define VECNUM_UIC2NCI 10
270 #define VECNUM_UIC2CI 11
271 #define VECNUM_UIC3NCI 16
272 #define VECNUM_UIC3CI 17
273 #define VECNUM_UIC1NCI 30
274 #define VECNUM_UIC1CI 31
277 #define VECNUM_MAL_SERR (64 + 3)
278 #define VECNUM_MAL_TXDE (64 + 4)
279 #define VECNUM_MAL_RXDE (64 + 5)
280 #define VECNUM_MAL_TXEOB (64 + 6)
281 #define VECNUM_MAL_RXEOB (64 + 7)
282 #define VECNUM_ETH0 (64 + 16)
283 #define VECNUM_ETH1_OFFS 1
284 #endif /* CONFIG_460EX */
286 #if defined(CONFIG_460SX)
288 #define VECNUM_UIC2NCI 10
289 #define VECNUM_UIC2CI 11
290 #define VECNUM_UIC3NCI 16
291 #define VECNUM_UIC3CI 17
292 #define VECNUM_ETH0 19
293 #define VECNUM_ETH1_OFFS 1
294 #define VECNUM_UIC1NCI 30
295 #define VECNUM_UIC1CI 31
298 #define VECNUM_MAL_SERR (32 + 1)
299 #define VECNUM_MAL_TXDE (32 + 2)
300 #define VECNUM_MAL_RXDE (32 + 3)
301 #define VECNUM_MAL_TXEOB (32 + 6)
302 #define VECNUM_MAL_RXEOB (32 + 7)
303 #endif /* CONFIG_460EX */
305 #if !defined(VECNUM_ETH1_OFFS)
306 #define VECNUM_ETH1_OFFS 1
310 * Mask definitions (used for example in 4xx_enet.c)
312 #define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
313 /* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
314 #define UIC_NR(vec) ((vec) >> 5)
316 #endif /* _PPC4xx_UIC_H_ */