3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef _PPC4xx_SDRAM_H_
25 #define _PPC4xx_SDRAM_H_
27 #if defined(CONFIG_SDRAM_PPC4xx_IBM_SDRAM)
33 * XXX - ToDo: Revisit file to change all these lower case defines into
34 * upper case. Also needs to be done in the controller setup code too
35 * of course. sr, 2008-06-02
38 #define mem_besra 0x00 /* bus error syndrome reg a */
39 #define mem_besrsa 0x04 /* bus error syndrome reg set a */
40 #define mem_besrb 0x08 /* bus error syndrome reg b */
41 #define mem_besrsb 0x0c /* bus error syndrome reg set b */
42 #define mem_bear 0x10 /* bus error address reg */
44 #define mem_mcopt1 0x20 /* memory controller options 1 */
45 #define mem_status 0x24 /* memory status */
46 #define mem_rtr 0x30 /* refresh timer reg */
47 #define mem_pmit 0x34 /* power management idle timer */
48 #define mem_mb0cf 0x40 /* memory bank 0 configuration */
49 #define mem_mb1cf 0x44 /* memory bank 1 configuration */
51 #define mem_mb2cf 0x48 /* memory bank 2 configuration */
52 #define mem_mb3cf 0x4c /* memory bank 3 configuration */
54 #define mem_sdtr1 0x80 /* timing reg 1 */
56 #define mem_ecccf 0x94 /* ECC configuration */
57 #define mem_eccerr 0x98 /* ECC error status */
60 #endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */
62 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
65 * Memory controller registers
67 #define SDRAM_CFG0 0x20 /* memory controller options 0 */
68 #define SDRAM_CFG1 0x21 /* memory controller options 1 */
71 * XXX - ToDo: Revisit file to change all these lower case defines into
72 * upper case. Also needs to be done in the controller setup code too
73 * of course. sr, 2008-06-02
75 #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
76 #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
77 #define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
78 #define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
79 #define mem_bear 0x0010 /* bus error address reg */
80 #define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
81 #define mem_mirq_set 0x0012 /* bus master interrupt (set) */
82 #define mem_slio 0x0018 /* ddr sdram slave interface options */
83 #define mem_cfg0 0x0020 /* ddr sdram options 0 */
84 #define mem_cfg1 0x0021 /* ddr sdram options 1 */
85 #define mem_devopt 0x0022 /* ddr sdram device options */
86 #define mem_mcsts 0x0024 /* memory controller status */
87 #define mem_rtr 0x0030 /* refresh timer register */
88 #define mem_pmit 0x0034 /* power management idle timer */
89 #define mem_uabba 0x0038 /* plb UABus base address */
90 #define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
91 #define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
92 #define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
93 #define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
94 #define mem_tr0 0x0080 /* sdram timing register 0 */
95 #define mem_tr1 0x0081 /* sdram timing register 1 */
96 #define mem_clktr 0x0082 /* ddr clock timing register */
97 #define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
98 #define mem_dlycal 0x0084 /* delay line calibration register */
99 #define mem_eccesr 0x0098 /* ECC error status */
102 * Memory Controller Options 0
104 #define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
105 #define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
106 #define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
107 #define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
108 #define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
109 #define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
110 #define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
111 #define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
112 #define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
113 #define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
114 #define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
115 #define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
118 * Memory Controller Options 1
120 #define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
121 #define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
124 * SDRAM DEVPOT Options
126 #define SDRAM_DEVOPT_DLL 0x80000000
127 #define SDRAM_DEVOPT_DS 0x40000000
130 * SDRAM MCSTS Options
132 #define SDRAM_MCSTS_MRSC 0x80000000
133 #define SDRAM_MCSTS_SRMS 0x40000000
134 #define SDRAM_MCSTS_CIS 0x20000000
137 * SDRAM Refresh Timer Register
139 #define SDRAM_RTR_RINT_MASK 0xFFFF0000
140 #define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
143 * SDRAM UABus Base Address Reg
145 #define SDRAM_UABBA_UBBA_MASK 0x0000000F
148 * Memory Bank 0-7 configuration
150 #define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
151 #define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
152 #define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
153 #define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
154 #define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
155 #define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
156 #define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
157 #define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
158 #define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
159 #define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
160 #define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
161 #define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
162 #define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
163 #define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
164 #define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
169 #define SDRAM_TR0_SDWR_MASK 0x80000000
170 #define SDRAM_TR0_SDWR_2_CLK 0x00000000
171 #define SDRAM_TR0_SDWR_3_CLK 0x80000000
172 #define SDRAM_TR0_SDWD_MASK 0x40000000
173 #define SDRAM_TR0_SDWD_0_CLK 0x00000000
174 #define SDRAM_TR0_SDWD_1_CLK 0x40000000
175 #define SDRAM_TR0_SDCL_MASK 0x01800000
176 #define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
177 #define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
178 #define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
179 #define SDRAM_TR0_SDPA_MASK 0x000C0000
180 #define SDRAM_TR0_SDPA_2_CLK 0x00040000
181 #define SDRAM_TR0_SDPA_3_CLK 0x00080000
182 #define SDRAM_TR0_SDPA_4_CLK 0x000C0000
183 #define SDRAM_TR0_SDCP_MASK 0x00030000
184 #define SDRAM_TR0_SDCP_2_CLK 0x00000000
185 #define SDRAM_TR0_SDCP_3_CLK 0x00010000
186 #define SDRAM_TR0_SDCP_4_CLK 0x00020000
187 #define SDRAM_TR0_SDCP_5_CLK 0x00030000
188 #define SDRAM_TR0_SDLD_MASK 0x0000C000
189 #define SDRAM_TR0_SDLD_1_CLK 0x00000000
190 #define SDRAM_TR0_SDLD_2_CLK 0x00004000
191 #define SDRAM_TR0_SDRA_MASK 0x0000001C
192 #define SDRAM_TR0_SDRA_6_CLK 0x00000000
193 #define SDRAM_TR0_SDRA_7_CLK 0x00000004
194 #define SDRAM_TR0_SDRA_8_CLK 0x00000008
195 #define SDRAM_TR0_SDRA_9_CLK 0x0000000C
196 #define SDRAM_TR0_SDRA_10_CLK 0x00000010
197 #define SDRAM_TR0_SDRA_11_CLK 0x00000014
198 #define SDRAM_TR0_SDRA_12_CLK 0x00000018
199 #define SDRAM_TR0_SDRA_13_CLK 0x0000001C
200 #define SDRAM_TR0_SDRD_MASK 0x00000003
201 #define SDRAM_TR0_SDRD_2_CLK 0x00000001
202 #define SDRAM_TR0_SDRD_3_CLK 0x00000002
203 #define SDRAM_TR0_SDRD_4_CLK 0x00000003
208 #define SDRAM_TR1_RDSS_MASK 0xC0000000
209 #define SDRAM_TR1_RDSS_TR0 0x00000000
210 #define SDRAM_TR1_RDSS_TR1 0x40000000
211 #define SDRAM_TR1_RDSS_TR2 0x80000000
212 #define SDRAM_TR1_RDSS_TR3 0xC0000000
213 #define SDRAM_TR1_RDSL_MASK 0x00C00000
214 #define SDRAM_TR1_RDSL_STAGE1 0x00000000
215 #define SDRAM_TR1_RDSL_STAGE2 0x00400000
216 #define SDRAM_TR1_RDSL_STAGE3 0x00800000
217 #define SDRAM_TR1_RDCD_MASK 0x00000800
218 #define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
219 #define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
220 #define SDRAM_TR1_RDCT_MASK 0x000001FF
221 #define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
222 #define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
223 #define SDRAM_TR1_RDCT_MIN 0x00000000
224 #define SDRAM_TR1_RDCT_MAX 0x000001FF
227 * SDRAM WDDCTR Options
229 #define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
230 #define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
231 #define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
232 #define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
233 #define SDRAM_WDDCTR_DCD_MASK 0x000001FF
236 * SDRAM CLKTR Options
238 #define SDRAM_CLKTR_CLKP_MASK 0xC0000000
239 #define SDRAM_CLKTR_CLKP_0DEG 0x00000000
240 #define SDRAM_CLKTR_CLKP_90DEG 0x40000000
241 #define SDRAM_CLKTR_CLKP_180DEG 0x80000000
242 #define SDRAM_CLKTR_DCDT_MASK 0x000001FF
245 * SDRAM DLYCAL Options
247 #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
248 #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
249 #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
251 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR */
253 #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
255 #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
256 #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
257 #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
260 * Memory queue defines
262 #define SDRAMQ_DCR_BASE 0x040
264 #define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
265 #define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
266 #define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
267 #define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
268 #define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
269 #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
270 #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
271 #define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
272 #define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
273 #define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
274 #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
275 #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
276 #define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
277 #define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
278 #define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
280 #if !defined(CONFIG_405EX)
282 * Memory Bank 0-7 configuration
284 #if defined(CONFIG_440SPE) || \
285 defined(CONFIG_460EX) || defined(CONFIG_460GT)
286 #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
287 #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))
288 #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2)
289 #endif /* CONFIG_440SPE */
290 #if defined(CONFIG_440SP)
291 #define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
292 #define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFF800000))
293 #define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFF800000))
294 #endif /* CONFIG_440SP */
295 #define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
296 #define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((u32)(n))&0x3FF)<<6)
297 #define SDRAM_RXBAS_SDSZ_DECODE(n) ((((u32)(n))>>6)&0x3FF)
298 #define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
299 #define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
300 #define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
301 #define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
302 #define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
303 #define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
304 #define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
305 #define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
306 #define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
307 #define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
308 #define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
309 #else /* CONFIG_405EX */
312 * Revisit this file to check if all these 405EX defines are correct and
313 * can be used in the common 44x_spd_ddr2 code as well. sr, 2008-06-02
315 #define SDRAM_RXBAS_SDSZ_MASK PPC_REG_VAL(19, 0xF)
316 #define SDRAM_RXBAS_SDSZ_4MB PPC_REG_VAL(19, 0x0)
317 #define SDRAM_RXBAS_SDSZ_8MB PPC_REG_VAL(19, 0x1)
318 #define SDRAM_RXBAS_SDSZ_16MB PPC_REG_VAL(19, 0x2)
319 #define SDRAM_RXBAS_SDSZ_32MB PPC_REG_VAL(19, 0x3)
320 #define SDRAM_RXBAS_SDSZ_64MB PPC_REG_VAL(19, 0x4)
321 #define SDRAM_RXBAS_SDSZ_128MB PPC_REG_VAL(19, 0x5)
322 #define SDRAM_RXBAS_SDSZ_256MB PPC_REG_VAL(19, 0x6)
323 #define SDRAM_RXBAS_SDSZ_512MB PPC_REG_VAL(19, 0x7)
324 #define SDRAM_RXBAS_SDSZ_1024MB PPC_REG_VAL(19, 0x8)
325 #define SDRAM_RXBAS_SDSZ_2048MB PPC_REG_VAL(19, 0x9)
326 #define SDRAM_RXBAS_SDSZ_4096MB PPC_REG_VAL(19, 0xA)
327 #define SDRAM_RXBAS_SDSZ_8192MB PPC_REG_VAL(19, 0xB)
328 #define SDRAM_RXBAS_SDSZ_8 SDRAM_RXBAS_SDSZ_8MB
329 #define SDRAM_RXBAS_SDSZ_16 SDRAM_RXBAS_SDSZ_16MB
330 #define SDRAM_RXBAS_SDSZ_32 SDRAM_RXBAS_SDSZ_32MB
331 #define SDRAM_RXBAS_SDSZ_64 SDRAM_RXBAS_SDSZ_64MB
332 #define SDRAM_RXBAS_SDSZ_128 SDRAM_RXBAS_SDSZ_128MB
333 #define SDRAM_RXBAS_SDSZ_256 SDRAM_RXBAS_SDSZ_256MB
334 #define SDRAM_RXBAS_SDSZ_512 SDRAM_RXBAS_SDSZ_512MB
335 #define SDRAM_RXBAS_SDSZ_1024 SDRAM_RXBAS_SDSZ_1024MB
336 #define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB
337 #define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB
338 #define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB
339 #define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0)
340 #define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1)
341 #define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2)
342 #define SDRAM_RXBAS_SDAM_MODE3 PPC_REG_VAL(23, 0x3)
343 #define SDRAM_RXBAS_SDAM_MODE4 PPC_REG_VAL(23, 0x4)
344 #define SDRAM_RXBAS_SDAM_MODE5 PPC_REG_VAL(23, 0x5)
345 #define SDRAM_RXBAS_SDAM_MODE6 PPC_REG_VAL(23, 0x6)
346 #define SDRAM_RXBAS_SDAM_MODE7 PPC_REG_VAL(23, 0x7)
347 #define SDRAM_RXBAS_SDAM_MODE8 PPC_REG_VAL(23, 0x8)
348 #define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9)
349 #define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0)
350 #define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1)
351 #endif /* CONFIG_405EX */
354 * Memory controller registers
356 #define SDRAM_MCSTAT 0x14 /* memory controller status */
357 #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
358 #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
359 #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
360 #define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
361 #define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
362 #define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
363 #define SDRAM_CODT 0x26 /* on die termination for controller */
364 #define SDRAM_VVPR 0x27 /* variable VRef programmming */
365 #define SDRAM_OPARS 0x28 /* on chip driver control setup */
366 #define SDRAM_OPART 0x29 /* on chip driver control trigger */
367 #define SDRAM_RTR 0x30 /* refresh timer */
368 #define SDRAM_PMIT 0x34 /* power management idle timer */
369 #define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
370 #define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
371 #define SDRAM_MB2CF 0x48
372 #define SDRAM_MB3CF 0x4C
373 #define SDRAM_INITPLR0 0x50 /* manual initialization control */
374 #define SDRAM_INITPLR1 0x51 /* manual initialization control */
375 #define SDRAM_INITPLR2 0x52 /* manual initialization control */
376 #define SDRAM_INITPLR3 0x53 /* manual initialization control */
377 #define SDRAM_INITPLR4 0x54 /* manual initialization control */
378 #define SDRAM_INITPLR5 0x55 /* manual initialization control */
379 #define SDRAM_INITPLR6 0x56 /* manual initialization control */
380 #define SDRAM_INITPLR7 0x57 /* manual initialization control */
381 #define SDRAM_INITPLR8 0x58 /* manual initialization control */
382 #define SDRAM_INITPLR9 0x59 /* manual initialization control */
383 #define SDRAM_INITPLR10 0x5a /* manual initialization control */
384 #define SDRAM_INITPLR11 0x5b /* manual initialization control */
385 #define SDRAM_INITPLR12 0x5c /* manual initialization control */
386 #define SDRAM_INITPLR13 0x5d /* manual initialization control */
387 #define SDRAM_INITPLR14 0x5e /* manual initialization control */
388 #define SDRAM_INITPLR15 0x5f /* manual initialization control */
389 #define SDRAM_RQDC 0x70 /* read DQS delay control */
390 #define SDRAM_RFDC 0x74 /* read feedback delay control */
391 #define SDRAM_RDCC 0x78 /* read data capture control */
392 #define SDRAM_DLCR 0x7A /* delay line calibration */
393 #define SDRAM_CLKTR 0x80 /* DDR clock timing */
394 #define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
395 #define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
396 #define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
397 #define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
398 #define SDRAM_MMODE 0x88 /* memory mode */
399 #define SDRAM_MEMODE 0x89 /* memory extended mode */
400 #define SDRAM_ECCCR 0x98 /* ECC error status */
401 #define SDRAM_CID 0xA4 /* core ID */
402 #define SDRAM_RID 0xA8 /* revision ID */
403 #define SDRAM_RTSR 0xB1 /* run time status tracking */
406 * Memory Controller Status
408 #define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
409 #define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
410 #define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
411 #define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */
412 #define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
413 #define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */
414 #define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */
415 #define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */
416 #define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */
419 * Memory Controller Options 1
421 #define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
422 #define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
423 #define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
424 #define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
425 #define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
426 #define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((u32)(n))>>28)&0x3)
427 #define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
428 #define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
429 #define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
430 #define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
431 #define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
432 #define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
433 #define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
434 #define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
435 #define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
436 #define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
437 #define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
438 #define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
439 #define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
440 #define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
441 #define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
442 #define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
443 #define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
444 #define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
445 #define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
446 #define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
447 #define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
448 #define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
449 #define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
450 #define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
451 #define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
452 #define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
453 #define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
454 #define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
455 #define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
458 * Memory Controller Options 2
460 #define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
461 #define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
462 #define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
463 #define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
464 #define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
465 #define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
466 #define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
467 #define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
468 #define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
469 #define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
470 #define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
471 #define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
472 #define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
473 #define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
474 #define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
475 #define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
476 #define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
477 #define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
480 * SDRAM Refresh Timer Register
482 #define SDRAM_RTR_RINT_MASK 0xFFF80000
483 #define SDRAM_RTR_RINT_ENCODE(n) ((((u32)(n))&0xFFF8)<<16)
484 #define SDRAM_RTR_RINT_DECODE(n) ((((u32)(n))>>16)&0xFFF8)
487 * SDRAM Read DQS Delay Control Register
489 #define SDRAM_RQDC_RQDE_MASK 0x80000000
490 #define SDRAM_RQDC_RQDE_DISABLE 0x00000000
491 #define SDRAM_RQDC_RQDE_ENABLE 0x80000000
492 #define SDRAM_RQDC_RQFD_MASK 0x000001FF
493 #define SDRAM_RQDC_RQFD_ENCODE(n) ((((u32)(n))&0x1FF)<<0)
495 #define SDRAM_RQDC_RQFD_MAX 0x1FF
498 * SDRAM Read Data Capture Control Register
500 #define SDRAM_RDCC_RDSS_MASK 0xC0000000
501 #define SDRAM_RDCC_RDSS_T1 0x00000000
502 #define SDRAM_RDCC_RDSS_T2 0x40000000
503 #define SDRAM_RDCC_RDSS_T3 0x80000000
504 #define SDRAM_RDCC_RDSS_T4 0xC0000000
505 #define SDRAM_RDCC_RSAE_MASK 0x00000001
506 #define SDRAM_RDCC_RSAE_DISABLE 0x00000001
507 #define SDRAM_RDCC_RSAE_ENABLE 0x00000000
510 * SDRAM Read Feedback Delay Control Register
512 #define SDRAM_RFDC_ARSE_MASK 0x80000000
513 #define SDRAM_RFDC_ARSE_DISABLE 0x80000000
514 #define SDRAM_RFDC_ARSE_ENABLE 0x00000000
515 #define SDRAM_RFDC_RFOS_MASK 0x007F0000
516 #define SDRAM_RFDC_RFOS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
517 #define SDRAM_RFDC_RFFD_MASK 0x000007FF
518 #define SDRAM_RFDC_RFFD_ENCODE(n) ((((u32)(n))&0x7FF)<<0)
520 #define SDRAM_RFDC_RFFD_MAX 0x7FF
523 * SDRAM Delay Line Calibration Register
525 #define SDRAM_DLCR_DCLM_MASK 0x80000000
526 #define SDRAM_DLCR_DCLM_MANUEL 0x80000000
527 #define SDRAM_DLCR_DCLM_AUTO 0x00000000
528 #define SDRAM_DLCR_DLCR_MASK 0x08000000
529 #define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
530 #define SDRAM_DLCR_DLCR_IDLE 0x00000000
531 #define SDRAM_DLCR_DLCS_MASK 0x07000000
532 #define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
533 #define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
534 #define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
535 #define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
536 #define SDRAM_DLCR_DLCS_ERROR 0x04000000
537 #define SDRAM_DLCR_DLCV_MASK 0x000001FF
538 #define SDRAM_DLCR_DLCV_ENCODE(n) ((((u32)(n))&0x1FF)<<0)
539 #define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF)
542 * SDRAM Controller On Die Termination Register
544 #define SDRAM_CODT_ODT_ON 0x80000000
545 #define SDRAM_CODT_ODT_OFF 0x00000000
546 #define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
547 #define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
548 #define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
549 #define SDRAM_CODT_DQS_MASK 0x00000010
550 #define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
551 #define SDRAM_CODT_DQS_SINGLE_END 0x00000010
552 #define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
553 #define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
554 #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
555 #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
556 #define SDRAM_CODT_IO_HIZ 0x00000000
557 #define SDRAM_CODT_IO_NMODE 0x00000001
560 * SDRAM Mode Register
562 #define SDRAM_MMODE_WR_MASK 0x00000E00
563 #define SDRAM_MMODE_WR_DDR1 0x00000000
564 #define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
565 #define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
566 #define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
567 #define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
568 #define SDRAM_MMODE_DCL_MASK 0x00000070
569 #define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
570 #define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
571 #define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
572 #define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
573 #define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
574 #define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
575 #define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
576 #define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
577 #define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
580 * SDRAM Extended Mode Register
582 #define SDRAM_MEMODE_DIC_MASK 0x00000002
583 #define SDRAM_MEMODE_DIC_NORMAL 0x00000000
584 #define SDRAM_MEMODE_DIC_WEAK 0x00000002
585 #define SDRAM_MEMODE_DLL_MASK 0x00000001
586 #define SDRAM_MEMODE_DLL_DISABLE 0x00000001
587 #define SDRAM_MEMODE_DLL_ENABLE 0x00000000
588 #define SDRAM_MEMODE_RTT_MASK 0x00000044
589 #define SDRAM_MEMODE_RTT_DISABLED 0x00000000
590 #define SDRAM_MEMODE_RTT_75OHM 0x00000004
591 #define SDRAM_MEMODE_RTT_150OHM 0x00000040
592 #define SDRAM_MEMODE_DQS_MASK 0x00000400
593 #define SDRAM_MEMODE_DQS_DISABLE 0x00000400
594 #define SDRAM_MEMODE_DQS_ENABLE 0x00000000
597 * SDRAM Clock Timing Register
599 #define SDRAM_CLKTR_CLKP_MASK 0xC0000000
600 #define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
601 #define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
602 #define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000
603 #define SDRAM_CLKTR_CLKP_270_DEG_ADV 0xC0000000
606 * SDRAM Write Timing Register
608 #define SDRAM_WRDTR_LLWP_MASK 0x10000000
609 #define SDRAM_WRDTR_LLWP_DIS 0x10000000
610 #define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
611 #define SDRAM_WRDTR_WTR_MASK 0x0E000000
612 #define SDRAM_WRDTR_WTR_0_DEG 0x06000000
613 #define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000
614 #define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
615 #define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
618 * SDRAM SDTR1 Options
620 #define SDRAM_SDTR1_LDOF_MASK 0x80000000
621 #define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
622 #define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
623 #define SDRAM_SDTR1_RTW_MASK 0x00F00000
624 #define SDRAM_SDTR1_RTW_2_CLK 0x00200000
625 #define SDRAM_SDTR1_RTW_3_CLK 0x00300000
626 #define SDRAM_SDTR1_WTWO_MASK 0x000F0000
627 #define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
628 #define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
629 #define SDRAM_SDTR1_RTRO_MASK 0x0000F000
630 #define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
631 #define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
634 * SDRAM SDTR2 Options
636 #define SDRAM_SDTR2_RCD_MASK 0xF0000000
637 #define SDRAM_SDTR2_RCD_1_CLK 0x10000000
638 #define SDRAM_SDTR2_RCD_2_CLK 0x20000000
639 #define SDRAM_SDTR2_RCD_3_CLK 0x30000000
640 #define SDRAM_SDTR2_RCD_4_CLK 0x40000000
641 #define SDRAM_SDTR2_RCD_5_CLK 0x50000000
642 #define SDRAM_SDTR2_WTR_MASK 0x0F000000
643 #define SDRAM_SDTR2_WTR_1_CLK 0x01000000
644 #define SDRAM_SDTR2_WTR_2_CLK 0x02000000
645 #define SDRAM_SDTR2_WTR_3_CLK 0x03000000
646 #define SDRAM_SDTR2_WTR_4_CLK 0x04000000
647 #define SDRAM_SDTR3_WTR_ENCODE(n) ((((u32)(n))&0xF)<<24)
648 #define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
649 #define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
650 #define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
651 #define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
652 #define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
653 #define SDRAM_SDTR2_WPC_MASK 0x0000F000
654 #define SDRAM_SDTR2_WPC_2_CLK 0x00002000
655 #define SDRAM_SDTR2_WPC_3_CLK 0x00003000
656 #define SDRAM_SDTR2_WPC_4_CLK 0x00004000
657 #define SDRAM_SDTR2_WPC_5_CLK 0x00005000
658 #define SDRAM_SDTR2_WPC_6_CLK 0x00006000
659 #define SDRAM_SDTR3_WPC_ENCODE(n) ((((u32)(n))&0xF)<<12)
660 #define SDRAM_SDTR2_RPC_MASK 0x00000F00
661 #define SDRAM_SDTR2_RPC_2_CLK 0x00000200
662 #define SDRAM_SDTR2_RPC_3_CLK 0x00000300
663 #define SDRAM_SDTR2_RPC_4_CLK 0x00000400
664 #define SDRAM_SDTR2_RP_MASK 0x000000F0
665 #define SDRAM_SDTR2_RP_3_CLK 0x00000030
666 #define SDRAM_SDTR2_RP_4_CLK 0x00000040
667 #define SDRAM_SDTR2_RP_5_CLK 0x00000050
668 #define SDRAM_SDTR2_RP_6_CLK 0x00000060
669 #define SDRAM_SDTR2_RP_7_CLK 0x00000070
670 #define SDRAM_SDTR2_RRD_MASK 0x0000000F
671 #define SDRAM_SDTR2_RRD_2_CLK 0x00000002
672 #define SDRAM_SDTR2_RRD_3_CLK 0x00000003
675 * SDRAM SDTR3 Options
677 #define SDRAM_SDTR3_RAS_MASK 0x1F000000
678 #define SDRAM_SDTR3_RAS_ENCODE(n) ((((u32)(n))&0x1F)<<24)
679 #define SDRAM_SDTR3_RC_MASK 0x001F0000
680 #define SDRAM_SDTR3_RC_ENCODE(n) ((((u32)(n))&0x1F)<<16)
681 #define SDRAM_SDTR3_XCS_MASK 0x00001F00
682 #define SDRAM_SDTR3_XCS 0x00000D00
683 #define SDRAM_SDTR3_RFC_MASK 0x0000003F
684 #define SDRAM_SDTR3_RFC_ENCODE(n) ((((u32)(n))&0x3F)<<0)
687 * Memory Bank 0-1 configuration
689 #define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
690 #define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
691 #define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
692 #define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
693 #define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
694 #define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
695 #define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
696 #define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
697 #define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
698 #define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
699 #define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
700 #define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
701 #define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
702 #define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
704 #define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/
705 #define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */
706 #define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */
707 #define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */
708 #define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */
710 #define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */
712 #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */
714 #if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2)
719 #define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
720 #define DDR0_00_INT_ACK_ALL 0x7F000000
721 #define DDR0_00_INT_ACK_ENCODE(n) ((((u32)(n))&0x7F)<<24)
722 #define DDR0_00_INT_ACK_DECODE(n) ((((u32)(n))>>24)&0x7F)
724 #define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
725 /* Bit0. A single access outside the defined PHYSICAL memory space detected. */
726 #define DDR0_00_INT_STATUS_BIT0 0x00010000
727 /* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
728 #define DDR0_00_INT_STATUS_BIT1 0x00020000
729 /* Bit2. Single correctable ECC event detected */
730 #define DDR0_00_INT_STATUS_BIT2 0x00040000
731 /* Bit3. Multiple correctable ECC events detected. */
732 #define DDR0_00_INT_STATUS_BIT3 0x00080000
733 /* Bit4. Single uncorrectable ECC event detected. */
734 #define DDR0_00_INT_STATUS_BIT4 0x00100000
735 /* Bit5. Multiple uncorrectable ECC events detected. */
736 #define DDR0_00_INT_STATUS_BIT5 0x00200000
737 /* Bit6. DRAM initialization complete. */
738 #define DDR0_00_INT_STATUS_BIT6 0x00400000
739 /* Bit7. Logical OR of all lower bits. */
740 #define DDR0_00_INT_STATUS_BIT7 0x00800000
742 #define DDR0_00_INT_STATUS_ENCODE(n) ((((u32)(n))&0xFF)<<16)
743 #define DDR0_00_INT_STATUS_DECODE(n) ((((u32)(n))>>16)&0xFF)
744 #define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
745 #define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((u32)(n))&0x7F)<<8)
746 #define DDR0_00_DLL_INCREMENT_DECODE(n) ((((u32)(n))>>8)&0x7F)
747 #define DDR0_00_DLL_START_POINT_MASK 0x0000007F
748 #define DDR0_00_DLL_START_POINT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
749 #define DDR0_00_DLL_START_POINT_DECODE(n) ((((u32)(n))>>0)&0x7F)
752 #define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
753 #define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((u32)(n))&0x1F)<<24)
754 #define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((u32)(n))>>24)&0x1F)
755 #define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
756 #define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((u32)(n))&0x1F)<<16)
757 #define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((u32)(n))>>16)&0x1F)
758 #define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
759 #define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((u32)(n))&0x7)<<8)
760 #define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((u32)(n))>>8)&0x7)
761 #define DDR0_01_INT_MASK_MASK 0x000000FF
762 #define DDR0_01_INT_MASK_ENCODE(n) ((((u32)(n))&0xFF)<<0)
763 #define DDR0_01_INT_MASK_DECODE(n) ((((u32)(n))>>0)&0xFF)
764 #define DDR0_01_INT_MASK_ALL_ON 0x000000FF
765 #define DDR0_01_INT_MASK_ALL_OFF 0x00000000
768 #define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
769 #define DDR0_02_MAX_CS_REG_ENCODE(n) ((((u32)(n))&0x2)<<24)
770 #define DDR0_02_MAX_CS_REG_DECODE(n) ((((u32)(n))>>24)&0x2)
771 #define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
772 #define DDR0_02_MAX_COL_REG_ENCODE(n) ((((u32)(n))&0xF)<<16)
773 #define DDR0_02_MAX_COL_REG_DECODE(n) ((((u32)(n))>>16)&0xF)
774 #define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
775 #define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((u32)(n))&0xF)<<8)
776 #define DDR0_02_MAX_ROW_REG_DECODE(n) ((((u32)(n))>>8)&0xF)
777 #define DDR0_02_START_MASK 0x00000001
778 #define DDR0_02_START_ENCODE(n) ((((u32)(n))&0x1)<<0)
779 #define DDR0_02_START_DECODE(n) ((((u32)(n))>>0)&0x1)
780 #define DDR0_02_START_OFF 0x00000000
781 #define DDR0_02_START_ON 0x00000001
784 #define DDR0_03_BSTLEN_MASK 0x07000000
785 #define DDR0_03_BSTLEN_ENCODE(n) ((((u32)(n))&0x7)<<24)
786 #define DDR0_03_BSTLEN_DECODE(n) ((((u32)(n))>>24)&0x7)
787 #define DDR0_03_CASLAT_MASK 0x00070000
788 #define DDR0_03_CASLAT_ENCODE(n) ((((u32)(n))&0x7)<<16)
789 #define DDR0_03_CASLAT_DECODE(n) ((((u32)(n))>>16)&0x7)
790 #define DDR0_03_CASLAT_LIN_MASK 0x00000F00
791 #define DDR0_03_CASLAT_LIN_ENCODE(n) ((((u32)(n))&0xF)<<8)
792 #define DDR0_03_CASLAT_LIN_DECODE(n) ((((u32)(n))>>8)&0xF)
793 #define DDR0_03_INITAREF_MASK 0x0000000F
794 #define DDR0_03_INITAREF_ENCODE(n) ((((u32)(n))&0xF)<<0)
795 #define DDR0_03_INITAREF_DECODE(n) ((((u32)(n))>>0)&0xF)
798 #define DDR0_04_TRC_MASK 0x1F000000
799 #define DDR0_04_TRC_ENCODE(n) ((((u32)(n))&0x1F)<<24)
800 #define DDR0_04_TRC_DECODE(n) ((((u32)(n))>>24)&0x1F)
801 #define DDR0_04_TRRD_MASK 0x00070000
802 #define DDR0_04_TRRD_ENCODE(n) ((((u32)(n))&0x7)<<16)
803 #define DDR0_04_TRRD_DECODE(n) ((((u32)(n))>>16)&0x7)
804 #define DDR0_04_TRTP_MASK 0x00000700
805 #define DDR0_04_TRTP_ENCODE(n) ((((u32)(n))&0x7)<<8)
806 #define DDR0_04_TRTP_DECODE(n) ((((u32)(n))>>8)&0x7)
809 #define DDR0_05_TMRD_MASK 0x1F000000
810 #define DDR0_05_TMRD_ENCODE(n) ((((u32)(n))&0x1F)<<24)
811 #define DDR0_05_TMRD_DECODE(n) ((((u32)(n))>>24)&0x1F)
812 #define DDR0_05_TEMRS_MASK 0x00070000
813 #define DDR0_05_TEMRS_ENCODE(n) ((((u32)(n))&0x7)<<16)
814 #define DDR0_05_TEMRS_DECODE(n) ((((u32)(n))>>16)&0x7)
815 #define DDR0_05_TRP_MASK 0x00000F00
816 #define DDR0_05_TRP_ENCODE(n) ((((u32)(n))&0xF)<<8)
817 #define DDR0_05_TRP_DECODE(n) ((((u32)(n))>>8)&0xF)
818 #define DDR0_05_TRAS_MIN_MASK 0x000000FF
819 #define DDR0_05_TRAS_MIN_ENCODE(n) ((((u32)(n))&0xFF)<<0)
820 #define DDR0_05_TRAS_MIN_DECODE(n) ((((u32)(n))>>0)&0xFF)
823 #define DDR0_06_WRITEINTERP_MASK 0x01000000
824 #define DDR0_06_WRITEINTERP_ENCODE(n) ((((u32)(n))&0x1)<<24)
825 #define DDR0_06_WRITEINTERP_DECODE(n) ((((u32)(n))>>24)&0x1)
826 #define DDR0_06_TWTR_MASK 0x00070000
827 #define DDR0_06_TWTR_ENCODE(n) ((((u32)(n))&0x7)<<16)
828 #define DDR0_06_TWTR_DECODE(n) ((((u32)(n))>>16)&0x7)
829 #define DDR0_06_TDLL_MASK 0x0000FF00
830 #define DDR0_06_TDLL_ENCODE(n) ((((u32)(n))&0xFF)<<8)
831 #define DDR0_06_TDLL_DECODE(n) ((((u32)(n))>>8)&0xFF)
832 #define DDR0_06_TRFC_MASK 0x0000007F
833 #define DDR0_06_TRFC_ENCODE(n) ((((u32)(n))&0x7F)<<0)
834 #define DDR0_06_TRFC_DECODE(n) ((((u32)(n))>>0)&0x7F)
837 #define DDR0_07_NO_CMD_INIT_MASK 0x01000000
838 #define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((u32)(n))&0x1)<<24)
839 #define DDR0_07_NO_CMD_INIT_DECODE(n) ((((u32)(n))>>24)&0x1)
840 #define DDR0_07_TFAW_MASK 0x001F0000
841 #define DDR0_07_TFAW_ENCODE(n) ((((u32)(n))&0x1F)<<16)
842 #define DDR0_07_TFAW_DECODE(n) ((((u32)(n))>>16)&0x1F)
843 #define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
844 #define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((u32)(n))&0x1)<<8)
845 #define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((u32)(n))>>8)&0x1)
846 #define DDR0_07_AREFRESH_MASK 0x00000001
847 #define DDR0_07_AREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<0)
848 #define DDR0_07_AREFRESH_DECODE(n) ((((u32)(n))>>0)&0x1)
851 #define DDR0_08_WRLAT_MASK 0x07000000
852 #define DDR0_08_WRLAT_ENCODE(n) ((((u32)(n))&0x7)<<24)
853 #define DDR0_08_WRLAT_DECODE(n) ((((u32)(n))>>24)&0x7)
854 #define DDR0_08_TCPD_MASK 0x00FF0000
855 #define DDR0_08_TCPD_ENCODE(n) ((((u32)(n))&0xFF)<<16)
856 #define DDR0_08_TCPD_DECODE(n) ((((u32)(n))>>16)&0xFF)
857 #define DDR0_08_DQS_N_EN_MASK 0x00000100
858 #define DDR0_08_DQS_N_EN_ENCODE(n) ((((u32)(n))&0x1)<<8)
859 #define DDR0_08_DQS_N_EN_DECODE(n) ((((u32)(n))>>8)&0x1)
860 #define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
861 #define DDR0_08_DDRII_ENCODE(n) ((((u32)(n))&0x1)<<0)
862 #define DDR0_08_DDRII_DECODE(n) ((((u32)(n))>>0)&0x1)
865 #define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
866 #define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<24)
867 #define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((u32)(n))>>24)&0x1F)
868 #define DDR0_09_RTT_0_MASK 0x00030000
869 #define DDR0_09_RTT_0_ENCODE(n) ((((u32)(n))&0x3)<<16)
870 #define DDR0_09_RTT_0_DECODE(n) ((((u32)(n))>>16)&0x3)
871 #define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
872 #define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<8)
873 #define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>8)&0x7F)
874 #define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
875 #define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<0)
876 #define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((u32)(n))>>0)&0x7F)
879 #define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
880 #define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((u32)(n))&0x1)<<16)
881 #define DDR0_10_WRITE_MODEREG_DECODE(n) ((((u32)(n))>>16)&0x1)
882 #define DDR0_10_CS_MAP_MASK 0x00000300
883 #define DDR0_10_CS_MAP_NO_MEM 0x00000000
884 #define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
885 #define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
886 #define DDR0_10_CS_MAP_ENCODE(n) ((((u32)(n))&0x3)<<8)
887 #define DDR0_10_CS_MAP_DECODE(n) ((((u32)(n))>>8)&0x3)
888 #define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
889 #define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((u32)(n))&0x1F)<<0)
890 #define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((u32)(n))>>0)&0x1F)
893 #define DDR0_11_SREFRESH_MASK 0x01000000
894 #define DDR0_11_SREFRESH_ENCODE(n) ((((u32)(n))&0x1)<<24)
895 #define DDR0_11_SREFRESH_DECODE(n) ((((u32)(n))>>24)&0x1F)
896 #define DDR0_11_TXSNR_MASK 0x00FF0000
897 #define DDR0_11_TXSNR_ENCODE(n) ((((u32)(n))&0xFF)<<16)
898 #define DDR0_11_TXSNR_DECODE(n) ((((u32)(n))>>16)&0xFF)
899 #define DDR0_11_TXSR_MASK 0x0000FF00
900 #define DDR0_11_TXSR_ENCODE(n) ((((u32)(n))&0xFF)<<8)
901 #define DDR0_11_TXSR_DECODE(n) ((((u32)(n))>>8)&0xFF)
904 #define DDR0_12_TCKE_MASK 0x0000007
905 #define DDR0_12_TCKE_ENCODE(n) ((((u32)(n))&0x7)<<0)
906 #define DDR0_12_TCKE_DECODE(n) ((((u32)(n))>>0)&0x7)
909 #define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
910 #define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((u32)(n))&0x1)<<24)
911 #define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((u32)(n))>>24)&0x1)
912 #define DDR0_14_REDUC_MASK 0x00010000
913 #define DDR0_14_REDUC_64BITS 0x00000000
914 #define DDR0_14_REDUC_32BITS 0x00010000
915 #define DDR0_14_REDUC_ENCODE(n) ((((u32)(n))&0x1)<<16)
916 #define DDR0_14_REDUC_DECODE(n) ((((u32)(n))>>16)&0x1)
917 #define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
918 #define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((u32)(n))&0x1)<<8)
919 #define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((u32)(n))>>8)&0x1)
922 #define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
923 #define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((u32)(n))&0x7F)<<24)
924 #define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((u32)(n))>>24)&0x7F)
925 #define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
926 #define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
927 #define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
928 #define DDR0_17_DLLLOCKREG_ENCODE(n) ((((u32)(n))&0x1)<<16)
929 #define DDR0_17_DLLLOCKREG_DECODE(n) ((((u32)(n))>>16)&0x1)
930 #define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
931 #define DDR0_17_DLL_LOCK_ENCODE(n) ((((u32)(n))&0x7F)<<8)
932 #define DDR0_17_DLL_LOCK_DECODE(n) ((((u32)(n))>>8)&0x7F)
935 #define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
936 #define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
937 #define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((u32)(n))&0x7F)<<24)
938 #define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((u32)(n))>>24)&0x7F)
939 #define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
940 #define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((u32)(n))&0x7F)<<16)
941 #define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((u32)(n))>>16)&0x7F)
942 #define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
943 #define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((u32)(n))&0x7F)<<8)
944 #define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((u32)(n))>>8)&0x7F)
945 #define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
946 #define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((u32)(n))&0x7F)<<0)
947 #define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((u32)(n))>>0)&0x7F)
950 #define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
951 #define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
952 #define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((u32)(n))&0x7F)<<24)
953 #define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((u32)(n))>>24)&0x7F)
954 #define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
955 #define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((u32)(n))&0x7F)<<16)
956 #define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((u32)(n))>>16)&0x7F)
957 #define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
958 #define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((u32)(n))&0x7F)<<8)
959 #define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((u32)(n))>>8)&0x7F)
960 #define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
961 #define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((u32)(n))&0x7F)<<0)
962 #define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((u32)(n))>>0)&0x7F)
965 #define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
966 #define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((u32)(n))&0x7F)<<24)
967 #define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((u32)(n))>>24)&0x7F)
968 #define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
969 #define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((u32)(n))&0x7F)<<16)
970 #define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((u32)(n))>>16)&0x7F)
971 #define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
972 #define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((u32)(n))&0x7F)<<8)
973 #define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((u32)(n))>>8)&0x7F)
974 #define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
975 #define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((u32)(n))&0x7F)<<0)
976 #define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((u32)(n))>>0)&0x7F)
979 #define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
980 #define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((u32)(n))&0x7F)<<24)
981 #define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((u32)(n))>>24)&0x7F)
982 #define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
983 #define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((u32)(n))&0x7F)<<16)
984 #define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((u32)(n))>>16)&0x7F)
985 #define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
986 #define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((u32)(n))&0x7F)<<8)
987 #define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((u32)(n))>>8)&0x7F)
988 #define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
989 #define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((u32)(n))&0x7F)<<0)
990 #define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((u32)(n))>>0)&0x7F)
993 #define DDR0_22_CTRL_RAW_MASK 0x03000000
994 #define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000
995 #define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000
996 #define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000
997 #define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000
998 #define DDR0_22_CTRL_RAW_ENCODE(n) ((((u32)(n))&0x3)<<24)
999 #define DDR0_22_CTRL_RAW_DECODE(n) ((((u32)(n))>>24)&0x3)
1000 #define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
1001 #define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((u32)(n))&0x7F)<<16)
1002 #define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((u32)(n))>>16)&0x7F)
1003 #define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
1004 #define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((u32)(n))&0x7F)<<8)
1005 #define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((u32)(n))>>8)&0x7F)
1006 #define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
1007 #define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((u32)(n))&0x7F)<<0)
1008 #define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((u32)(n))>>0)&0x7F)
1010 #define DDR0_23 0x17
1011 #define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
1012 #define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<24)
1013 #define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((u32)(n))>>24)&0x3)
1014 #define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
1015 #define DDR0_23_ECC_C_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<16)
1016 #define DDR0_23_ECC_C_SYND_DECODE(n) ((((u32)(n))>>16)&0xFF)
1017 #define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
1018 #define DDR0_23_ECC_U_SYND_ENCODE(n) ((((u32)(n))&0xFF)<<8)
1019 #define DDR0_23_ECC_U_SYND_DECODE(n) ((((u32)(n))>>8)&0xFF)
1020 #define DDR0_23_FWC_MASK 0x00000001 /* Write only */
1021 #define DDR0_23_FWC_ENCODE(n) ((((u32)(n))&0x1)<<0)
1022 #define DDR0_23_FWC_DECODE(n) ((((u32)(n))>>0)&0x1)
1024 #define DDR0_24 0x18
1025 #define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
1026 #define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((u32)(n))&0x3)<<24)
1027 #define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((u32)(n))>>24)&0x3)
1028 #define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
1029 #define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<16)
1030 #define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((u32)(n))>>16)&0x3)
1031 #define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
1032 #define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((u32)(n))&0x3)<<8)
1033 #define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((u32)(n))>>8)&0x3)
1034 #define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
1035 #define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((u32)(n))&0x3)<<0)
1036 #define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((u32)(n))>>0)&0x3)
1038 #define DDR0_25 0x19
1039 #define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
1040 #define DDR0_25_VERSION_ENCODE(n) ((((u32)(n))&0xFFFF)<<16)
1041 #define DDR0_25_VERSION_DECODE(n) ((((u32)(n))>>16)&0xFFFF)
1042 #define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
1043 #define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((u32)(n))&0x3FF)<<0)
1044 #define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((u32)(n))>>0)&0x3FF)
1046 #define DDR0_26 0x1A
1047 #define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
1048 #define DDR0_26_TRAS_MAX_ENCODE(n) ((((u32)(n))&0xFFFF)<<16)
1049 #define DDR0_26_TRAS_MAX_DECODE(n) ((((u32)(n))>>16)&0xFFFF)
1050 #define DDR0_26_TREF_MASK 0x00003FFF
1051 #define DDR0_26_TREF_ENCODE(n) ((((u32)(n))&0x3FFF)<<0)
1052 #define DDR0_26_TREF_DECODE(n) ((((u32)(n))>>0)&0x3FFF)
1054 #define DDR0_27 0x1B
1055 #define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
1056 #define DDR0_27_EMRS_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16)
1057 #define DDR0_27_EMRS_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF)
1058 #define DDR0_27_TINIT_MASK 0x0000FFFF
1059 #define DDR0_27_TINIT_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
1060 #define DDR0_27_TINIT_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
1062 #define DDR0_28 0x1C
1063 #define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
1064 #define DDR0_28_EMRS3_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<16)
1065 #define DDR0_28_EMRS3_DATA_DECODE(n) ((((u32)(n))>>16)&0x3FFF)
1066 #define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
1067 #define DDR0_28_EMRS2_DATA_ENCODE(n) ((((u32)(n))&0x3FFF)<<0)
1068 #define DDR0_28_EMRS2_DATA_DECODE(n) ((((u32)(n))>>0)&0x3FFF)
1070 #define DDR0_31 0x1F
1071 #define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
1072 #define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((u32)(n))&0xFFFF)<<0)
1073 #define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((u32)(n))>>0)&0xFFFF)
1075 #define DDR0_32 0x20
1076 #define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
1077 #define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1078 #define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1080 #define DDR0_33 0x21
1081 #define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
1082 #define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
1083 #define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
1085 #define DDR0_34 0x22
1086 #define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
1087 #define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1088 #define DDR0_34_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1090 #define DDR0_35 0x23
1091 #define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
1092 #define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
1093 #define DDR0_35_ECC_U_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
1095 #define DDR0_36 0x24
1096 #define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
1097 #define DDR0_36_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1098 #define DDR0_36_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1100 #define DDR0_37 0x25
1101 #define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
1102 #define DDR0_37_ECC_U_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1103 #define DDR0_37_ECC_U_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1105 #define DDR0_38 0x26
1106 #define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
1107 #define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1108 #define DDR0_38_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1110 #define DDR0_39 0x27
1111 #define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
1112 #define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((u32)(n))&0x1)<<0)
1113 #define DDR0_39_ECC_C_ADDR_DECODE(n) ((((u32)(n))>>0)&0x1)
1115 #define DDR0_40 0x28
1116 #define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
1117 #define DDR0_40_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1118 #define DDR0_40_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1120 #define DDR0_41 0x29
1121 #define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
1122 #define DDR0_41_ECC_C_DATA_ENCODE(n) ((((u32)(n))&0xFFFFFFFF)<<0)
1123 #define DDR0_41_ECC_C_DATA_DECODE(n) ((((u32)(n))>>0)&0xFFFFFFFF)
1125 #define DDR0_42 0x2A
1126 #define DDR0_42_ADDR_PINS_MASK 0x07000000
1127 #define DDR0_42_ADDR_PINS_ENCODE(n) ((((u32)(n))&0x7)<<24)
1128 #define DDR0_42_ADDR_PINS_DECODE(n) ((((u32)(n))>>24)&0x7)
1129 #define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
1130 #define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((u32)(n))&0xF)<<0)
1131 #define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((u32)(n))>>0)&0xF)
1133 #define DDR0_43 0x2B
1134 #define DDR0_43_TWR_MASK 0x07000000
1135 #define DDR0_43_TWR_ENCODE(n) ((((u32)(n))&0x7)<<24)
1136 #define DDR0_43_TWR_DECODE(n) ((((u32)(n))>>24)&0x7)
1137 #define DDR0_43_APREBIT_MASK 0x000F0000
1138 #define DDR0_43_APREBIT_ENCODE(n) ((((u32)(n))&0xF)<<16)
1139 #define DDR0_43_APREBIT_DECODE(n) ((((u32)(n))>>16)&0xF)
1140 #define DDR0_43_COLUMN_SIZE_MASK 0x00000700
1141 #define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((u32)(n))&0x7)<<8)
1142 #define DDR0_43_COLUMN_SIZE_DECODE(n) ((((u32)(n))>>8)&0x7)
1143 #define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
1144 #define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
1145 #define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
1146 #define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((u32)(n))&0x1)<<0)
1147 #define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((u32)(n))>>0)&0x1)
1149 #define DDR0_44 0x2C
1150 #define DDR0_44_TRCD_MASK 0x000000FF
1151 #define DDR0_44_TRCD_ENCODE(n) ((((u32)(n))&0xFF)<<0)
1152 #define DDR0_44_TRCD_DECODE(n) ((((u32)(n))>>0)&0xFF)
1154 #endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
1156 #endif /* _PPC4xx_SDRAM_H_ */
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