2 * mcfuart.h -- ColdFire internal UART support defines.
4 * File copied from mcfuart.h of uCLinux distribution:
5 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
6 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 /****************************************************************************/
30 /****************************************************************************/
32 #include <linux/config.h>
35 * Define the base address of the UARTS within the MBAR address
38 #if defined(CONFIG_M5272)
39 #define MCFUART_BASE1 0x100 /* Base address of UART1 */
40 #define MCFUART_BASE2 0x140 /* Base address of UART2 */
41 #elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
42 #if defined(CONFIG_NETtel)
43 #define MCFUART_BASE1 0x180 /* Base address of UART1 */
44 #define MCFUART_BASE2 0x140 /* Base address of UART2 */
46 #define MCFUART_BASE1 0x140 /* Base address of UART1 */
47 #define MCFUART_BASE2 0x180 /* Base address of UART2 */
49 #elif defined(CONFIG_M5282) || defined(CONFIG_M5271)
50 #define MCFUART_BASE1 0x200 /* Base address of UART1 */
51 #define MCFUART_BASE2 0x240 /* Base address of UART2 */
52 #define MCFUART_BASE3 0x280 /* Base address of UART3 */
53 #elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
54 #if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
55 #define MCFUART_BASE1 0x200 /* Base address of UART1 */
56 #define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
58 #define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
59 #define MCFUART_BASE2 0x200 /* Base address of UART2 */
64 * Define the ColdFire UART register set addresses.
66 #define MCFUART_UMR 0x00 /* Mode register (r/w) */
67 #define MCFUART_USR 0x04 /* Status register (r) */
68 #define MCFUART_UCSR 0x04 /* Clock Select (w) */
69 #define MCFUART_UCR 0x08 /* Command register (w) */
70 #define MCFUART_URB 0x0c /* Receiver Buffer (r) */
71 #define MCFUART_UTB 0x0c /* Transmit Buffer (w) */
72 #define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
73 #define MCFUART_UACR 0x10 /* Auxiliary Control (w) */
74 #define MCFUART_UISR 0x14 /* Interrup Status (r) */
75 #define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */
76 #define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */
77 #define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */
79 #define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */
80 #define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */
81 #define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
83 #define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */
85 #define MCFUART_UIPR 0x34 /* Input Port (r) */
86 #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
87 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
90 /* Note: This isn't in the 5249 docs */
91 #define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
95 * Define bit flags in Mode Register 1 (MR1).
97 #define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */
98 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
99 #define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
100 #define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
101 #define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
103 #define MCFUART_MR1_PARITYNONE 0x10 /* No parity */
104 #define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */
105 #define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */
106 #define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */
107 #define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */
109 #define MCFUART_MR1_CS5 0x00 /* 5 bits per char */
110 #define MCFUART_MR1_CS6 0x01 /* 6 bits per char */
111 #define MCFUART_MR1_CS7 0x02 /* 7 bits per char */
112 #define MCFUART_MR1_CS8 0x03 /* 8 bits per char */
115 * Define bit flags in Mode Register 2 (MR2).
117 #define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */
118 #define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */
119 #define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */
120 #define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */
121 #define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */
123 #define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
124 #define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */
125 #define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */
128 * Define bit flags in Status Register (USR).
130 #define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */
131 #define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */
132 #define MCFUART_USR_RXPARITY 0x20 /* Received parity error */
133 #define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */
134 #define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */
135 #define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */
136 #define MCFUART_USR_RXFULL 0x02 /* Receiver full */
137 #define MCFUART_USR_RXREADY 0x01 /* Receiver ready */
139 #define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
140 MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
143 * Define bit flags in Clock Select Register (UCSR).
145 #define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
146 #define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */
147 #define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */
149 #define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */
150 #define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */
151 #define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */
154 * Define bit flags in Command Register (UCR).
156 #define MCFUART_UCR_CMDNULL 0x00 /* No command */
157 #define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */
158 #define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */
159 #define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */
160 #define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */
161 #define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */
162 #define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */
163 #define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */
165 #define MCFUART_UCR_TXNULL 0x00 /* No TX command */
166 #define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */
167 #define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */
168 #define MCFUART_UCR_RXNULL 0x00 /* No RX command */
169 #define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */
170 #define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */
173 * Define bit flags in Input Port Change Register (UIPCR).
175 #define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */
176 #define MCFUART_UIPCR_CTS 0x01 /* CTS value */
179 * Define bit flags in Input Port Register (UIP).
181 #define MCFUART_UIPR_CTS 0x01 /* CTS value */
184 * Define bit flags in Output Port Registers (UOP).
185 * Clear bit by writing to UOP0, set by writing to UOP1.
187 #define MCFUART_UOP_RTS 0x01 /* RTS set or clear */
190 * Define bit flags in the Auxiliary Control Register (UACR).
192 #define MCFUART_UACR_IEC 0x01 /* Input enable control */
195 * Define bit flags in Interrupt Status Register (UISR).
196 * These same bits are used for the Interrupt Mask Register (UIMR).
198 #define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */
199 #define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */
200 #define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */
201 #define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */
205 * Define bit flags in the Transmitter FIFO Register (UTF).
207 #define MCFUART_UTF_TXB 0x1f /* transmitter data level */
208 #define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */
209 #define MCFUART_UTF_TXS 0xc0 /* transmitter status */
212 * Define bit flags in the Receiver FIFO Register (URF).
214 #define MCFUART_URF_RXB 0x1f /* receiver data level */
215 #define MCFUART_URF_FULL 0x20 /* receiver fifo full */
216 #define MCFUART_URF_RXS 0xc0 /* receiver status */
219 #ifdef CONFIG_MCFUART
220 /* UART module registers */
221 /* Register read/write struct */
222 typedef struct uart {
223 u8 umr; /* 0x00 Mode Register */
226 u8 usr; /* 0x04 Status Register */
227 u8 ucsr; /* 0x04 Clock Select Register */
230 u8 ucr; /* 0x08 Command Register */
233 u8 utb; /* 0x0c Transmit Buffer */
234 u8 urb; /* 0x0c Receive Buffer */
238 u8 uipcr; /* 0x10 Input Port Change Register */
239 u8 uacr; /* 0x10 Auxiliary Control reg */
243 u8 uimr; /* 0x14 Interrupt Mask reg */
244 u8 uisr; /* 0x14 Interrupt Status reg */
247 u8 ubg1; /* 0x18 Counter Timer Upper Register */
249 u8 ubg2; /* 0x1c Counter Timer Lower Register */
251 u8 uip; /* 0x34 Input Port Register */
253 u8 uop1; /* 0x38 Output Port Set Register */
255 u8 uop0; /* 0x3c Output Port Reset Register */
258 /*********************************************************************
259 * Universal Asynchronous Receiver Transmitter (UART)
260 *********************************************************************/
261 /* Bit definitions and macros for UMR */
262 #define UART_UMR_BC(x) (((x)&0x03))
263 #define UART_UMR_PT (0x04)
264 #define UART_UMR_PM(x) (((x)&0x03)<<3)
265 #define UART_UMR_ERR (0x20)
266 #define UART_UMR_RXIRQ (0x40)
267 #define UART_UMR_RXRTS (0x80)
268 #define UART_UMR_SB(x) (((x)&0x0F))
269 #define UART_UMR_TXCTS (0x10) /* Trsnsmit CTS */
270 #define UART_UMR_TXRTS (0x20) /* Transmit RTS */
271 #define UART_UMR_CM(x) (((x)&0x03)<<6) /* CM bits */
272 #define UART_UMR_PM_MULTI_ADDR (0x1C)
273 #define UART_UMR_PM_MULTI_DATA (0x18)
274 #define UART_UMR_PM_NONE (0x10)
275 #define UART_UMR_PM_FORCE_HI (0x0C)
276 #define UART_UMR_PM_FORCE_LO (0x08)
277 #define UART_UMR_PM_ODD (0x04)
278 #define UART_UMR_PM_EVEN (0x00)
279 #define UART_UMR_BC_5 (0x00)
280 #define UART_UMR_BC_6 (0x01)
281 #define UART_UMR_BC_7 (0x02)
282 #define UART_UMR_BC_8 (0x03)
283 #define UART_UMR_CM_NORMAL (0x00)
284 #define UART_UMR_CM_ECH (0x40)
285 #define UART_UMR_CM_LOCAL_LOOP (0x80)
286 #define UART_UMR_CM_REMOTE_LOOP (0xC0)
287 #define UART_UMR_SB_STOP_BITS_1 (0x07)
288 #define UART_UMR_SB_STOP_BITS_15 (0x08)
289 #define UART_UMR_SB_STOP_BITS_2 (0x0F)
291 /* Bit definitions and macros for USR */
292 #define UART_USR_RXRDY (0x01)
293 #define UART_USR_FFULL (0x02)
294 #define UART_USR_TXRDY (0x04)
295 #define UART_USR_TXEMP (0x08)
296 #define UART_USR_OE (0x10)
297 #define UART_USR_PE (0x20)
298 #define UART_USR_FE (0x40)
299 #define UART_USR_RB (0x80)
301 /* Bit definitions and macros for UCSR */
302 #define UART_UCSR_TCS(x) (((x)&0x0F))
303 #define UART_UCSR_RCS(x) (((x)&0x0F)<<4)
304 #define UART_UCSR_RCS_SYS_CLK (0xD0)
305 #define UART_UCSR_RCS_CTM16 (0xE0)
306 #define UART_UCSR_RCS_CTM (0xF0)
307 #define UART_UCSR_TCS_SYS_CLK (0x0D)
308 #define UART_UCSR_TCS_CTM16 (0x0E)
309 #define UART_UCSR_TCS_CTM (0x0F)
311 /* Bit definitions and macros for UCR */
312 #define UART_UCR_RXC(x) (((x)&0x03))
313 #define UART_UCR_TXC(x) (((x)&0x03)<<2)
314 #define UART_UCR_MISC(x) (((x)&0x07)<<4)
315 #define UART_UCR_NONE (0x00)
316 #define UART_UCR_STOP_BREAK (0x70)
317 #define UART_UCR_START_BREAK (0x60)
318 #define UART_UCR_BKCHGINT (0x50)
319 #define UART_UCR_RESET_ERROR (0x40)
320 #define UART_UCR_RESET_TX (0x30)
321 #define UART_UCR_RESET_RX (0x20)
322 #define UART_UCR_RESET_MR (0x10)
323 #define UART_UCR_TX_DISABLED (0x08)
324 #define UART_UCR_TX_ENABLED (0x04)
325 #define UART_UCR_RX_DISABLED (0x02)
326 #define UART_UCR_RX_ENABLED (0x01)
328 /* Bit definitions and macros for UIPCR */
329 #define UART_UIPCR_CTS (0x01)
330 #define UART_UIPCR_COS (0x10)
332 /* Bit definitions and macros for UACR */
333 #define UART_UACR_IEC (0x01)
335 /* Bit definitions and macros for UIMR */
336 #define UART_UIMR_TXRDY (0x01)
337 #define UART_UIMR_RXRDY_FU (0x02)
338 #define UART_UIMR_DB (0x04)
339 #define UART_UIMR_COS (0x80)
341 /* Bit definitions and macros for UISR */
342 #define UART_UISR_TXRDY (0x01)
343 #define UART_UISR_RXRDY_FU (0x02)
344 #define UART_UISR_DB (0x04)
345 #define UART_UISR_RXFTO (0x08)
346 #define UART_UISR_TXFIFO (0x10)
347 #define UART_UISR_RXFIFO (0x20)
348 #define UART_UISR_COS (0x80)
350 /* Bit definitions and macros for UIP */
351 #define UART_UIP_CTS (0x01)
353 /* Bit definitions and macros for UOP1 */
354 #define UART_UOP1_RTS (0x01)
356 /* Bit definitions and macros for UOP0 */
357 #define UART_UOP0_RTS (0x01)
358 #endif /* CONFIG_MCFUART */
360 /****************************************************************************/
361 #endif /* mcfuart_h */