2 * MCF5445x Internal Memory Map
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /*********************************************************************
30 * Interrupt Controller (INTC)
31 *********************************************************************/
32 #define INT0_LO_RSVD0 (0)
33 #define INT0_LO_EPORT1 (1)
34 #define INT0_LO_EPORT2 (2)
35 #define INT0_LO_EPORT3 (3)
36 #define INT0_LO_EPORT4 (4)
37 #define INT0_LO_EPORT5 (5)
38 #define INT0_LO_EPORT6 (6)
39 #define INT0_LO_EPORT7 (7)
40 #define INT0_LO_EDMA_00 (8)
41 #define INT0_LO_EDMA_01 (9)
42 #define INT0_LO_EDMA_02 (10)
43 #define INT0_LO_EDMA_03 (11)
44 #define INT0_LO_EDMA_04 (12)
45 #define INT0_LO_EDMA_05 (13)
46 #define INT0_LO_EDMA_06 (14)
47 #define INT0_LO_EDMA_07 (15)
48 #define INT0_LO_EDMA_08 (16)
49 #define INT0_LO_EDMA_09 (17)
50 #define INT0_LO_EDMA_10 (18)
51 #define INT0_LO_EDMA_11 (19)
52 #define INT0_LO_EDMA_12 (20)
53 #define INT0_LO_EDMA_13 (21)
54 #define INT0_LO_EDMA_14 (22)
55 #define INT0_LO_EDMA_15 (23)
56 #define INT0_LO_EDMA_ERR (24)
57 #define INT0_LO_SCM (25)
58 #define INT0_LO_UART0 (26)
59 #define INT0_LO_UART1 (27)
60 #define INT0_LO_UART2 (28)
61 #define INT0_LO_RSVD1 (29)
62 #define INT0_LO_I2C (30)
63 #define INT0_LO_QSPI (31)
64 #define INT0_HI_DTMR0 (32)
65 #define INT0_HI_DTMR1 (33)
66 #define INT0_HI_DTMR2 (34)
67 #define INT0_HI_DTMR3 (35)
68 #define INT0_HI_FEC0_TXF (36)
69 #define INT0_HI_FEC0_TXB (37)
70 #define INT0_HI_FEC0_UN (38)
71 #define INT0_HI_FEC0_RL (39)
72 #define INT0_HI_FEC0_RXF (40)
73 #define INT0_HI_FEC0_RXB (41)
74 #define INT0_HI_FEC0_MII (42)
75 #define INT0_HI_FEC0_LC (43)
76 #define INT0_HI_FEC0_HBERR (44)
77 #define INT0_HI_FEC0_GRA (45)
78 #define INT0_HI_FEC0_EBERR (46)
79 #define INT0_HI_FEC0_BABT (47)
80 #define INT0_HI_FEC0_BABR (48)
81 #define INT0_HI_FEC1_TXF (49)
82 #define INT0_HI_FEC1_TXB (50)
83 #define INT0_HI_FEC1_UN (51)
84 #define INT0_HI_FEC1_RL (52)
85 #define INT0_HI_FEC1_RXF (53)
86 #define INT0_HI_FEC1_RXB (54)
87 #define INT0_HI_FEC1_MII (55)
88 #define INT0_HI_FEC1_LC (56)
89 #define INT0_HI_FEC1_HBERR (57)
90 #define INT0_HI_FEC1_GRA (58)
91 #define INT0_HI_FEC1_EBERR (59)
92 #define INT0_HI_FEC1_BABT (60)
93 #define INT0_HI_FEC1_BABR (61)
94 #define INT0_HI_SCMIR (62)
95 #define INT0_HI_RTC_ISR (63)
97 #define INT1_HI_DSPI_EOQF (33)
98 #define INT1_HI_DSPI_TFFF (34)
99 #define INT1_HI_DSPI_TCF (35)
100 #define INT1_HI_DSPI_TFUF (36)
101 #define INT1_HI_DSPI_RFDF (37)
102 #define INT1_HI_DSPI_RFOF (38)
103 #define INT1_HI_DSPI_RFOF_TFUF (39)
104 #define INT1_HI_RNG_EI (40)
105 #define INT1_HI_PIT0_PIF (43)
106 #define INT1_HI_PIT1_PIF (44)
107 #define INT1_HI_PIT2_PIF (45)
108 #define INT1_HI_PIT3_PIF (46)
109 #define INT1_HI_USBOTG_USBSTS (47)
110 #define INT1_HI_SSI_ISR (49)
111 #define INT1_HI_CCM_UOCSR (53)
112 #define INT1_HI_ATA_ISR (54)
113 #define INT1_HI_PCI_SCR (55)
114 #define INT1_HI_PCI_ASR (56)
115 #define INT1_HI_PLL_LOCKS (57)
117 /* Bit definitions and macros for IPRH */
118 #define INTC_IPRH_INT32 (0x00000001)
119 #define INTC_IPRH_INT33 (0x00000002)
120 #define INTC_IPRH_INT34 (0x00000004)
121 #define INTC_IPRH_INT35 (0x00000008)
122 #define INTC_IPRH_INT36 (0x00000010)
123 #define INTC_IPRH_INT37 (0x00000020)
124 #define INTC_IPRH_INT38 (0x00000040)
125 #define INTC_IPRH_INT39 (0x00000080)
126 #define INTC_IPRH_INT40 (0x00000100)
127 #define INTC_IPRH_INT41 (0x00000200)
128 #define INTC_IPRH_INT42 (0x00000400)
129 #define INTC_IPRH_INT43 (0x00000800)
130 #define INTC_IPRH_INT44 (0x00001000)
131 #define INTC_IPRH_INT45 (0x00002000)
132 #define INTC_IPRH_INT46 (0x00004000)
133 #define INTC_IPRH_INT47 (0x00008000)
134 #define INTC_IPRH_INT48 (0x00010000)
135 #define INTC_IPRH_INT49 (0x00020000)
136 #define INTC_IPRH_INT50 (0x00040000)
137 #define INTC_IPRH_INT51 (0x00080000)
138 #define INTC_IPRH_INT52 (0x00100000)
139 #define INTC_IPRH_INT53 (0x00200000)
140 #define INTC_IPRH_INT54 (0x00400000)
141 #define INTC_IPRH_INT55 (0x00800000)
142 #define INTC_IPRH_INT56 (0x01000000)
143 #define INTC_IPRH_INT57 (0x02000000)
144 #define INTC_IPRH_INT58 (0x04000000)
145 #define INTC_IPRH_INT59 (0x08000000)
146 #define INTC_IPRH_INT60 (0x10000000)
147 #define INTC_IPRH_INT61 (0x20000000)
148 #define INTC_IPRH_INT62 (0x40000000)
149 #define INTC_IPRH_INT63 (0x80000000)
151 /* Bit definitions and macros for IPRL */
152 #define INTC_IPRL_INT0 (0x00000001)
153 #define INTC_IPRL_INT1 (0x00000002)
154 #define INTC_IPRL_INT2 (0x00000004)
155 #define INTC_IPRL_INT3 (0x00000008)
156 #define INTC_IPRL_INT4 (0x00000010)
157 #define INTC_IPRL_INT5 (0x00000020)
158 #define INTC_IPRL_INT6 (0x00000040)
159 #define INTC_IPRL_INT7 (0x00000080)
160 #define INTC_IPRL_INT8 (0x00000100)
161 #define INTC_IPRL_INT9 (0x00000200)
162 #define INTC_IPRL_INT10 (0x00000400)
163 #define INTC_IPRL_INT11 (0x00000800)
164 #define INTC_IPRL_INT12 (0x00001000)
165 #define INTC_IPRL_INT13 (0x00002000)
166 #define INTC_IPRL_INT14 (0x00004000)
167 #define INTC_IPRL_INT15 (0x00008000)
168 #define INTC_IPRL_INT16 (0x00010000)
169 #define INTC_IPRL_INT17 (0x00020000)
170 #define INTC_IPRL_INT18 (0x00040000)
171 #define INTC_IPRL_INT19 (0x00080000)
172 #define INTC_IPRL_INT20 (0x00100000)
173 #define INTC_IPRL_INT21 (0x00200000)
174 #define INTC_IPRL_INT22 (0x00400000)
175 #define INTC_IPRL_INT23 (0x00800000)
176 #define INTC_IPRL_INT24 (0x01000000)
177 #define INTC_IPRL_INT25 (0x02000000)
178 #define INTC_IPRL_INT26 (0x04000000)
179 #define INTC_IPRL_INT27 (0x08000000)
180 #define INTC_IPRL_INT28 (0x10000000)
181 #define INTC_IPRL_INT29 (0x20000000)
182 #define INTC_IPRL_INT30 (0x40000000)
183 #define INTC_IPRL_INT31 (0x80000000)
185 /* Bit definitions and macros for IMRH */
186 #define INTC_IMRH_INT_MASK32 (0x00000001)
187 #define INTC_IMRH_INT_MASK33 (0x00000002)
188 #define INTC_IMRH_INT_MASK34 (0x00000004)
189 #define INTC_IMRH_INT_MASK35 (0x00000008)
190 #define INTC_IMRH_INT_MASK36 (0x00000010)
191 #define INTC_IMRH_INT_MASK37 (0x00000020)
192 #define INTC_IMRH_INT_MASK38 (0x00000040)
193 #define INTC_IMRH_INT_MASK39 (0x00000080)
194 #define INTC_IMRH_INT_MASK40 (0x00000100)
195 #define INTC_IMRH_INT_MASK41 (0x00000200)
196 #define INTC_IMRH_INT_MASK42 (0x00000400)
197 #define INTC_IMRH_INT_MASK43 (0x00000800)
198 #define INTC_IMRH_INT_MASK44 (0x00001000)
199 #define INTC_IMRH_INT_MASK45 (0x00002000)
200 #define INTC_IMRH_INT_MASK46 (0x00004000)
201 #define INTC_IMRH_INT_MASK47 (0x00008000)
202 #define INTC_IMRH_INT_MASK48 (0x00010000)
203 #define INTC_IMRH_INT_MASK49 (0x00020000)
204 #define INTC_IMRH_INT_MASK50 (0x00040000)
205 #define INTC_IMRH_INT_MASK51 (0x00080000)
206 #define INTC_IMRH_INT_MASK52 (0x00100000)
207 #define INTC_IMRH_INT_MASK53 (0x00200000)
208 #define INTC_IMRH_INT_MASK54 (0x00400000)
209 #define INTC_IMRH_INT_MASK55 (0x00800000)
210 #define INTC_IMRH_INT_MASK56 (0x01000000)
211 #define INTC_IMRH_INT_MASK57 (0x02000000)
212 #define INTC_IMRH_INT_MASK58 (0x04000000)
213 #define INTC_IMRH_INT_MASK59 (0x08000000)
214 #define INTC_IMRH_INT_MASK60 (0x10000000)
215 #define INTC_IMRH_INT_MASK61 (0x20000000)
216 #define INTC_IMRH_INT_MASK62 (0x40000000)
217 #define INTC_IMRH_INT_MASK63 (0x80000000)
219 /* Bit definitions and macros for IMRL */
220 #define INTC_IMRL_INT_MASK0 (0x00000001)
221 #define INTC_IMRL_INT_MASK1 (0x00000002)
222 #define INTC_IMRL_INT_MASK2 (0x00000004)
223 #define INTC_IMRL_INT_MASK3 (0x00000008)
224 #define INTC_IMRL_INT_MASK4 (0x00000010)
225 #define INTC_IMRL_INT_MASK5 (0x00000020)
226 #define INTC_IMRL_INT_MASK6 (0x00000040)
227 #define INTC_IMRL_INT_MASK7 (0x00000080)
228 #define INTC_IMRL_INT_MASK8 (0x00000100)
229 #define INTC_IMRL_INT_MASK9 (0x00000200)
230 #define INTC_IMRL_INT_MASK10 (0x00000400)
231 #define INTC_IMRL_INT_MASK11 (0x00000800)
232 #define INTC_IMRL_INT_MASK12 (0x00001000)
233 #define INTC_IMRL_INT_MASK13 (0x00002000)
234 #define INTC_IMRL_INT_MASK14 (0x00004000)
235 #define INTC_IMRL_INT_MASK15 (0x00008000)
236 #define INTC_IMRL_INT_MASK16 (0x00010000)
237 #define INTC_IMRL_INT_MASK17 (0x00020000)
238 #define INTC_IMRL_INT_MASK18 (0x00040000)
239 #define INTC_IMRL_INT_MASK19 (0x00080000)
240 #define INTC_IMRL_INT_MASK20 (0x00100000)
241 #define INTC_IMRL_INT_MASK21 (0x00200000)
242 #define INTC_IMRL_INT_MASK22 (0x00400000)
243 #define INTC_IMRL_INT_MASK23 (0x00800000)
244 #define INTC_IMRL_INT_MASK24 (0x01000000)
245 #define INTC_IMRL_INT_MASK25 (0x02000000)
246 #define INTC_IMRL_INT_MASK26 (0x04000000)
247 #define INTC_IMRL_INT_MASK27 (0x08000000)
248 #define INTC_IMRL_INT_MASK28 (0x10000000)
249 #define INTC_IMRL_INT_MASK29 (0x20000000)
250 #define INTC_IMRL_INT_MASK30 (0x40000000)
251 #define INTC_IMRL_INT_MASK31 (0x80000000)
253 /* Bit definitions and macros for INTFRCH */
254 #define INTC_INTFRCH_INTFRC32 (0x00000001)
255 #define INTC_INTFRCH_INTFRC33 (0x00000002)
256 #define INTC_INTFRCH_INTFRC34 (0x00000004)
257 #define INTC_INTFRCH_INTFRC35 (0x00000008)
258 #define INTC_INTFRCH_INTFRC36 (0x00000010)
259 #define INTC_INTFRCH_INTFRC37 (0x00000020)
260 #define INTC_INTFRCH_INTFRC38 (0x00000040)
261 #define INTC_INTFRCH_INTFRC39 (0x00000080)
262 #define INTC_INTFRCH_INTFRC40 (0x00000100)
263 #define INTC_INTFRCH_INTFRC41 (0x00000200)
264 #define INTC_INTFRCH_INTFRC42 (0x00000400)
265 #define INTC_INTFRCH_INTFRC43 (0x00000800)
266 #define INTC_INTFRCH_INTFRC44 (0x00001000)
267 #define INTC_INTFRCH_INTFRC45 (0x00002000)
268 #define INTC_INTFRCH_INTFRC46 (0x00004000)
269 #define INTC_INTFRCH_INTFRC47 (0x00008000)
270 #define INTC_INTFRCH_INTFRC48 (0x00010000)
271 #define INTC_INTFRCH_INTFRC49 (0x00020000)
272 #define INTC_INTFRCH_INTFRC50 (0x00040000)
273 #define INTC_INTFRCH_INTFRC51 (0x00080000)
274 #define INTC_INTFRCH_INTFRC52 (0x00100000)
275 #define INTC_INTFRCH_INTFRC53 (0x00200000)
276 #define INTC_INTFRCH_INTFRC54 (0x00400000)
277 #define INTC_INTFRCH_INTFRC55 (0x00800000)
278 #define INTC_INTFRCH_INTFRC56 (0x01000000)
279 #define INTC_INTFRCH_INTFRC57 (0x02000000)
280 #define INTC_INTFRCH_INTFRC58 (0x04000000)
281 #define INTC_INTFRCH_INTFRC59 (0x08000000)
282 #define INTC_INTFRCH_INTFRC60 (0x10000000)
283 #define INTC_INTFRCH_INTFRC61 (0x20000000)
284 #define INTC_INTFRCH_INTFRC62 (0x40000000)
285 #define INTC_INTFRCH_INTFRC63 (0x80000000)
287 /* Bit definitions and macros for INTFRCL */
288 #define INTC_INTFRCL_INTFRC0 (0x00000001)
289 #define INTC_INTFRCL_INTFRC1 (0x00000002)
290 #define INTC_INTFRCL_INTFRC2 (0x00000004)
291 #define INTC_INTFRCL_INTFRC3 (0x00000008)
292 #define INTC_INTFRCL_INTFRC4 (0x00000010)
293 #define INTC_INTFRCL_INTFRC5 (0x00000020)
294 #define INTC_INTFRCL_INTFRC6 (0x00000040)
295 #define INTC_INTFRCL_INTFRC7 (0x00000080)
296 #define INTC_INTFRCL_INTFRC8 (0x00000100)
297 #define INTC_INTFRCL_INTFRC9 (0x00000200)
298 #define INTC_INTFRCL_INTFRC10 (0x00000400)
299 #define INTC_INTFRCL_INTFRC11 (0x00000800)
300 #define INTC_INTFRCL_INTFRC12 (0x00001000)
301 #define INTC_INTFRCL_INTFRC13 (0x00002000)
302 #define INTC_INTFRCL_INTFRC14 (0x00004000)
303 #define INTC_INTFRCL_INTFRC15 (0x00008000)
304 #define INTC_INTFRCL_INTFRC16 (0x00010000)
305 #define INTC_INTFRCL_INTFRC17 (0x00020000)
306 #define INTC_INTFRCL_INTFRC18 (0x00040000)
307 #define INTC_INTFRCL_INTFRC19 (0x00080000)
308 #define INTC_INTFRCL_INTFRC20 (0x00100000)
309 #define INTC_INTFRCL_INTFRC21 (0x00200000)
310 #define INTC_INTFRCL_INTFRC22 (0x00400000)
311 #define INTC_INTFRCL_INTFRC23 (0x00800000)
312 #define INTC_INTFRCL_INTFRC24 (0x01000000)
313 #define INTC_INTFRCL_INTFRC25 (0x02000000)
314 #define INTC_INTFRCL_INTFRC26 (0x04000000)
315 #define INTC_INTFRCL_INTFRC27 (0x08000000)
316 #define INTC_INTFRCL_INTFRC28 (0x10000000)
317 #define INTC_INTFRCL_INTFRC29 (0x20000000)
318 #define INTC_INTFRCL_INTFRC30 (0x40000000)
319 #define INTC_INTFRCL_INTFRC31 (0x80000000)
321 /* Bit definitions and macros for ICONFIG */
322 #define INTC_ICONFIG_EMASK (0x0020)
323 #define INTC_ICONFIG_ELVLPRI1 (0x0200)
324 #define INTC_ICONFIG_ELVLPRI2 (0x0400)
325 #define INTC_ICONFIG_ELVLPRI3 (0x0800)
326 #define INTC_ICONFIG_ELVLPRI4 (0x1000)
327 #define INTC_ICONFIG_ELVLPRI5 (0x2000)
328 #define INTC_ICONFIG_ELVLPRI6 (0x4000)
329 #define INTC_ICONFIG_ELVLPRI7 (0x8000)
331 /* Bit definitions and macros for SIMR */
332 #define INTC_SIMR_SIMR(x) (((x)&0x7F))
334 /* Bit definitions and macros for CIMR */
335 #define INTC_CIMR_CIMR(x) (((x)&0x7F))
337 /* Bit definitions and macros for CLMASK */
338 #define INTC_CLMASK_CLMASK(x) (((x)&0x0F))
340 /* Bit definitions and macros for SLMASK */
341 #define INTC_SLMASK_SLMASK(x) (((x)&0x0F))
343 /* Bit definitions and macros for ICR group */
344 #define INTC_ICR_IL(x) (((x)&0x07))
346 /*********************************************************************
347 * Edge Port Module (EPORT)
348 *********************************************************************/
350 /* Bit definitions and macros for EPPAR */
351 #define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
352 #define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
353 #define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
354 #define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
355 #define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
356 #define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
357 #define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
358 #define EPORT_EPPAR_LEVEL (0)
359 #define EPORT_EPPAR_RISING (1)
360 #define EPORT_EPPAR_FALLING (2)
361 #define EPORT_EPPAR_BOTH (3)
362 #define EPORT_EPPAR_EPPA7_LEVEL (0x0000)
363 #define EPORT_EPPAR_EPPA7_RISING (0x4000)
364 #define EPORT_EPPAR_EPPA7_FALLING (0x8000)
365 #define EPORT_EPPAR_EPPA7_BOTH (0xC000)
366 #define EPORT_EPPAR_EPPA6_LEVEL (0x0000)
367 #define EPORT_EPPAR_EPPA6_RISING (0x1000)
368 #define EPORT_EPPAR_EPPA6_FALLING (0x2000)
369 #define EPORT_EPPAR_EPPA6_BOTH (0x3000)
370 #define EPORT_EPPAR_EPPA5_LEVEL (0x0000)
371 #define EPORT_EPPAR_EPPA5_RISING (0x0400)
372 #define EPORT_EPPAR_EPPA5_FALLING (0x0800)
373 #define EPORT_EPPAR_EPPA5_BOTH (0x0C00)
374 #define EPORT_EPPAR_EPPA4_LEVEL (0x0000)
375 #define EPORT_EPPAR_EPPA4_RISING (0x0100)
376 #define EPORT_EPPAR_EPPA4_FALLING (0x0200)
377 #define EPORT_EPPAR_EPPA4_BOTH (0x0300)
378 #define EPORT_EPPAR_EPPA3_LEVEL (0x0000)
379 #define EPORT_EPPAR_EPPA3_RISING (0x0040)
380 #define EPORT_EPPAR_EPPA3_FALLING (0x0080)
381 #define EPORT_EPPAR_EPPA3_BOTH (0x00C0)
382 #define EPORT_EPPAR_EPPA2_LEVEL (0x0000)
383 #define EPORT_EPPAR_EPPA2_RISING (0x0010)
384 #define EPORT_EPPAR_EPPA2_FALLING (0x0020)
385 #define EPORT_EPPAR_EPPA2_BOTH (0x0030)
386 #define EPORT_EPPAR_EPPA1_LEVEL (0x0000)
387 #define EPORT_EPPAR_EPPA1_RISING (0x0004)
388 #define EPORT_EPPAR_EPPA1_FALLING (0x0008)
389 #define EPORT_EPPAR_EPPA1_BOTH (0x000C)
391 /* Bit definitions and macros for EPDDR */
392 #define EPORT_EPDDR_EPDD1 (0x02)
393 #define EPORT_EPDDR_EPDD2 (0x04)
394 #define EPORT_EPDDR_EPDD3 (0x08)
395 #define EPORT_EPDDR_EPDD4 (0x10)
396 #define EPORT_EPDDR_EPDD5 (0x20)
397 #define EPORT_EPDDR_EPDD6 (0x40)
398 #define EPORT_EPDDR_EPDD7 (0x80)
400 /* Bit definitions and macros for EPIER */
401 #define EPORT_EPIER_EPIE1 (0x02)
402 #define EPORT_EPIER_EPIE2 (0x04)
403 #define EPORT_EPIER_EPIE3 (0x08)
404 #define EPORT_EPIER_EPIE4 (0x10)
405 #define EPORT_EPIER_EPIE5 (0x20)
406 #define EPORT_EPIER_EPIE6 (0x40)
407 #define EPORT_EPIER_EPIE7 (0x80)
409 /* Bit definitions and macros for EPDR */
410 #define EPORT_EPDR_EPD1 (0x02)
411 #define EPORT_EPDR_EPD2 (0x04)
412 #define EPORT_EPDR_EPD3 (0x08)
413 #define EPORT_EPDR_EPD4 (0x10)
414 #define EPORT_EPDR_EPD5 (0x20)
415 #define EPORT_EPDR_EPD6 (0x40)
416 #define EPORT_EPDR_EPD7 (0x80)
418 /* Bit definitions and macros for EPPDR */
419 #define EPORT_EPPDR_EPPD1 (0x02)
420 #define EPORT_EPPDR_EPPD2 (0x04)
421 #define EPORT_EPPDR_EPPD3 (0x08)
422 #define EPORT_EPPDR_EPPD4 (0x10)
423 #define EPORT_EPPDR_EPPD5 (0x20)
424 #define EPORT_EPPDR_EPPD6 (0x40)
425 #define EPORT_EPPDR_EPPD7 (0x80)
427 /* Bit definitions and macros for EPFR */
428 #define EPORT_EPFR_EPF1 (0x02)
429 #define EPORT_EPFR_EPF2 (0x04)
430 #define EPORT_EPFR_EPF3 (0x08)
431 #define EPORT_EPFR_EPF4 (0x10)
432 #define EPORT_EPFR_EPF5 (0x20)
433 #define EPORT_EPFR_EPF6 (0x40)
434 #define EPORT_EPFR_EPF7 (0x80)
436 /*********************************************************************
437 * Watchdog Timer Modules (WTM)
438 *********************************************************************/
440 /* Bit definitions and macros for WCR */
441 #define WTM_WCR_EN (0x0001)
442 #define WTM_WCR_HALTED (0x0002)
443 #define WTM_WCR_DOZE (0x0004)
444 #define WTM_WCR_WAIT (0x0008)
446 /*********************************************************************
447 * Serial Boot Facility (SBF)
448 *********************************************************************/
450 /* Bit definitions and macros for SBFCR */
451 #define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */
452 #define SBF_SBFCR_FR (0x0010) /* Fast read */
454 /*********************************************************************
455 * Reset Controller Module (RCM)
456 *********************************************************************/
458 /* Bit definitions and macros for RCR */
459 #define RCM_RCR_FRCRSTOUT (0x40)
460 #define RCM_RCR_SOFTRST (0x80)
462 /* Bit definitions and macros for RSR */
463 #define RCM_RSR_LOL (0x01)
464 #define RCM_RSR_WDR_CORE (0x02)
465 #define RCM_RSR_EXT (0x04)
466 #define RCM_RSR_POR (0x08)
467 #define RCM_RSR_SOFT (0x20)
469 /*********************************************************************
470 * Chip Configuration Module (CCM)
471 *********************************************************************/
473 /* Bit definitions and macros for CCR_360 */
474 #define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */
475 #define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
476 #define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */
477 #define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */
478 #define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
479 #define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */
480 #define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */
481 #define CCM_CCR_360_FBCONFIG_MASK (0x00E0)
482 #define CCM_CCR_360_PLLMULT2_MASK (0x0003)
483 #define CCM_CCR_360_PLLMULT3_MASK (0x0007)
484 #define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000)
485 #define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020)
486 #define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040)
487 #define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060)
488 #define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080)
489 #define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0)
490 #define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0)
491 #define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0)
492 #define CCM_CCR_360_PLLMULT2_12X (0x0000)
493 #define CCM_CCR_360_PLLMULT2_6X (0x0001)
494 #define CCM_CCR_360_PLLMULT2_16X (0x0002)
495 #define CCM_CCR_360_PLLMULT2_8X (0x0003)
496 #define CCM_CCR_360_PLLMULT3_20X (0x0000)
497 #define CCM_CCR_360_PLLMULT3_10X (0x0001)
498 #define CCM_CCR_360_PLLMULT3_24X (0x0002)
499 #define CCM_CCR_360_PLLMULT3_18X (0x0003)
500 #define CCM_CCR_360_PLLMULT3_12X (0x0004)
501 #define CCM_CCR_360_PLLMULT3_6X (0x0005)
502 #define CCM_CCR_360_PLLMULT3_16X (0x0006)
503 #define CCM_CCR_360_PLLMULT3_8X (0x0007)
505 /* Bit definitions and macros for CCR_256 */
506 #define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */
507 #define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */
508 #define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */
509 #define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
510 #define CCM_CCR_256_FBCONFIG_MASK (0x00E0)
511 #define CCM_CCR_256_FBCONFIG_NM_32 (0x0000)
512 #define CCM_CCR_256_FBCONFIG_NM_8 (0x0020)
513 #define CCM_CCR_256_FBCONFIG_NM_16 (0x0040)
514 #define CCM_CCR_256_FBCONFIG_M_32 (0x0080)
515 #define CCM_CCR_256_FBCONFIG_M_8 (0x00A0)
516 #define CCM_CCR_256_FBCONFIG_M_16 (0x00C0)
517 #define CCM_CCR_256_PLLMULT3_MASK (0x0007)
518 #define CCM_CCR_256_PLLMULT3_20X (0x0000)
519 #define CCM_CCR_256_PLLMULT3_10X (0x0001)
520 #define CCM_CCR_256_PLLMULT3_24X (0x0002)
521 #define CCM_CCR_256_PLLMULT3_18X (0x0003)
522 #define CCM_CCR_256_PLLMULT3_12X (0x0004)
523 #define CCM_CCR_256_PLLMULT3_6X (0x0005)
524 #define CCM_CCR_256_PLLMULT3_16X (0x0006)
525 #define CCM_CCR_256_PLLMULT3_8X (0x0007)
527 /* Bit definitions and macros for RCON_360 */
528 #define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */
529 #define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
530 #define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */
531 #define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */
532 #define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
534 /* Bit definitions and macros for RCON_256 */
535 #define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */
536 #define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */
537 #define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */
538 #define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
540 /* Bit definitions and macros for CIR */
541 #define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */
542 #define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */
543 #define CCM_CIR_PIN_MASK (0xFFC0)
544 #define CCM_CIR_PRN_MASK (0x003F)
545 #define CCM_CIR_PIN_MCF54450 (0x4F<<6)
546 #define CCM_CIR_PIN_MCF54451 (0x4D<<6)
547 #define CCM_CIR_PIN_MCF54452 (0x4B<<6)
548 #define CCM_CIR_PIN_MCF54453 (0x49<<6)
549 #define CCM_CIR_PIN_MCF54454 (0x4A<<6)
550 #define CCM_CIR_PIN_MCF54455 (0x48<<6)
552 /* Bit definitions and macros for MISCCR */
553 #define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
554 #define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */
555 #define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */
556 #define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
557 #define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
558 #define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
559 #define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
560 #define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */
561 #define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */
562 #define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
563 #define CCM_MISCCR_BMT_65536 (0)
564 #define CCM_MISCCR_BMT_32768 (1)
565 #define CCM_MISCCR_BMT_16384 (2)
566 #define CCM_MISCCR_BMT_8192 (3)
567 #define CCM_MISCCR_BMT_4096 (4)
568 #define CCM_MISCCR_BMT_2048 (5)
569 #define CCM_MISCCR_BMT_1024 (6)
570 #define CCM_MISCCR_BMT_512 (7)
571 #define CCM_MISCCR_SSIPUS_UP (1)
572 #define CCM_MISCCR_SSIPUS_DOWN (0)
573 #define CCM_MISCCR_TIMDMA_TIM (1)
574 #define CCM_MISCCR_TIMDMA_SSI (0)
575 #define CCM_MISCCR_SSISRC_CLKIN (0)
576 #define CCM_MISCCR_SSISRC_PLL (1)
577 #define CCM_MISCCR_USBOC_ACTHI (0)
578 #define CCM_MISCCR_USBOV_ACTLO (1)
579 #define CCM_MISCCR_USBSRC_CLKIN (0)
580 #define CCM_MISCCR_USBSRC_PLL (1)
582 /* Bit definitions and macros for CDR */
583 #define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */
584 #define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */
586 /* Bit definitions and macros for UOCSR */
587 #define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */
588 #define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */
589 #define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
590 #define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */
591 #define CCM_UOCSR_SEND (0x0010) /* Session end */
592 #define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
593 #define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
594 #define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
595 #define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */
596 #define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */
597 #define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */
598 #define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */
599 #define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */
601 /*********************************************************************
602 * General Purpose I/O Module (GPIO)
603 *********************************************************************/
605 /* Bit definitions and macros for PAR_FEC */
606 #define GPIO_PAR_FEC_FEC0(x) (((x)&0x07))
607 #define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4)
608 #define GPIO_PAR_FEC_FEC1_MASK (0x8F)
609 #define GPIO_PAR_FEC_FEC1_MII (0x70)
610 #define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30)
611 #define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20)
612 #define GPIO_PAR_FEC_FEC1_ATA (0x10)
613 #define GPIO_PAR_FEC_FEC1_GPIO (0x00)
614 #define GPIO_PAR_FEC_FEC0_MASK (0xF8)
615 #define GPIO_PAR_FEC_FEC0_MII (0x07)
616 #define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
617 #define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
618 #define GPIO_PAR_FEC_FEC0_ULPI (0x01)
619 #define GPIO_PAR_FEC_FEC0_GPIO (0x00)
621 /* Bit definitions and macros for PAR_DMA */
622 #define GPIO_PAR_DMA_DREQ0 (0x01)
623 #define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2)
624 #define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4)
625 #define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
626 #define GPIO_PAR_DMA_DACK1_MASK (0x3F)
627 #define GPIO_PAR_DMA_DACK1_DACK1 (0xC0)
628 #define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40)
629 #define GPIO_PAR_DMA_DACK1_GPIO (0x00)
630 #define GPIO_PAR_DMA_DREQ1_MASK (0xCF)
631 #define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30)
632 #define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
633 #define GPIO_PAR_DMA_DREQ1_GPIO (0x00)
634 #define GPIO_PAR_DMA_DACK0_MASK (0xF3)
635 #define GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
636 #define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
637 #define GPIO_PAR_DMA_DACK0_GPIO (0x00)
638 #define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01)
639 #define GPIO_PAR_DMA_DREQ0_GPIO (0x00)
641 /* Bit definitions and macros for PAR_FBCTL */
642 #define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3)
643 #define GPIO_PAR_FBCTL_RW (0x20)
644 #define GPIO_PAR_FBCTL_TA (0x40)
645 #define GPIO_PAR_FBCTL_OE (0x80)
646 #define GPIO_PAR_FBCTL_OE_OE (0x80)
647 #define GPIO_PAR_FBCTL_OE_GPIO (0x00)
648 #define GPIO_PAR_FBCTL_TA_TA (0x40)
649 #define GPIO_PAR_FBCTL_TA_GPIO (0x00)
650 #define GPIO_PAR_FBCTL_RW_RW (0x20)
651 #define GPIO_PAR_FBCTL_RW_GPIO (0x00)
652 #define GPIO_PAR_FBCTL_TS_MASK (0xE7)
653 #define GPIO_PAR_FBCTL_TS_TS (0x18)
654 #define GPIO_PAR_FBCTL_TS_ALE (0x10)
655 #define GPIO_PAR_FBCTL_TS_TBST (0x08)
656 #define GPIO_PAR_FBCTL_TS_GPIO (0x80)
658 /* Bit definitions and macros for PAR_DSPI */
659 #define GPIO_PAR_DSPI_SCK (0x01)
660 #define GPIO_PAR_DSPI_SOUT (0x02)
661 #define GPIO_PAR_DSPI_SIN (0x04)
662 #define GPIO_PAR_DSPI_PCS0 (0x08)
663 #define GPIO_PAR_DSPI_PCS1 (0x10)
664 #define GPIO_PAR_DSPI_PCS2 (0x20)
665 #define GPIO_PAR_DSPI_PCS5 (0x40)
666 #define GPIO_PAR_DSPI_PCS5_PCS5 (0x40)
667 #define GPIO_PAR_DSPI_PCS5_GPIO (0x00)
668 #define GPIO_PAR_DSPI_PCS2_PCS2 (0x20)
669 #define GPIO_PAR_DSPI_PCS2_GPIO (0x00)
670 #define GPIO_PAR_DSPI_PCS1_PCS1 (0x10)
671 #define GPIO_PAR_DSPI_PCS1_GPIO (0x00)
672 #define GPIO_PAR_DSPI_PCS0_PCS0 (0x08)
673 #define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
674 #define GPIO_PAR_DSPI_SIN_SIN (0x04)
675 #define GPIO_PAR_DSPI_SIN_GPIO (0x00)
676 #define GPIO_PAR_DSPI_SOUT_SOUT (0x02)
677 #define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
678 #define GPIO_PAR_DSPI_SCK_SCK (0x01)
679 #define GPIO_PAR_DSPI_SCK_GPIO (0x00)
681 /* Bit definitions and macros for PAR_BE */
682 #define GPIO_PAR_BE_BS0 (0x01)
683 #define GPIO_PAR_BE_BS1 (0x04)
684 #define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
685 #define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
686 #define GPIO_PAR_BE_BE3_MASK (0x3F)
687 #define GPIO_PAR_BE_BE3_BE3 (0xC0)
688 #define GPIO_PAR_BE_BE3_TSIZ1 (0x80)
689 #define GPIO_PAR_BE_BE3_GPIO (0x00)
690 #define GPIO_PAR_BE_BE2_MASK (0xCF)
691 #define GPIO_PAR_BE_BE2_BE2 (0x30)
692 #define GPIO_PAR_BE_BE2_TSIZ0 (0x20)
693 #define GPIO_PAR_BE_BE2_GPIO (0x00)
694 #define GPIO_PAR_BE_BE1_BE1 (0x04)
695 #define GPIO_PAR_BE_BE1_GPIO (0x00)
696 #define GPIO_PAR_BE_BE0_BE0 (0x01)
697 #define GPIO_PAR_BE_BE0_GPIO (0x00)
699 /* Bit definitions and macros for PAR_CS */
700 #define GPIO_PAR_CS_CS1 (0x02)
701 #define GPIO_PAR_CS_CS2 (0x04)
702 #define GPIO_PAR_CS_CS3 (0x08)
703 #define GPIO_PAR_CS_CS3_CS3 (0x08)
704 #define GPIO_PAR_CS_CS3_GPIO (0x00)
705 #define GPIO_PAR_CS_CS2_CS2 (0x04)
706 #define GPIO_PAR_CS_CS2_GPIO (0x00)
707 #define GPIO_PAR_CS_CS1_CS1 (0x02)
708 #define GPIO_PAR_CS_CS1_GPIO (0x00)
710 /* Bit definitions and macros for PAR_TIMER */
711 #define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03))
712 #define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
713 #define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
714 #define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
715 #define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
716 #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
717 #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
718 #define GPIO_PAR_TIMER_T3IN_U2RXD (0x40)
719 #define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
720 #define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
721 #define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
722 #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
723 #define GPIO_PAR_TIMER_T2IN_U2TXD (0x10)
724 #define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
725 #define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
726 #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
727 #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
728 #define GPIO_PAR_TIMER_T1IN_U2CTS (0x04)
729 #define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
730 #define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
731 #define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
732 #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
733 #define GPIO_PAR_TIMER_T0IN_U2RTS (0x01)
734 #define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
736 /* Bit definitions and macros for PAR_USB */
737 #define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03))
738 #define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2)
739 #define GPIO_PAR_USB_VBUSEN_MASK (0xF3)
740 #define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C)
741 #define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08)
742 #define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04)
743 #define GPIO_PAR_USB_VBUSEN_GPIO (0x00)
744 #define GPIO_PAR_USB_VBUSOC_MASK (0xFC)
745 #define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03)
746 #define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01)
747 #define GPIO_PAR_USB_VBUSOC_GPIO (0x00)
749 /* Bit definitions and macros for PAR_UART */
750 #define GPIO_PAR_UART_U0TXD (0x01)
751 #define GPIO_PAR_UART_U0RXD (0x02)
752 #define GPIO_PAR_UART_U0RTS (0x04)
753 #define GPIO_PAR_UART_U0CTS (0x08)
754 #define GPIO_PAR_UART_U1TXD (0x10)
755 #define GPIO_PAR_UART_U1RXD (0x20)
756 #define GPIO_PAR_UART_U1RTS (0x40)
757 #define GPIO_PAR_UART_U1CTS (0x80)
758 #define GPIO_PAR_UART_U1CTS_U1CTS (0x80)
759 #define GPIO_PAR_UART_U1CTS_GPIO (0x00)
760 #define GPIO_PAR_UART_U1RTS_U1RTS (0x40)
761 #define GPIO_PAR_UART_U1RTS_GPIO (0x00)
762 #define GPIO_PAR_UART_U1RXD_U1RXD (0x20)
763 #define GPIO_PAR_UART_U1RXD_GPIO (0x00)
764 #define GPIO_PAR_UART_U1TXD_U1TXD (0x10)
765 #define GPIO_PAR_UART_U1TXD_GPIO (0x00)
766 #define GPIO_PAR_UART_U0CTS_U0CTS (0x08)
767 #define GPIO_PAR_UART_U0CTS_GPIO (0x00)
768 #define GPIO_PAR_UART_U0RTS_U0RTS (0x04)
769 #define GPIO_PAR_UART_U0RTS_GPIO (0x00)
770 #define GPIO_PAR_UART_U0RXD_U0RXD (0x02)
771 #define GPIO_PAR_UART_U0RXD_GPIO (0x00)
772 #define GPIO_PAR_UART_U0TXD_U0TXD (0x01)
773 #define GPIO_PAR_UART_U0TXD_GPIO (0x00)
775 /* Bit definitions and macros for PAR_FECI2C */
776 #define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003))
777 #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2)
778 #define GPIO_PAR_FECI2C_MDIO0 (0x0010)
779 #define GPIO_PAR_FECI2C_MDC0 (0x0040)
780 #define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8)
781 #define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10)
782 #define GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF)
783 #define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00)
784 #define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
785 #define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000)
786 #define GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF)
787 #define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300)
788 #define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
789 #define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000)
790 #define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040)
791 #define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000)
792 #define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010)
793 #define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000)
794 #define GPIO_PAR_FECI2C_SCL_MASK (0xFFF3)
795 #define GPIO_PAR_FECI2C_SCL_SCL (0x000C)
796 #define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004)
797 #define GPIO_PAR_FECI2C_SCL_GPIO (0x0000)
798 #define GPIO_PAR_FECI2C_SDA_MASK (0xFFFC)
799 #define GPIO_PAR_FECI2C_SDA_SDA (0x0003)
800 #define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001)
801 #define GPIO_PAR_FECI2C_SDA_GPIO (0x0000)
803 /* Bit definitions and macros for PAR_SSI */
804 #define GPIO_PAR_SSI_MCLK (0x0001)
805 #define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2)
806 #define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4)
807 #define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6)
808 #define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8)
809 #define GPIO_PAR_SSI_BCLK_MASK (0xFCFF)
810 #define GPIO_PAR_SSI_BCLK_BCLK (0x0300)
811 #define GPIO_PAR_SSI_BCLK_U1CTS (0x0200)
812 #define GPIO_PAR_SSI_BCLK_GPIO (0x0000)
813 #define GPIO_PAR_SSI_FS_MASK (0xFF3F)
814 #define GPIO_PAR_SSI_FS_FS (0x00C0)
815 #define GPIO_PAR_SSI_FS_U1RTS (0x0080)
816 #define GPIO_PAR_SSI_FS_GPIO (0x0000)
817 #define GPIO_PAR_SSI_SRXD_MASK (0xFFCF)
818 #define GPIO_PAR_SSI_SRXD_SRXD (0x0030)
819 #define GPIO_PAR_SSI_SRXD_U1RXD (0x0020)
820 #define GPIO_PAR_SSI_SRXD_GPIO (0x0000)
821 #define GPIO_PAR_SSI_STXD_MASK (0xFFF3)
822 #define GPIO_PAR_SSI_STXD_STXD (0x000C)
823 #define GPIO_PAR_SSI_STXD_U1TXD (0x0008)
824 #define GPIO_PAR_SSI_STXD_GPIO (0x0000)
825 #define GPIO_PAR_SSI_MCLK_MCLK (0x0001)
826 #define GPIO_PAR_SSI_MCLK_GPIO (0x0000)
828 /* Bit definitions and macros for PAR_ATA */
829 #define GPIO_PAR_ATA_IORDY (0x0001)
830 #define GPIO_PAR_ATA_DMARQ (0x0002)
831 #define GPIO_PAR_ATA_RESET (0x0004)
832 #define GPIO_PAR_ATA_DA0 (0x0020)
833 #define GPIO_PAR_ATA_DA1 (0x0040)
834 #define GPIO_PAR_ATA_DA2 (0x0080)
835 #define GPIO_PAR_ATA_CS0 (0x0100)
836 #define GPIO_PAR_ATA_CS1 (0x0200)
837 #define GPIO_PAR_ATA_BUFEN (0x0400)
838 #define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400)
839 #define GPIO_PAR_ATA_BUFEN_GPIO (0x0000)
840 #define GPIO_PAR_ATA_CS1_CS1 (0x0200)
841 #define GPIO_PAR_ATA_CS1_GPIO (0x0000)
842 #define GPIO_PAR_ATA_CS0_CS0 (0x0100)
843 #define GPIO_PAR_ATA_CS0_GPIO (0x0000)
844 #define GPIO_PAR_ATA_DA2_DA2 (0x0080)
845 #define GPIO_PAR_ATA_DA2_GPIO (0x0000)
846 #define GPIO_PAR_ATA_DA1_DA1 (0x0040)
847 #define GPIO_PAR_ATA_DA1_GPIO (0x0000)
848 #define GPIO_PAR_ATA_DA0_DA0 (0x0020)
849 #define GPIO_PAR_ATA_DA0_GPIO (0x0000)
850 #define GPIO_PAR_ATA_RESET_RESET (0x0004)
851 #define GPIO_PAR_ATA_RESET_GPIO (0x0000)
852 #define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002)
853 #define GPIO_PAR_ATA_DMARQ_GPIO (0x0000)
854 #define GPIO_PAR_ATA_IORDY_IORDY (0x0001)
855 #define GPIO_PAR_ATA_IORDY_GPIO (0x0000)
857 /* Bit definitions and macros for PAR_IRQ */
858 #define GPIO_PAR_IRQ_IRQ1 (0x02)
859 #define GPIO_PAR_IRQ_IRQ4 (0x10)
860 #define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10)
861 #define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
862 #define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02)
863 #define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
865 /* Bit definitions and macros for PAR_PCI */
866 #define GPIO_PAR_PCI_REQ0 (0x0001)
867 #define GPIO_PAR_PCI_REQ1 (0x0004)
868 #define GPIO_PAR_PCI_REQ2 (0x0010)
869 #define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6)
870 #define GPIO_PAR_PCI_GNT0 (0x0100)
871 #define GPIO_PAR_PCI_GNT1 (0x0400)
872 #define GPIO_PAR_PCI_GNT2 (0x1000)
873 #define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14)
874 #define GPIO_PAR_PCI_GNT3_MASK (0x3FFF)
875 #define GPIO_PAR_PCI_GNT3_GNT3 (0xC000)
876 #define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000)
877 #define GPIO_PAR_PCI_GNT3_GPIO (0x0000)
878 #define GPIO_PAR_PCI_GNT2_GNT2 (0x1000)
879 #define GPIO_PAR_PCI_GNT2_GPIO (0x0000)
880 #define GPIO_PAR_PCI_GNT1_GNT1 (0x0400)
881 #define GPIO_PAR_PCI_GNT1_GPIO (0x0000)
882 #define GPIO_PAR_PCI_GNT0_GNT0 (0x0100)
883 #define GPIO_PAR_PCI_GNT0_GPIO (0x0000)
884 #define GPIO_PAR_PCI_REQ3_MASK (0xFF3F)
885 #define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0)
886 #define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080)
887 #define GPIO_PAR_PCI_REQ3_GPIO (0x0000)
888 #define GPIO_PAR_PCI_REQ2_REQ2 (0x0010)
889 #define GPIO_PAR_PCI_REQ2_GPIO (0x0000)
890 #define GPIO_PAR_PCI_REQ1_REQ1 (0x0040)
891 #define GPIO_PAR_PCI_REQ1_GPIO (0x0000)
892 #define GPIO_PAR_PCI_REQ0_REQ0 (0x0001)
893 #define GPIO_PAR_PCI_REQ0_GPIO (0x0000)
895 /* Bit definitions and macros for MSCR_SDRAM */
896 #define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03))
897 #define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
898 #define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4)
899 #define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6)
900 #define GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F)
901 #define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0)
902 #define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80)
903 #define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
904 #define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
905 #define GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF)
906 #define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30)
907 #define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20)
908 #define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10)
909 #define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00)
910 #define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
911 #define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C)
912 #define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08)
913 #define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04)
914 #define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00)
915 #define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
916 #define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03)
917 #define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02)
918 #define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01)
919 #define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00)
921 /* Bit definitions and macros for MSCR_PCI */
922 #define GPIO_MSCR_PCI_PCI (0x01)
923 #define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01)
924 #define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00)
926 /* Bit definitions and macros for DSCR_I2C */
927 #define GPIO_DSCR_I2C_I2C(x) (((x)&0x03))
928 #define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03)
929 #define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02)
930 #define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01)
931 #define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00)
933 /* Bit definitions and macros for DSCR_FLEXBUS */
934 #define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03))
935 #define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2)
936 #define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4)
937 #define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6)
938 #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0)
939 #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80)
940 #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40)
941 #define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00)
942 #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30)
943 #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20)
944 #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10)
945 #define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00)
946 #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C)
947 #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08)
948 #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04)
949 #define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00)
950 #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03)
951 #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02)
952 #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01)
953 #define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00)
955 /* Bit definitions and macros for DSCR_FEC */
956 #define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03))
957 #define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2)
958 #define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C)
959 #define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08)
960 #define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04)
961 #define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00)
962 #define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03)
963 #define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02)
964 #define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01)
965 #define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00)
967 /* Bit definitions and macros for DSCR_UART */
968 #define GPIO_DSCR_UART_UART0(x) (((x)&0x03))
969 #define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2)
970 #define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C)
971 #define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08)
972 #define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04)
973 #define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00)
974 #define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03)
975 #define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02)
976 #define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01)
977 #define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00)
979 /* Bit definitions and macros for DSCR_DSPI */
980 #define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03))
981 #define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03)
982 #define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02)
983 #define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01)
984 #define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00)
986 /* Bit definitions and macros for DSCR_TIMER */
987 #define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03))
988 #define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03)
989 #define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02)
990 #define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01)
991 #define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00)
993 /* Bit definitions and macros for DSCR_SSI */
994 #define GPIO_DSCR_SSI_SSI(x) (((x)&0x03))
995 #define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03)
996 #define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02)
997 #define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01)
998 #define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00)
1000 /* Bit definitions and macros for DSCR_DMA */
1001 #define GPIO_DSCR_DMA_DMA(x) (((x)&0x03))
1002 #define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03)
1003 #define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02)
1004 #define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01)
1005 #define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00)
1007 /* Bit definitions and macros for DSCR_DEBUG */
1008 #define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03))
1009 #define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03)
1010 #define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02)
1011 #define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01)
1012 #define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00)
1014 /* Bit definitions and macros for DSCR_RESET */
1015 #define GPIO_DSCR_RESET_RESET(x) (((x)&0x03))
1016 #define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03)
1017 #define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02)
1018 #define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01)
1019 #define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00)
1021 /* Bit definitions and macros for DSCR_IRQ */
1022 #define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03))
1023 #define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03)
1024 #define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02)
1025 #define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01)
1026 #define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00)
1028 /* Bit definitions and macros for DSCR_USB */
1029 #define GPIO_DSCR_USB_USB(x) (((x)&0x03))
1030 #define GPIO_DSCR_USB_USB_LOAD_50PF (0x03)
1031 #define GPIO_DSCR_USB_USB_LOAD_30PF (0x02)
1032 #define GPIO_DSCR_USB_USB_LOAD_20PF (0x01)
1033 #define GPIO_DSCR_USB_USB_LOAD_10PF (0x00)
1035 /* Bit definitions and macros for DSCR_ATA */
1036 #define GPIO_DSCR_ATA_ATA(x) (((x)&0x03))
1037 #define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03)
1038 #define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02)
1039 #define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
1040 #define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
1042 /*********************************************************************
1043 * Random Number Generator (RNG)
1044 *********************************************************************/
1046 /* Bit definitions and macros for RNGCR */
1047 #define RNG_RNGCR_GO (0x00000001)
1048 #define RNG_RNGCR_HA (0x00000002)
1049 #define RNG_RNGCR_IM (0x00000004)
1050 #define RNG_RNGCR_CI (0x00000008)
1052 /* Bit definitions and macros for RNGSR */
1053 #define RNG_RNGSR_SV (0x00000001)
1054 #define RNG_RNGSR_LRS (0x00000002)
1055 #define RNG_RNGSR_FUF (0x00000004)
1056 #define RNG_RNGSR_EI (0x00000008)
1057 #define RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8)
1058 #define RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16)
1060 /*********************************************************************
1061 * SDRAM Controller (SDRAMC)
1062 *********************************************************************/
1064 /* Bit definitions and macros for SDMR */
1065 #define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
1066 #define SDRAMC_SDMR_CMD (0x00010000) /* Command */
1067 #define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
1068 #define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
1069 #define SDRAMC_SDMR_BK_LMR (0x00000000)
1070 #define SDRAMC_SDMR_BK_LEMR (0x40000000)
1072 /* Bit definitions and macros for SDCR */
1073 #define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
1074 #define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
1075 #define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
1076 #define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
1077 #define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
1078 #define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
1079 #define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
1080 #define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
1081 #define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
1082 #define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
1083 #define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
1084 #define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
1085 #define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
1086 #define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
1088 /* Bit definitions and macros for SDCFG1 */
1089 #define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
1090 #define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
1091 #define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
1092 #define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
1093 #define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
1094 #define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
1095 #define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
1097 /* Bit definitions and macros for SDCFG2 */
1098 #define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
1099 #define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
1100 #define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
1101 #define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
1103 /* Bit definitions and macros for SDCS group */
1104 #define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
1105 #define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
1106 #define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
1107 #define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
1108 #define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
1109 #define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
1110 #define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
1111 #define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
1112 #define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
1113 #define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
1114 #define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
1115 #define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
1116 #define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
1117 #define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
1118 #define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
1119 #define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
1120 #define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
1122 /*********************************************************************
1123 * Phase Locked Loop (PLL)
1124 *********************************************************************/
1126 /* Bit definitions and macros for PCR */
1127 #define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
1128 #define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */
1129 #define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */
1130 #define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */
1131 #define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
1132 #define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
1133 #define PLL_PCR_PFDR_MASK (0x000F0000)
1134 #define PLL_PCR_OUTDIV5_MASK (0x000F0000)
1135 #define PLL_PCR_OUTDIV4_MASK (0x0000F000)
1136 #define PLL_PCR_OUTDIV3_MASK (0x00000F00)
1137 #define PLL_PCR_OUTDIV2_MASK (0x000000F0)
1138 #define PLL_PCR_OUTDIV1_MASK (0x0000000F)
1140 /* Bit definitions and macros for PSR */
1141 #define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
1142 #define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
1143 #define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
1144 #define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
1146 /*********************************************************************
1148 *********************************************************************/
1150 /* Bit definitions and macros for SCR */
1151 #define PCI_SCR_PE (0x80000000) /* Parity Error detected */
1152 #define PCI_SCR_SE (0x40000000) /* System error signalled */
1153 #define PCI_SCR_MA (0x20000000) /* Master aboart received */
1154 #define PCI_SCR_TR (0x10000000) /* Target abort received */
1155 #define PCI_SCR_TS (0x08000000) /* Target abort signalled */
1156 #define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
1157 #define PCI_SCR_DP (0x01000000) /* Master data parity err */
1158 #define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
1159 #define PCI_SCR_R (0x00400000) /* Reserved */
1160 #define PCI_SCR_66M (0x00200000) /* 66Mhz */
1161 #define PCI_SCR_C (0x00100000) /* Capabilities list */
1162 #define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
1163 #define PCI_SCR_S (0x00000100) /* SERR enable */
1164 #define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
1165 #define PCI_SCR_PER (0x00000040) /* Parity error response */
1166 #define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
1167 #define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
1168 #define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
1169 #define PCI_SCR_B (0x00000004) /* Bus master enable */
1170 #define PCI_SCR_M (0x00000002) /* Memory access control */
1171 #define PCI_SCR_IO (0x00000001) /* I/O access control */
1173 #define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
1174 #define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
1175 #define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
1176 #define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
1178 #define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
1179 #define PCI_BAR_BAR1(x) (x & 0xFFF00000)
1180 #define PCI_BAR_BAR2(x) (x & 0xFFC00000)
1181 #define PCI_BAR_BAR3(x) (x & 0xFF000000)
1182 #define PCI_BAR_BAR4(x) (x & 0xF8000000)
1183 #define PCI_BAR_BAR5(x) (x & 0xE0000000)
1184 #define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
1185 #define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
1186 #define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
1188 #define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
1189 #define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
1190 #define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
1191 #define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
1193 #define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
1194 #define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
1195 #define PCI_GSCR_SE (0x10000000) /* SERR detected */
1196 #define PCI_GSCR_ER (0x08000000) /* Error response detected */
1197 #define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
1198 #define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
1199 #define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
1200 #define PCI_GSCR_PR (0x00000001) /* PCI reset */
1202 #define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
1203 #define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
1204 #define PCI_TCR1_P (0x00010000) /* Prefetch reads */
1205 #define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
1207 #define PCI_TCR2_B5E (0x00002000) /* */
1208 #define PCI_TCR2_B4E (0x00001000) /* */
1209 #define PCI_TCR2_B3E (0x00000800) /* */
1210 #define PCI_TCR2_B2E (0x00000400) /* */
1211 #define PCI_TCR2_B1E (0x00000200) /* */
1212 #define PCI_TCR2_B0E (0x00000100) /* */
1213 #define PCI_TCR2_CR (0x00000001) /* */
1215 #define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20)
1216 #define PCI_TBATR_EN (0x00000001) /* Enable */
1218 #define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
1219 #define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
1220 #define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
1221 #define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
1222 #define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
1223 #define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
1224 #define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
1225 #define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
1226 #define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
1227 #define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
1228 #define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
1229 #define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
1230 #define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
1231 #define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
1232 #define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
1234 #define PCI_ICR_REE (0x04000000) /* Retry error enable */
1235 #define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
1236 #define PCI_ICR_TAE (0x01000000) /* Target abort enable */
1237 #define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
1239 /********************************************************************/
1241 #endif /* __MCF5445X__ */
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