2 * mcf5271.h -- Definitions for Motorola Coldfire 5271
4 * (C) Copyright 2006, Lab X Technologies <zachary.landau@labxtechnologies.com>
5 * Based on mcf5272sim.h of uCLinux distribution:
6 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x))
33 #define mbar_readShort(x) *((volatile unsigned short *) (CFG_MBAR + x))
34 #define mbar_readByte(x) *((volatile unsigned char *) (CFG_MBAR + x))
35 #define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y
36 #define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y
37 #define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y
39 #define MCF_FMPLL_SYNCR 0x120000
40 #define MCF_FMPLL_SYNSR 0x120004
41 #define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24)
42 #define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19)
43 #define MCF_FMPLL_SYNSR_LOCK 0x8
45 #define MCF_WTM_WCR 0x140000
46 #define MCF_WTM_WCNTR 0x140004
47 #define MCF_WTM_WSR 0x140006
48 #define MCF_WTM_WCR_EN 0x0001
50 #define MCF_RCM_RCR 0x110000
51 #define MCF_RCM_RCR_FRCRSTOUT 0x40
52 #define MCF_RCM_RCR_SOFTRST 0x80
54 #define MCF_GPIO_PAR_CS 0x100045
55 #define MCF_GPIO_PAR_SDRAM 0x100046
56 #define MCF_GPIO_PAR_FECI2C 0x100047
57 #define MCF_GPIO_PAR_UART 0x100048
59 #define MCF_GPIO_PAR_CS_PAR_CS2 (0x04)
61 #define MCF_GPIO_PAR_UART_U0RTS (0x0001)
62 #define MCF_GPIO_PAR_UART_U0CTS (0x0002)
63 #define MCF_GPIO_PAR_UART_U0TXD (0x0004)
64 #define MCF_GPIO_PAR_UART_U0RXD (0x0008)
65 #define MCF_GPIO_PAR_UART_U1RXD_UART1 (0x0C00)
66 #define MCF_GPIO_PAR_UART_U1TXD_UART1 (0x0300)
68 #define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
70 #define MCF_SDRAMC_DCR 0x000040
71 #define MCF_SDRAMC_DACR0 0x000048
72 #define MCF_SDRAMC_DMR0 0x00004C
74 #define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
75 #define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
76 #define MCF_SDRAMC_DCR_IS (0x0800)
77 #define MCF_SDRAMC_DCR_COC (0x1000)
78 #define MCF_SDRAMC_DCR_NAM (0x2000)
80 #define MCF_SDRAMC_DACRn_IP (0x00000008)
81 #define MCF_SDRAMC_DACRn_PS(x) (((x)&0x00000003)<<4)
82 #define MCF_SDRAMC_DACRn_MRS (0x00000040)
83 #define MCF_SDRAMC_DACRn_CBM(x) (((x)&0x00000007)<<8)
84 #define MCF_SDRAMC_DACRn_CASL(x) (((x)&0x00000003)<<12)
85 #define MCF_SDRAMC_DACRn_RE (0x00008000)
86 #define MCF_SDRAMC_DACRn_BA(x) (((x)&0x00003FFF)<<18)
88 #define MCF_SDRAMC_DMRn_BAM_8M (0x007C0000)
89 #define MCF_SDRAMC_DMRn_V (0x00000001)
91 #define MCFSIM_ICR1 (0x000C41)
93 #endif /* _MCF5271_H_ */