include/asm-m68k/immap_5329.h

   1 /*
   2  * MCF5329 Internal Memory Map
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __IMMAP_5329__
  27 #define __IMMAP_5329__
  28
  29 #define MMAP_SCM1       0xEC000000
  30 #define MMAP_MDHA       0xEC080000
  31 #define MMAP_SKHA       0xEC084000
  32 #define MMAP_RNG        0xEC088000
  33 #define MMAP_SCM2       0xFC000000
  34 #define MMAP_XBS        0xFC004000
  35 #define MMAP_FBCS       0xFC008000
  36 #define MMAP_CAN        0xFC020000
  37 #define MMAP_FEC        0xFC030000
  38 #define MMAP_SCM3       0xFC040000
  39 #define MMAP_EDMA       0xFC044000
  40 #define MMAP_TCD        0xFC045000
  41 #define MMAP_INTC0      0xFC048000
  42 #define MMAP_INTC1      0xFC04C000
  43 #define MMAP_INTCACK    0xFC054000
  44 #define MMAP_I2C        0xFC058000
  45 #define MMAP_QSPI       0xFC05C000
  46 #define MMAP_UART0      0xFC060000
  47 #define MMAP_UART1      0xFC064000
  48 #define MMAP_UART2      0xFC068000
  49 #define MMAP_DTMR0      0xFC070000
  50 #define MMAP_DTMR1      0xFC074000
  51 #define MMAP_DTMR2      0xFC078000
  52 #define MMAP_DTMR3      0xFC07C000
  53 #define MMAP_PIT0       0xFC080000
  54 #define MMAP_PIT1       0xFC084000
  55 #define MMAP_PIT2       0xFC088000
  56 #define MMAP_PIT3       0xFC08C000
  57 #define MMAP_PWM        0xFC090000
  58 #define MMAP_EPORT      0xFC094000
  59 #define MMAP_WDOG       0xFC098000
  60 #define MMAP_CCM        0xFC0A0000
  61 #define MMAP_GPIO       0xFC0A4000
  62 #define MMAP_RTC        0xFC0A8000
  63 #define MMAP_LCDC       0xFC0AC000
  64 #define MMAP_USBOTG     0xFC0B0000
  65 #define MMAP_USBH       0xFC0B4000
  66 #define MMAP_SDRAM      0xFC0B8000
  67 #define MMAP_SSI        0xFC0BC000
  68 #define MMAP_PLL        0xFC0C0000
  69
  70 /* System control module registers */
  71 typedef struct scm1_ctrl {
  72         u32 mpr0;               /* 0x00 Master Privilege Register 0 */
  73         u32 res1[15];           /* 0x04 - 0x3F */
  74         u32 pacrh;              /* 0x40 Peripheral Access Control Register H */
  75         u32 res2[3];            /* 0x44 - 0x53 */
  76         u32 bmt0;               /*0x54 Bus Monitor Timeout 0 */
  77 } scm1_t;
  78
  79 /* Message Digest Hardware Accelerator */
  80 typedef struct mdha_ctrl {
  81         u32 mdmr;               /* 0x00 MDHA Mode Register */
  82         u32 mdcr;               /* 0x04 Control register */
  83         u32 mdcmr;              /* 0x08 Command Register */
  84         u32 mdsr;               /* 0x0C Status Register */
  85         u32 mdisr;              /* 0x10 Interrupt Status Register */
  86         u32 mdimr;              /* 0x14 Interrupt Mask Register */
  87         u32 mddsr;              /* 0x1C Data Size Register */
  88         u32 mdin;               /* 0x20 Input FIFO */
  89         u32 res1[3];            /* 0x24 - 0x2F */
  90         u32 mdao;               /* 0x30 Message Digest AO Register */
  91         u32 mdbo;               /* 0x34 Message Digest BO Register */
  92         u32 mdco;               /* 0x38 Message Digest CO Register */
  93         u32 mddo;               /* 0x3C Message Digest DO Register */
  94         u32 mdeo;               /* 0x40 Message Digest EO Register */
  95         u32 mdmds;              /* 0x44 Message Data Size Register */
  96         u32 res[10];            /* 0x48 - 0x6F */
  97         u32 mda1;               /* 0x70 Message Digest A1 Register */
  98         u32 mdb1;               /* 0x74 Message Digest B1 Register */
  99         u32 mdc1;               /* 0x78 Message Digest C1 Register */
 100         u32 mdd1;               /* 0x7C Message Digest D1 Register */
 101         u32 mde1;               /* 0x80 Message Digest E1 Register */
 102 } mdha_t;
 103
 104 /* Symmetric Key Hardware Accelerator */
 105 typedef struct skha_ctrl {
 106         u32 mr;                 /* 0x00 Mode Register */
 107         u32 cr;                 /* 0x04 Control Register */
 108         u32 cmr;                /* 0x08 Command Register */
 109         u32 sr;                 /* 0x0C Status Register */
 110         u32 esr;                /* 0x10 Error Status Register */
 111         u32 emr;                /* 0x14 Error Status Mask Register) */
 112         u32 ksr;                /* 0x18 Key Size Register */
 113         u32 dsr;                /* 0x1C Data Size Register */
 114         u32 in;                 /* 0x20 Input FIFO */
 115         u32 out;                /* 0x24 Output FIFO */
 116         u32 res1[2];            /* 0x28 - 0x2F */
 117         u32 kdr1;               /* 0x30 Key Data Register 1  */
 118         u32 kdr2;               /* 0x34 Key Data Register 2 */
 119         u32 kdr3;               /* 0x38 Key Data Register 3 */
 120         u32 kdr4;               /* 0x3C Key Data Register 4 */
 121         u32 kdr5;               /* 0x40 Key Data Register 5 */
 122         u32 kdr6;               /* 0x44 Key Data Register 6 */
 123         u32 res2[10];           /* 0x48 - 0x6F */
 124         u32 c1;                 /* 0x70 Context 1 */
 125         u32 c2;                 /* 0x74 Context 2 */
 126         u32 c3;                 /* 0x78 Context 3 */
 127         u32 c4;                 /* 0x7C Context 4 */
 128         u32 c5;                 /* 0x80 Context 5 */
 129         u32 c6;                 /* 0x84 Context 6 */
 130         u32 c7;                 /* 0x88 Context 7 */
 131         u32 c8;                 /* 0x8C Context 8 */
 132         u32 c9;                 /* 0x90 Context 9 */
 133         u32 c10;                /* 0x94 Context 10 */
 134         u32 c11;                /* 0x98 Context 11 */
 135 } skha_t;
 136
 137 /* Random Number Generator */
 138 typedef struct rng_ctrl {
 139         u32 rngcr;              /* 0x00 RNG Control Register */
 140         u32 rngsr;              /* 0x04 RNG Status Register */
 141         u32 rnger;              /* 0x08 RNG Entropy Register */
 142         u32 rngout;             /* 0x0C RNG Output FIFO */
 143 } rng_t;
 144
 145 /* System control module registers 2 */
 146 typedef struct scm2_ctrl {
 147         u32 mpr1;               /* 0x00 Master Privilege Register */
 148         u32 res1[7];            /* 0x04 - 0x1F */
 149         u32 pacra;              /* 0x20 Peripheral Access Control Register A */
 150         u32 pacrb;              /* 0x24 Peripheral Access Control Register B */
 151         u32 pacrc;              /* 0x28 Peripheral Access Control Register C */
 152         u32 pacrd;              /* 0x2C Peripheral Access Control Register D */
 153         u32 res2[4];            /* 0x30 - 0x3F */
 154         u32 pacre;              /* 0x40 Peripheral Access Control Register E */
 155         u32 pacrf;              /* 0x44 Peripheral Access Control Register F */
 156         u32 pacrg;              /* 0x48 Peripheral Access Control Register G */
 157         u32 res3[2];            /* 0x4C - 0x53 */
 158         u32 bmt1;               /* 0x54 Bus Monitor Timeout 1 */
 159 } scm2_t;
 160
 161 /* Cross-Bar Switch Module */
 162 typedef struct xbs_ctrl {
 163         u32 prs1;               /* 0x100 Priority Register Slave 1 */
 164         u32 res1[3];            /* 0x104 - 0F */
 165         u32 crs1;               /* 0x110 Control Register Slave 1 */
 166         u32 res2[187];          /* 0x114 - 0x3FF */
 167
 168         u32 prs4;               /* 0x400 Priority Register Slave 4 */
 169         u32 res3[3];            /* 0x404 - 0F */
 170         u32 crs4;               /* 0x410 Control Register Slave 4 */
 171         u32 res4[123];          /* 0x414 - 0x5FF */
 172
 173         u32 prs6;               /* 0x600 Priority Register Slave 6 */
 174         u32 res5[3];            /* 0x604 - 0F */
 175         u32 crs6;               /* 0x610 Control Register Slave 6 */
 176         u32 res6[59];           /* 0x614 - 0x6FF */
 177
 178         u32 prs7;               /* 0x700 Priority Register Slave 7 */
 179         u32 res7[3];            /* 0x704 - 0F */
 180         u32 crs7;               /* 0x710 Control Register Slave 7 */
 181 } xbs_t;
 182
 183 /* Flexbus module Chip select registers */
 184 typedef struct fbcs_ctrl {
 185         u16 csar0;              /* 0x00 Chip-Select Address Register 0 */
 186         u16 res0;
 187         u32 csmr0;              /* 0x04 Chip-Select Mask Register 0 */
 188         u32 cscr0;              /* 0x08 Chip-Select Control Register 0 */
 189
 190         u16 csar1;              /* 0x0C Chip-Select Address Register 1 */
 191         u16 res1;
 192         u32 csmr1;              /* 0x10 Chip-Select Mask Register 1 */
 193         u32 cscr1;              /* 0x14 Chip-Select Control Register 1 */
 194
 195         u16 csar2;              /* 0x18 Chip-Select Address Register 2 */
 196         u16 res2;
 197         u32 csmr2;              /* 0x1C Chip-Select Mask Register 2 */
 198         u32 cscr2;              /* 0x20 Chip-Select Control Register 2 */
 199
 200         u16 csar3;              /* 0x24 Chip-Select Address Register 3 */
 201         u16 res3;
 202         u32 csmr3;              /* 0x28 Chip-Select Mask Register 3 */
 203         u32 cscr3;              /* 0x2C Chip-Select Control Register 3 */
 204
 205         u16 csar4;              /* 0x30 Chip-Select Address Register 4 */
 206         u16 res4;
 207         u32 csmr4;              /* 0x34 Chip-Select Mask Register 4 */
 208         u32 cscr4;              /* 0x38 Chip-Select Control Register 4 */
 209
 210         u16 csar5;              /* 0x3C Chip-Select Address Register 5 */
 211         u16 res5;
 212         u32 csmr5;              /* 0x40 Chip-Select Mask Register 5 */
 213         u32 cscr5;              /* 0x44 Chip-Select Control Register 5 */
 214 } fbcs_t;
 215
 216 /* FlexCan module registers */
 217 typedef struct can_ctrl {
 218         u32 mcr;                /* 0x00 Module Configuration register */
 219         u32 ctrl;               /* 0x04 Control register */
 220         u32 timer;              /* 0x08 Free Running Timer */
 221         u32 res1;               /* 0x0C */
 222         u32 rxgmask;            /* 0x10 Rx Global Mask */
 223         u32 rx14mask;           /* 0x14 RxBuffer 14 Mask */
 224         u32 rx15mask;           /* 0x18 RxBuffer 15 Mask */
 225         u32 errcnt;             /* 0x1C Error Counter Register */
 226         u32 errstat;            /* 0x20 Error and status Register */
 227         u32 res2;               /* 0x24 */
 228         u32 imask;              /* 0x28 Interrupt Mask Register */
 229         u32 res3;               /* 0x2C */
 230         u32 iflag;              /* 0x30 Interrupt Flag Register */
 231         u32 res4[19];           /* 0x34 - 0x7F */
 232         u32 MB0_15[2048];       /* 0x80 Message Buffer 0-15 */
 233 } can_t;
 234
 235 /* System Control Module register 3 */
 236 typedef struct scm3_ctrl {
 237         u8 res1[19];            /* 0x00 - 0x12 */
 238         u8 wcr;                 /* 0x13 wakeup control register */
 239         u16 res2;               /* 0x14 - 0x15 */
 240         u16 cwcr;               /* 0x16 Core Watchdog Control Register */
 241         u8 res3[3];             /* 0x18 - 0x1A */
 242         u8 cwsr;                /* 0x1B Core Watchdog Service Register */
 243         u8 res4[2];             /* 0x1C - 0x1D */
 244         u8 scmisr;              /* 0x1F Interrupt Status Register */
 245         u32 res5;               /* 0x20 */
 246         u32 bcr;                /* 0x24 Burst Configuration Register */
 247         u32 res6[18];           /* 0x28 - 0x6F */
 248         u32 cfadr;              /* 0x70 Core Fault Address Register */
 249         u8 res7[4];             /* 0x71 - 0x74 */
 250         u8 cfier;               /* 0x75 Core Fault Interrupt Enable Register */
 251         u8 cfloc;               /* 0x76 Core Fault Location Register */
 252         u8 cfatr;               /* 0x77 Core Fault Attributes Register */
 253         u32 res8;               /* 0x78 */
 254         u32 cfdtr;              /* 0x7C Core Fault Data Register */
 255 } scm3_t;
 256
 257 /* eDMA module registers */
 258 typedef struct edma_ctrl {
 259         u32 cr;                 /* 0x00 Control Register */
 260         u32 es;                 /* 0x04 Error Status Register */
 261         u16 res1[3];            /* 0x08 - 0x0D */
 262         u16 erq;                /* 0x0E Enable Request Register */
 263         u16 res2[3];            /* 0x10 - 0x15 */
 264         u16 eei;                /* 0x16 Enable Error Interrupt Request */
 265         u8 serq;                /* 0x18 Set Enable Request */
 266         u8 cerq;                /* 0x19 Clear Enable Request */
 267         u8 seei;                /* 0x1A Set Enable Error Interrupt Request */
 268         u8 ceei;                /* 0x1B Clear Enable Error Interrupt Request */
 269         u8 cint;                /* 0x1C Clear Interrupt Enable Register */
 270         u8 cerr;                /* 0x1D Clear Error Register */
 271         u8 ssrt;                /* 0x1E Set START Bit Register */
 272         u8 cdne;                /* 0x1F Clear DONE Status Bit Register */
 273         u16 res3[3];            /* 0x20 - 0x25 */
 274         u16 intr;               /* 0x26 Interrupt Request Register */
 275         u16 res4[3];            /* 0x28 - 0x2D */
 276         u16 err;                /* 0x2E Error Register */
 277         u32 res5[52];           /* 0x30 - 0xFF */
 278         u8 dchpri0;             /* 0x100 Channel 0 Priority Register */
 279         u8 dchpri1;             /* 0x101 Channel 1 Priority Register */
 280         u8 dchpri2;             /* 0x102 Channel 2 Priority Register */
 281         u8 dchpri3;             /* 0x103 Channel 3 Priority Register */
 282         u8 dchpri4;             /* 0x104 Channel 4 Priority Register */
 283         u8 dchpri5;             /* 0x105 Channel 5 Priority Register */
 284         u8 dchpri6;             /* 0x106 Channel 6 Priority Register */
 285         u8 dchpri7;             /* 0x107 Channel 7 Priority Register */
 286         u8 dchpri8;             /* 0x108 Channel 8 Priority Register */
 287         u8 dchpri9;             /* 0x109 Channel 9 Priority Register */
 288         u8 dchpri10;            /* 0x110 Channel 10 Priority Register */
 289         u8 dchpri11;            /* 0x111 Channel 11 Priority Register */
 290         u8 dchpri12;            /* 0x112 Channel 12 Priority Register */
 291         u8 dchpri13;            /* 0x113 Channel 13 Priority Register */
 292         u8 dchpri14;            /* 0x114 Channel 14 Priority Register */
 293         u8 dchpri15;            /* 0x115 Channel 15 Priority Register */
 294 } edma_t;
 295
 296 /* TCD - eDMA*/
 297 typedef struct tcd_ctrl {
 298         u32 saddr;              /* 0x00 Source Address */
 299         u16 attr;               /* 0x04 Transfer Attributes */
 300         u16 soff;               /* 0x06 Signed Source Address Offset */
 301         u32 nbytes;             /* 0x08 Minor Byte Count */
 302         u32 slast;              /* 0x0C Last Source Address Adjustment */
 303         u32 daddr;              /* 0x10 Destination address */
 304         u16 citer;              /* 0x14 Current Minor Loop Link, Major Loop Count */
 305         u16 doff;               /* 0x16 Signed Destination Address Offset */
 306         u32 dlast_sga;          /* 0x18 Last Destination Address Adjustment/Scatter Gather Address */
 307         u16 biter;              /* 0x1C Beginning Minor Loop Link, Major Loop Count */
 308         u16 csr;                /* 0x1E Control and Status */
 309 } tcd_st;
 310
 311 typedef struct tcd_multiple {
 312         tcd_st tcd[16];
 313 } tcd_t;
 314
 315 /* Interrupt module registers */
 316 typedef struct int0_ctrl {
 317         /* Interrupt Controller 0 */
 318         u32 iprh0;              /* 0x00 Pending Register High */
 319         u32 iprl0;              /* 0x04 Pending Register Low */
 320         u32 imrh0;              /* 0x08 Mask Register High */
 321         u32 imrl0;              /* 0x0C Mask Register Low */
 322         u32 frch0;              /* 0x10 Force Register High */
 323         u32 frcl0;              /* 0x14 Force Register Low */
 324         u16 res1;               /* 0x18 - 0x19 */
 325         u16 icfg0;              /* 0x1A Configuration Register */
 326         u8 simr0;               /* 0x1C Set Interrupt Mask */
 327         u8 cimr0;               /* 0x1D Clear Interrupt Mask */
 328         u8 clmask0;             /* 0x1E Current Level Mask */
 329         u8 slmask;              /* 0x1F Saved Level Mask */
 330         u32 res2[8];            /* 0x20 - 0x3F */
 331         u8 icr0[64];            /* 0x40 - 0x7F Control registers */
 332         u32 res3[24];           /* 0x80 - 0xDF */
 333         u8 swiack0;             /* 0xE0 Software Interrupt Acknowledge */
 334         u8 res4[3];             /* 0xE1 - 0xE3 */
 335         u8 Lniack0_1;           /* 0xE4 Level n interrupt acknowledge resister */
 336         u8 res5[3];             /* 0xE5 - 0xE7 */
 337         u8 Lniack0_2;           /* 0xE8 Level n interrupt acknowledge resister */
 338         u8 res6[3];             /* 0xE9 - 0xEB */
 339         u8 Lniack0_3;           /* 0xEC Level n interrupt acknowledge resister */
 340         u8 res7[3];             /* 0xED - 0xEF */
 341         u8 Lniack0_4;           /* 0xF0 Level n interrupt acknowledge resister */
 342         u8 res8[3];             /* 0xF1 - 0xF3 */
 343         u8 Lniack0_5;           /* 0xF4 Level n interrupt acknowledge resister */
 344         u8 res9[3];             /* 0xF5 - 0xF7 */
 345         u8 Lniack0_6;           /* 0xF8 Level n interrupt acknowledge resister */
 346         u8 resa[3];             /* 0xF9 - 0xFB */
 347         u8 Lniack0_7;           /* 0xFC Level n interrupt acknowledge resister */
 348         u8 resb[3];             /* 0xFD - 0xFF */
 349 } int0_t;
 350
 351 typedef struct int1_ctrl {
 352         /* Interrupt Controller 1 */
 353         u32 iprh1;              /* 0x00 Pending Register High */
 354         u32 iprl1;              /* 0x04 Pending Register Low */
 355         u32 imrh1;              /* 0x08 Mask Register High */
 356         u32 imrl1;              /* 0x0C Mask Register Low */
 357         u32 frch1;              /* 0x10 Force Register High */
 358         u32 frcl1;              /* 0x14 Force Register Low */
 359         u16 res1;               /* 0x18 */
 360         u16 icfg1;              /* 0x1A Configuration Register */
 361         u8 simr1;               /* 0x1C Set Interrupt Mask */
 362         u8 cimr1;               /* 0x1D Clear Interrupt Mask */
 363         u16 res2;               /* 0x1E - 0x1F */
 364         u32 res3[8];            /* 0x20 - 0x3F */
 365         u8 icr1[64];            /* 0x40 - 0x7F */
 366         u32 res4[24];           /* 0x80 - 0xDF */
 367         u8 swiack1;             /* 0xE0 Software Interrupt Acknowledge */
 368         u8 res5[3];             /* 0xE1 - 0xE3 */
 369         u8 Lniack1_1;           /* 0xE4 Level n interrupt acknowledge resister */
 370         u8 res6[3];             /* 0xE5 - 0xE7 */
 371         u8 Lniack1_2;           /* 0xE8 Level n interrupt acknowledge resister */
 372         u8 res7[3];             /* 0xE9 - 0xEB */
 373         u8 Lniack1_3;           /* 0xEC Level n interrupt acknowledge resister */
 374         u8 res8[3];             /* 0xED - 0xEF */
 375         u8 Lniack1_4;           /* 0xF0 Level n interrupt acknowledge resister */
 376         u8 res9[3];             /* 0xF1 - 0xF3 */
 377         u8 Lniack1_5;           /* 0xF4 Level n interrupt acknowledge resister */
 378         u8 resa[3];             /* 0xF5 - 0xF7 */
 379         u8 Lniack1_6;           /* 0xF8 Level n interrupt acknowledge resister */
 380         u8 resb[3];             /* 0xF9 - 0xFB */
 381         u8 Lniack1_7;           /* 0xFC Level n interrupt acknowledge resister */
 382         u8 resc[3];             /* 0xFD - 0xFF */
 383 } int1_t;
 384
 385 typedef struct intgack_ctrl1 {
 386         /* Global IACK Registers */
 387         u8 swiack;              /* 0xE0 Global Software Interrupt Acknowledge */
 388         u8 Lniack[7];           /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
 389 } intgack_t;
 390
 391 /*I2C module registers */
 392 typedef struct i2c_ctrl {
 393         u8 adr;                 /* 0x00 address register */
 394         u8 res1[3];             /* 0x01 - 0x03 */
 395         u8 fdr;                 /* 0x04 frequency divider register */
 396         u8 res2[3];             /* 0x05 - 0x07 */
 397         u8 cr;                  /* 0x08 control register */
 398         u8 res3[3];             /* 0x09 - 0x0B */
 399         u8 sr;                  /* 0x0C status register */
 400         u8 res4[3];             /* 0x0D - 0x0F */
 401         u8 dr;                  /* 0x10 data register */
 402         u8 res5[3];             /* 0x11 - 0x13 */
 403 } i2c_t;
 404
 405 /* QSPI module registers */
 406 typedef struct qspi_ctrl {
 407         u16 qmr;                /* Mode register */
 408         u16 res1;
 409         u16 qdlyr;              /* Delay register */
 410         u16 res2;
 411         u16 qwr;                /* Wrap register */
 412         u16 res3;
 413         u16 qir;                /* Interrupt register */
 414         u16 res4;
 415         u16 qar;                /* Address register */
 416         u16 res5;
 417         u16 qdr;                /* Data register */
 418         u16 res6;
 419 } qspi_t;
 420
 421 /* PWM module registers */
 422 typedef struct pwm_ctrl {
 423         u8 en;                  /* 0x00 PWM Enable Register */
 424         u8 pol;                 /* 0x01 Polarity Register */
 425         u8 clk;                 /* 0x02 Clock Select Register */
 426         u8 prclk;               /* 0x03 Prescale Clock Select Register */
 427         u8 cae;                 /* 0x04 Center Align Enable Register */
 428         u8 ctl;                 /* 0x05 Control Register */
 429         u8 res1[2];             /* 0x06 - 0x07 */
 430         u8 scla;                /* 0x08 Scale A register */
 431         u8 sclb;                /* 0x09 Scale B register */
 432         u8 res2[2];             /* 0x0A - 0x0B */
 433         u8 cnt0;                /* 0x0C Channel 0 Counter register */
 434         u8 cnt1;                /* 0x0D Channel 1 Counter register */
 435         u8 cnt2;                /* 0x0E Channel 2 Counter register */
 436         u8 cnt3;                /* 0x0F Channel 3 Counter register */
 437         u8 cnt4;                /* 0x10 Channel 4 Counter register */
 438         u8 cnt5;                /* 0x11 Channel 5 Counter register */
 439         u8 cnt6;                /* 0x12 Channel 6 Counter register */
 440         u8 cnt7;                /* 0x13 Channel 7 Counter register */
 441         u8 per0;                /* 0x14 Channel 0 Period register */
 442         u8 per1;                /* 0x15 Channel 1 Period register */
 443         u8 per2;                /* 0x16 Channel 2 Period register */
 444         u8 per3;                /* 0x17 Channel 3 Period register */
 445         u8 per4;                /* 0x18 Channel 4 Period register */
 446         u8 per5;                /* 0x19 Channel 5 Period register */
 447         u8 per6;                /* 0x1A Channel 6 Period register */
 448         u8 per7;                /* 0x1B Channel 7 Period register */
 449         u8 dty0;                /* 0x1C Channel 0 Duty register */
 450         u8 dty1;                /* 0x1D Channel 1 Duty register */
 451         u8 dty2;                /* 0x1E Channel 2 Duty register */
 452         u8 dty3;                /* 0x1F Channel 3 Duty register */
 453         u8 dty4;                /* 0x20 Channel 4 Duty register */
 454         u8 dty5;                /* 0x21 Channel 5 Duty register */
 455         u8 dty6;                /* 0x22 Channel 6 Duty register */
 456         u8 dty7;                /* 0x23 Channel 7 Duty register */
 457         u8 sdn;                 /* 0x24 Shutdown register */
 458         u8 res3[3];             /* 0x25 - 0x27 */
 459 } pwm_t;
 460
 461 /* Edge Port module registers */
 462 typedef struct eport_ctrl {
 463         u16 par;                /* 0x00 Pin Assignment Register */
 464         u8 ddar;                /* 0x02 Data Direction Register */
 465         u8 ier;                 /* 0x03 Interrupt Enable Register */
 466         u8 dr;                  /* 0x04 Data Register */
 467         u8 pdr;                 /* 0x05 Pin Data  Register */
 468         u8 fr;                  /* 0x06 Flag_Register */
 469         u8 res1;
 470 } eport_t;
 471
 472 /* Watchdog registers */
 473 typedef struct wdog_ctrl {
 474         u16 cr;                 /* 0x00 Control register */
 475         u16 mr;                 /* 0x02 Modulus register */
 476         u16 cntr;               /* 0x04 Count register */
 477         u16 sr;                 /* 0x06 Service register */
 478 } wdog_t;
 479
 480 /*Chip configuration module registers */
 481 typedef struct ccm_ctrl {
 482         u8 rstctrl;             /* 0x00 Reset Controller register */
 483         u8 rststat;             /* 0x01 Reset Status register */
 484         u16 res1;               /* 0x02 - 0x03 */
 485         u16 ccr;                /* 0x04 Chip configuration register */
 486         u16 res2;               /* 0x06 */
 487         u16 rcon;               /* 0x08 Rreset configuration register */
 488         u16 cir;                /* 0x0A Chip identification register */
 489         u32 res3;               /* 0x0C */
 490         u16 misccr;             /* 0x10 Miscellaneous control register */
 491         u16 cdr;                /* 0x12 Clock divider register */
 492         u16 uhcsr;              /* 0x14 USB Host controller status register */
 493         u16 uocsr;              /* 0x16 USB On-the-Go Controller Status Register */
 494 } ccm_t;
 495
 496 /* GPIO port registers */
 497 typedef struct gpio_ctrl {
 498         /* Port Output Data Registers */
 499         u8 podr_fech;           /* 0x00 */
 500         u8 podr_fecl;           /* 0x01 */
 501         u8 podr_ssi;            /* 0x02 */
 502         u8 podr_busctl;         /* 0x03 */
 503         u8 podr_be;             /* 0x04 */
 504         u8 podr_cs;             /* 0x05 */
 505         u8 podr_pwm;            /* 0x06 */
 506         u8 podr_feci2c;         /* 0x07 */
 507         u8 res1;                /* 0x08 */
 508         u8 podr_uart;           /* 0x09 */
 509         u8 podr_qspi;           /* 0x0A */
 510         u8 podr_timer;          /* 0x0B */
 511         u8 res2;                /* 0x0C */
 512         u8 podr_lcddatah;       /* 0x0D */
 513         u8 podr_lcddatam;       /* 0x0E */
 514         u8 podr_lcddatal;       /* 0x0F */
 515         u8 podr_lcdctlh;        /* 0x10 */
 516         u8 podr_lcdctll;        /* 0x11 */
 517
 518         /* Port Data Direction Registers */
 519         u16 res3;               /* 0x12 - 0x13 */
 520         u8 pddr_fech;           /* 0x14 */
 521         u8 pddr_fecl;           /* 0x15 */
 522         u8 pddr_ssi;            /* 0x16 */
 523         u8 pddr_busctl;         /* 0x17 */
 524         u8 pddr_be;             /* 0x18 */
 525         u8 pddr_cs;             /* 0x19 */
 526         u8 pddr_pwm;            /* 0x1A */
 527         u8 pddr_feci2c;         /* 0x1B */
 528         u8 res4;                /* 0x1C */
 529         u8 pddr_uart;           /* 0x1D */
 530         u8 pddr_qspi;           /* 0x1E */
 531         u8 pddr_timer;          /* 0x1F */
 532         u8 res5;                /* 0x20 */
 533         u8 pddr_lcddatah;       /* 0x21 */
 534         u8 pddr_lcddatam;       /* 0x22 */
 535         u8 pddr_lcddatal;       /* 0x23 */
 536         u8 pddr_lcdctlh;        /* 0x24 */
 537         u8 pddr_lcdctll;        /* 0x25 */
 538         u16 res6;               /* 0x26 - 0x27 */
 539
 540         /* Port Data Direction Registers */
 541         u8 ppd_fech;            /* 0x28 */
 542         u8 ppd_fecl;            /* 0x29 */
 543         u8 ppd_ssi;             /* 0x2A */
 544         u8 ppd_busctl;          /* 0x2B */
 545         u8 ppd_be;              /* 0x2C */
 546         u8 ppd_cs;              /* 0x2D */
 547         u8 ppd_pwm;             /* 0x2E */
 548         u8 ppd_feci2c;          /* 0x2F */
 549         u8 res7;                /* 0x30 */
 550         u8 ppd_uart;            /* 0x31 */
 551         u8 ppd_qspi;            /* 0x32 */
 552         u8 ppd_timer;           /* 0x33 */
 553         u8 res8;                /* 0x34 */
 554         u8 ppd_lcddatah;        /* 0x35 */
 555         u8 ppd_lcddatam;        /* 0x36 */
 556         u8 ppd_lcddatal;        /* 0x37 */
 557         u8 ppd_lcdctlh;         /* 0x38 */
 558         u8 ppd_lcdctll;         /* 0x39 */
 559         u16 res9;               /* 0x3A - 0x3B */
 560
 561         /* Port Clear Output Data Registers */
 562         u8 pclrr_fech;          /* 0x3C */
 563         u8 pclrr_fecl;          /* 0x3D */
 564         u8 pclrr_ssi;           /* 0x3E */
 565         u8 pclrr_busctl;        /* 0x3F */
 566         u8 pclrr_be;            /* 0x40 */
 567         u8 pclrr_cs;            /* 0x41 */
 568         u8 pclrr_pwm;           /* 0x42 */
 569         u8 pclrr_feci2c;        /* 0x43 */
 570         u8 res10;               /* 0x44 */
 571         u8 pclrr_uart;          /* 0x45 */
 572         u8 pclrr_qspi;          /* 0x46 */
 573         u8 pclrr_timer;         /* 0x47 */
 574         u8 res11;               /* 0x48 */
 575         u8 pclrr_lcddatah;      /* 0x49 */
 576         u8 pclrr_lcddatam;      /* 0x4A */
 577         u8 pclrr_lcddatal;      /* 0x4B */
 578         u8 pclrr_lcdctlh;       /* 0x4C */
 579         u8 pclrr_lcdctll;       /* 0x4D */
 580         u16 res12;              /* 0x4E - 0x4F */
 581
 582         /* Pin Assignment Registers */
 583         u8 par_fec;             /* 0x50 */
 584         u8 par_pwm;             /* 0x51 */
 585         u8 par_busctl;          /* 0x52 */
 586         u8 par_feci2c;          /* 0x53 */
 587         u8 par_be;              /* 0x54 */
 588         u8 par_cs;              /* 0x55 */
 589         u16 par_ssi;            /* 0x56 */
 590         u16 par_uart;           /* 0x58 */
 591         u16 par_qspi;           /* 0x5A */
 592         u8 par_timer;           /* 0x5C */
 593         u8 par_lcddata;         /* 0x5D */
 594         u16 par_lcdctl;         /* 0x5E */
 595         u16 par_irq;            /* 0x60 */
 596         u16 res16;              /* 0x62 - 0x63 */
 597
 598         /* Mode Select Control Registers */
 599         u8 mscr_flexbus;        /* 0x64 */
 600         u8 mscr_sdram;          /* 0x65 */
 601         u16 res17;              /* 0x66 - 0x67 */
 602
 603         /* Drive Strength Control Registers */
 604         u8 dscr_i2c;            /* 0x68 */
 605         u8 dscr_pwm;            /* 0x69 */
 606         u8 dscr_fec;            /* 0x6A */
 607         u8 dscr_uart;           /* 0x6B */
 608         u8 dscr_qspi;           /* 0x6C */
 609         u8 dscr_timer;          /* 0x6D */
 610         u8 dscr_ssi;            /* 0x6E */
 611         u8 dscr_lcd;            /* 0x6F */
 612         u8 dscr_debug;          /* 0x70 */
 613         u8 dscr_clkrst;         /* 0x71 */
 614         u8 dscr_irq;            /* 0x72 */
 615 } gpio_t;
 616
 617 /* LCD module registers */
 618 typedef struct lcd_ctrl {
 619         u32 ssar;               /* 0x00 Screen Start Address Register */
 620         u32 sr;                 /* 0x04 LCD Size Register */
 621         u32 vpw;                /* 0x08 Virtual Page Width Register */
 622         u32 cpr;                /* 0x0C Cursor Position Register */
 623         u32 cwhb;               /* 0x10 Cursor Width Height and Blink Register */
 624         u32 ccmr;               /* 0x14 Color Cursor Mapping Register */
 625         u32 pcr;                /* 0x18 Panel Configuration Register */
 626         u32 hcr;                /* 0x1C Horizontal Configuration Register */
 627         u32 vcr;                /* 0x20 Vertical Configuration Register */
 628         u32 por;                /* 0x24 Panning Offset Register */
 629         u32 scr;                /* 0x28 Sharp Configuration Register */
 630         u32 pccr;               /* 0x2C PWM Contrast Control Register */
 631         u32 dcr;                /* 0x30 DMA Control Register */
 632         u32 rmcr;               /* 0x34 Refresh Mode Control Register */
 633         u32 icr;                /* 0x38 Refresh Mode Control Register */
 634         u32 ier;                /* 0x3C Interrupt Enable Register */
 635         u32 isr;                /* 0x40 Interrupt Status Register */
 636         u32 res[4];
 637         u32 gwsar;              /* 0x50 Graphic Window Start Address Register */
 638         u32 gwsr;               /* 0x54 Graphic Window Size Register */
 639         u32 gwvpw;              /* 0x58 Graphic Window Virtual Page Width Register */
 640         u32 gwpor;              /* 0x5C Graphic Window Panning Offset Register */
 641         u32 gwpr;               /* 0x60 Graphic Window Position Register */
 642         u32 gwcr;               /* 0x64 Graphic Window Control Register */
 643         u32 gwdcr;              /* 0x68 Graphic Window DMA Control Register */
 644 } lcd_t;
 645
 646 typedef struct lcdbg_ctrl {
 647         u32 bglut[255];
 648 } lcdbg_t;
 649
 650 typedef struct lcdgw_ctrl {
 651         u32 gwlut[255];
 652 } lcdgw_t;
 653
 654 /* USB OTG module registers */
 655 typedef struct usb_otg {
 656         u32 id;                 /* 0x000 Identification Register */
 657         u32 hwgeneral;          /* 0x004 General HW Parameters */
 658         u32 hwhost;             /* 0x008 Host HW Parameters */
 659         u32 hwdev;              /* 0x00C Device HW parameters */
 660         u32 hwtxbuf;            /* 0x010 TX Buffer HW Parameters */
 661         u32 hwrxbuf;            /* 0x014 RX Buffer HW Parameters */
 662         u32 res1[58];           /* 0x18 - 0xFF */
 663         u8 caplength;           /* 0x100 Capability Register Length */
 664         u8 res2;                /* 0x101 */
 665         u16 hciver;             /* 0x102 Host Interface Version Number */
 666         u32 hcsparams;          /* 0x104 Host Structural Parameters */
 667         u32 hccparams;          /* 0x108 Host Capability Parameters */
 668         u32 res3[5];            /* 0x10C - 0x11F */
 669         u16 dciver;             /* 0x120 Device Interface Version Number */
 670         u16 res4;               /* 0x122 */
 671         u32 dccparams;          /* 0x124 Device Capability Parameters */
 672         u32 res5[6];            /* 0x128 - 0x13F */
 673         u32 cmd;                /* 0x140 USB Command */
 674         u32 sts;                /* 0x144 USB Status */
 675         u32 intr;               /* 0x148 USB Interrupt Enable */
 676         u32 frindex;            /* 0x14C USB Frame Index */
 677         u32 res6;               /* 0x150 */
 678         u32 prd_dev;            /* 0x154 Periodic Frame List Base or Device Address */
 679         u32 aync_ep;            /* 0x158 Current Asynchronous List or Address at Endpoint List Address */
 680         u32 ttctrl;             /* 0x15C Host TT Asynchronous Buffer Control */
 681         u32 burstsize;          /* 0x160 Master Interface Data Burst Size */
 682         u32 txfill;             /* 0x164 Host Transmit FIFO Tuning Control */
 683         u32 res7[6];            /* 0x168 - 0x17F */
 684         u32 cfgflag;            /* 0x180 Configure Flag Register */
 685         u32 portsc1;            /* 0x184 Port Status/Control */
 686         u32 res8[7];            /* 0x188 - 0x1A3 */
 687         u32 otgsc;              /* 0x1A4 On The Go Status and Control */
 688         u32 mode;               /* 0x1A8 USB mode register */
 689         u32 eptsetstat;         /* 0x1AC Endpoint Setup status */
 690         u32 eptprime;           /* 0x1B0 Endpoint initialization */
 691         u32 eptflush;           /* 0x1B4 Endpoint de-initialize */
 692         u32 eptstat;            /* 0x1B8 Endpoint status */
 693         u32 eptcomplete;        /* 0x1BC Endpoint Complete */
 694         u32 eptctrl0;           /* 0x1C0 Endpoint control 0 */
 695         u32 eptctrl1;           /* 0x1C4 Endpoint control 1 */
 696         u32 eptctrl2;           /* 0x1C8 Endpoint control 2 */
 697         u32 eptctrl3;           /* 0x1CC Endpoint control 3 */
 698 } usbotg_t;
 699
 700 /* USB Host module registers */
 701 typedef struct usb_host {
 702         u32 id;                 /* 0x000 Identification Register */
 703         u32 hwgeneral;          /* 0x004 General HW Parameters */
 704         u32 hwhost;             /* 0x008 Host HW Parameters */
 705         u32 res1;               /* 0x0C */
 706         u32 hwtxbuf;            /* 0x010 TX Buffer HW Parameters */
 707         u32 hwrxbuf;            /* 0x014 RX Buffer HW Parameters */
 708         u32 res2[58];           /* 0x18 - 0xFF */
 709
 710         /* Host Controller Capability Register */
 711         u8 caplength;           /* 0x100 Capability Register Length */
 712         u8 res3;                /* 0x101 */
 713         u16 hciver;             /* 0x102 Host Interface Version Number */
 714         u32 hcsparams;          /* 0x104 Host Structural Parameters */
 715         u32 hccparams;          /* 0x108 Host Capability Parameters */
 716         u32 res4[13];           /* 0x10C - 0x13F */
 717
 718         /* Host Controller Operational Register */
 719         u32 cmd;                /* 0x140 USB Command */
 720         u32 sts;                /* 0x144 USB Status */
 721         u32 intr;               /* 0x148 USB Interrupt Enable */
 722         u32 frindex;            /* 0x14C USB Frame Index */
 723         u32 res5;               /* 0x150 (ctrl segment register in EHCI spec) */
 724         u32 prdlst;             /* 0x154 Periodic Frame List Base Address */
 725         u32 aynclst;            /* 0x158 Current Asynchronous List Address */
 726         u32 ttctrl;             /* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */
 727         u32 burstsize;          /* 0x160 Master Interface Data Burst Size (non-ehci) */
 728         u32 txfill;             /* 0x164 Host Transmit FIFO Tuning Control  (non-ehci) */
 729         u32 res6[6];            /* 0x168 - 0x17F */
 730         u32 cfgflag;            /* 0x180 Configure Flag Register */
 731         u32 portsc1;            /* 0x184 Port Status/Control */
 732         u32 res7[8];            /* 0x188 - 0x1A7 */
 733
 734         /* non-ehci registers */
 735         u32 mode;               /* 0x1A8 USB mode register */
 736         u32 eptsetstat;         /* 0x1AC Endpoint Setup status */
 737         u32 eptprime;           /* 0x1B0 Endpoint initialization */
 738         u32 eptflush;           /* 0x1B4 Endpoint de-initialize */
 739         u32 eptstat;            /* 0x1B8 Endpoint status */
 740         u32 eptcomplete;        /* 0x1BC Endpoint Complete */
 741         u32 eptctrl0;           /* 0x1C0 Endpoint control 0 */
 742         u32 eptctrl1;           /* 0x1C4 Endpoint control 1 */
 743         u32 eptctrl2;           /* 0x1C8 Endpoint control 2 */
 744         u32 eptctrl3;           /* 0x1CC Endpoint control 3 */
 745 } usbhost_t;
 746
 747 /* SDRAM controller registers */
 748 typedef struct sdram_ctrl {
 749         u32 mode;               /* 0x00 Mode/Extended Mode register */
 750         u32 ctrl;               /* 0x04 Control register */
 751         u32 cfg1;               /* 0x08 Configuration register 1 */
 752         u32 cfg2;               /* 0x0C Configuration register 2 */
 753         u32 res1[64];           /* 0x10 - 0x10F */
 754         u32 cs0;                /* 0x110 Chip Select 0 Configuration */
 755         u32 cs1;                /* 0x114 Chip Select 1 Configuration */
 756 } sdram_t;
 757
 758 /* Synchronous serial interface */
 759 typedef struct ssi_ctrl {
 760         u32 tx0;                /* 0x00 Transmit Data Register 0 */
 761         u32 tx1;                /* 0x04 Transmit Data Register 1 */
 762         u32 rx0;                /* 0x08 Receive Data Register 0 */
 763         u32 rx1;                /* 0x0C Receive Data Register 1 */
 764         u32 cr;                 /* 0x10 Control Register */
 765         u32 isr;                /* 0x14 Interrupt Status Register */
 766         u32 ier;                /* 0x18 Interrupt Enable Register */
 767         u32 tcr;                /* 0x1C Transmit Configuration Register */
 768         u32 rcr;                /* 0x20 Receive Configuration Register */
 769         u32 ccr;                /* 0x24 Clock Control Register */
 770         u32 res1;               /* 0x28 */
 771         u32 fcsr;               /* 0x2C FIFO Control/Status Register */
 772         u32 res2[2];            /* 0x30 - 0x37 */
 773         u32 acr;                /* 0x38 AC97 Control Register */
 774         u32 acadd;              /* 0x3C AC97 Command Address Register */
 775         u32 acdat;              /* 0x40 AC97 Command Data Register */
 776         u32 atag;               /* 0x44 AC97 Tag Register */
 777         u32 tmask;              /* 0x48 Transmit Time Slot Mask Register */
 778         u32 rmask;              /* 0x4C Receive Time Slot Mask Register */
 779 } ssi_t;
 780
 781 /* Clock Module registers */
 782 typedef struct pll_ctrl {
 783         u8 podr;                /* 0x00 Output Divider Register */
 784         u8 res1[3];
 785         u8 pcr;                 /* 0x04 Control Register */
 786         u8 res2[3];
 787         u8 pmdr;                /* 0x08 Modulation Divider Register */
 788         u8 res3[3];
 789         u8 pfdr;                /* 0x0C Feedback Divider Register */
 790         u8 res4[3];
 791 } pll_t;
 792
 793 #endif                          /* __IMMAP_5329__ */