1 /*This file is subject to the terms and conditions of the GNU General Public
4 * Blackfin BF533/2.6 support : LG Soft India
5 * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
6 * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
7 * shouldn't be victimized. cplbmgr.S search logic is corrected
8 * to findout the appropriate victim.
9 * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
14 #ifndef __ARCH_BFINNOMMU_CPLBTAB_H
15 #define __ARCH_BFINNOMMU_CPLBTAB_H
17 /*************************************************************************
19 *************************************************************************/
23 /* This table is configurable */
29 #define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
30 #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
31 #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
32 #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
34 /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
36 #define ANOMALY_05000158 0x200
37 #ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
38 #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
39 #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
40 #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
41 #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
42 #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
44 #else /*Write Through*/
45 #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
46 #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
47 #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
48 #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
49 #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
57 .byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
59 .byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
61 .byte4 (SDRAM_IKERNEL); /*SDRAM_Page14*/
63 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
65 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
67 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/
69 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/
71 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/
73 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/
74 #ifndef CONFIG_EZKIT /*STAMP Memory regions*/
76 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/
78 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/
80 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/
82 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/
84 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/
86 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/
88 .byte4 0xffffffff; /* end of section - termination*/
93 #ifdef CONFIG_CPLB_INFO
95 .byte4 (SDRAM_IKERNEL); /*SDRAM_Page0*/
97 .byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
100 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
102 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page3*/
104 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/
106 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/
108 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/
110 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/
111 #ifndef CONFIG_EZKIT /*STAMP Memory regions*/
113 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/
115 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/
117 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/
119 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/
121 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/
123 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/
125 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page14*/
127 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page15*/
130 .byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/
132 .byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/
134 .byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/
135 .byte4 0x20300000; /*Fix for Network*/
136 .byte4 (SDRAM_EBIU); /*Async Memory bank 3*/
140 .byte4 (SDRAM_IGENERIC);
142 .byte4 (SDRAM_IGENERIC);
144 .byte4 (SDRAM_IGENERIC);
146 .byte4 (SDRAM_IGENERIC);
148 .byte4 (SDRAM_IGENERIC);
150 .byte4 (SDRAM_IGENERIC);
152 .byte4 (SDRAM_IGENERIC);
154 .byte4 (SDRAM_IGENERIC);
156 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page25*/
158 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page26*/
160 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page27*/
162 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page28*/
164 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page29*/
166 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page30*/
168 .byte4 (SDRAM_IGENERIC); /*SDRAM_Page31*/
169 #ifdef CONFIG_CPLB_INFO
171 .byte4 (SDRAM_IKERNEL); /*SDRAM_Page32*/
174 .byte4 0xffffffff; /* end of section - termination*/
176 /*********************************************************************
178 ********************************************************************/
183 .byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
185 .byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
187 .byte4 (SDRAM_DKERNEL); /*SDRAM_Page15*/
189 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/
191 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/
193 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/
195 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/
197 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/
199 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/
202 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/
204 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/
206 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/
208 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/
210 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/
212 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/
214 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/
216 .byte4 0xffffffff; /*end of section - termination*/
218 /**********************************************************************
219 * PAGE DESCRIPTOR TABLE
221 **********************************************************************/
223 /* Till here we are discussing about the static memory management model.
224 * However, the operating envoronments commonly define more CPLB
225 * descriptors to cover the entire addressable memory than will fit into
226 * the available on-chip 16 CPLB MMRs. When this happens, the below table
227 * will be used which will hold all the potentially required CPLB descriptors
229 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
233 #ifdef CONFIG_CPLB_INFO
235 .byte4 (SDRAM_DKERNEL); /*SDRAM_Page0*/
237 .byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
240 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/
242 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/
244 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/
246 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/
248 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/
250 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/
254 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/
256 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/
258 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/
260 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/
262 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/
264 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/
266 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/
268 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page15*/
271 .byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/
273 .byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/
275 .byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/
276 .byte4 0x20300000; /*Fix for Network*/
277 .byte4 (SDRAM_EBIU); /*Async Memory bank 3*/
281 .byte4 (SDRAM_DGENERIC);
283 .byte4 (SDRAM_DGENERIC);
285 .byte4 (SDRAM_DGENERIC);
287 .byte4 (SDRAM_DGENERIC);
289 .byte4 (SDRAM_DGENERIC);
291 .byte4 (SDRAM_DGENERIC);
293 .byte4 (SDRAM_DGENERIC);
295 .byte4 (SDRAM_DGENERIC);
297 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page25*/
299 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page26*/
301 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page27*/
303 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page28*/
305 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page29*/
307 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page30*/
309 .byte4 (SDRAM_DGENERIC); /*SDRAM_Page31*/
310 #ifdef CONFIG_CPLB_INFO
312 .byte4 (SDRAM_DKERNEL); /*SDRAM_Page32*/
341 .byte4 0xffffffff; /*end of section - termination*/
343 #ifdef CONFIG_CPLB_INFO
344 .global ipdt_swapcount_table; /* swapin count first, then swapout count*/
345 ipdt_swapcount_table:
355 .byte4 0x00000000; /* 10 */
365 .byte4 0x00000000; /* 20 */
375 .byte4 0x00000000; /* 30 */
385 .byte4 0x00000000; /* 40 */
395 .byte4 0x00000000; /* 50 */
405 .byte4 0x00000000; /* 60 */
415 .byte4 0x00000000; /* 70 */
425 .byte4 0x00000000; /* 80 */
435 .byte4 0x00000000; /* 90 */
445 .byte4 0x00000000; /* 100 */
447 .global dpdt_swapcount_table; /* swapin count first, then swapout count*/
448 dpdt_swapcount_table:
458 .byte4 0x00000000; /* 10 */
468 .byte4 0x00000000; /* 20 */
478 .byte4 0x00000000; /* 30 */
488 .byte4 0x00000000; /* 40 */
498 .byte4 0x00000000; /* 50 */
508 .byte4 0x00000000; /* 60 */
518 .byte4 0x00000000; /* 70 */
528 .byte4 0x00000000; /* 80 */
538 .byte4 0x00000000; /* 80 */
548 .byte4 0x00000000; /* 100 */
558 .byte4 0x00000000; /* 110 */
568 .byte4 0x00000000; /* 120 */
572 #endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/