1 /************************************************************************
5 * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
7 ************************************************************************/
9 /* Defines necessary for cplb initialisation routines. */
13 #define CONFIG_BLKFIN_WT
15 #define CPLB_ENABLE_ICACHE_P 0
16 #define CPLB_ENABLE_DCACHE_P 1
17 #define CPLB_ENABLE_DCACHE2_P 2
18 #define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
19 #define CPLB_ENABLE_ICPLBS_P 4
20 #define CPLB_ENABLE_DCPLBS_P 5
22 #define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
23 #define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
24 #define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
25 #define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
26 #define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
27 #define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
28 #define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
29 CPLB_ENABLE_ICPLBS | \
32 #define CPLB_RELOADED 0x0000
33 #define CPLB_NO_UNLOCKED 0x0001
34 #define CPLB_NO_ADDR_MATCH 0x0002
35 #define CPLB_PROT_VIOL 0x0003
37 #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
38 #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
40 #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
42 #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
43 #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
44 #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
45 #define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
46 #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
47 #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
51 #define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
52 #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
53 #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
54 #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
56 /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
58 #define ANOMALY_05000158 0x200
60 #ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
61 #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
62 #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
63 #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
64 #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
65 #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
67 #else /*Write Through */
68 #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
69 #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
70 #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
71 #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
72 #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
75 #if defined(CONFIG_BF561)
76 #define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM +L1 + ASYNC_Memory */
78 #define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 3) /* SDRAM + L1 + ASYNC_Memory */