2 * Copyright (C) 2004-2005 Analog Devices Inc., All Rights Reserved.
4 ***********************************************************************************
6 * This include file contains a list of macro "defines" to enable the programmer
7 * to use symbolic names for register-access and bit-manipulation.
9 * ----------------------------
11 * date: 2004/03/01 21:23:01; author: joeb
14 * ----------------------------
16 * date: 2004/05/15 16:30:00; author: joeb
17 * comments: removed I2C/IIC references, changed GPIO sections
19 * ----------------------------
21 * date: 2004/06/08 12:25:00; author: joeb
22 * comments: fixed mis-mapped TIMER registers, changed TWI register names, fixed
23 * FLAG references in GPIO register names
25 * ----------------------------
27 * date: 2004/06/09 2:25:00; author: joeb
28 * comments: fixed bit-defines for EMAC section, renamed EMAC count registers,
29 * combined 2 Timer status registers into one
31 * ----------------------------
33 * date: 2004/08/10 10:25:00; author: joeb
34 * comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers
36 * ----------------------------
38 * date: 2004/08/17 16:25:00; author: joeb
39 * comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK
41 * ----------------------------
43 * date: 2004/08/18 13:21:00; author: joeb
44 * comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes
46 * ----------------------------
48 * date: 2004/08/20 10:24:00; author: joeb
49 * comments: Renamed External DMA to Handshake MDMA
51 * ----------------------------
53 * date: 2004/08/23 13:42:00; author: joeb
54 * comments: Renamed Handshake DMA Register Set
56 * ----------------------------
58 * date: 2004/09/07 11:21:00; author: joeb
59 * comments: Fixed EMAC TX/RX DMA Priority (DMA and SIC Bit Names)
61 * ----------------------------
63 * date: 2004/09/28 15:14:00; author: joeb
64 * comments: Fixed CAN Mailbox Area
66 * ----------------------------
68 * date: 2004/10/27 13:18:00; author: joeb
69 * comments: Added IEEE EMAC Register Support
71 * ----------------------------
73 * date: 2004/10/28 15:40:00; author: joeb
74 * comments: Shortened EMAC Count Register Names
76 * ----------------------------
78 * date: 2004/11/09 10:45:00; author: joeb
79 * comments: Fixed WDSIZE macros
81 * ----------------------------
83 * date: 2004/11/18 07:45:00; author: joeb
84 * comments: Fixed TIMER_STATUS register, added EMAC macros
86 * ----------------------------
88 * date: 2004/12/13 11:05:00; author: joeb
89 * comments: Removed HI/LO macros (now Assembler mnemonics)
90 * Renamed enable bit for HMDMA from EN to HMDMAEN
92 * ----------------------------
94 * date: 2004/12/17 14:25:00; author: joeb
95 * comments: Replaced C++ Single-Line Comments w/C-standard Comments
96 * Changed EMAC EQ1024 TX/RX References to GE1024
98 * ----------------------------
100 * date: 2005/01/05 10:50:00; author: joeb
101 * comments: Added CAN Macros To Index Mailbox Area and Acceptance Masks
102 * Added mask values for field deposit protection
104 * ----------------------------
106 * date: 2005/01/10 10:30:00; author: joeb
107 * comments: Made all Macro argument syntax compliant to MISRA-C 2004 rule 19.10.
109 * ----------------------------
111 * date: 2005/01/27 14:25:15; author: joeb
112 * comments: Moved MMRs common to BF534 to BF534 header.
117 /* Include all Core registers and bit definitions */
118 #include <asm/arch-common/def_LPBlackfin.h>
120 /* Include all MMR and bit defines common to BF534 */
121 #include <asm/arch-bf537/defBF534.h>
124 * Define EMAC Section Unique to BF536/BF537
127 /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
128 #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
129 #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
130 #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
131 #define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
132 #define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
133 #define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
134 #define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
135 #define EMAC_FLC 0xFFC0301C /* Flow Control Register */
136 #define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
137 #define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
138 #define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
139 #define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
140 #define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
141 #define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
142 #define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
143 #define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
144 #define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
145 #define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
146 #define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
148 #define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
149 #define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
150 #define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
151 #define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
152 #define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
153 #define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
154 #define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
155 #define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
157 #define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
158 #define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
159 #define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
160 #define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
161 #define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
163 #define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
164 #define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
165 #define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
166 #define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
167 #define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
168 #define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
169 #define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
170 #define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
171 #define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
172 #define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
173 #define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
174 #define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
175 #define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
176 #define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
177 #define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
178 #define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
179 #define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
180 #define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
181 #define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
182 #define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
183 #define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
184 #define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
185 #define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
186 #define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
188 #define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
189 #define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
190 #define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
191 #define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
192 #define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
193 #define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
194 #define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
195 #define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
196 #define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
197 #define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
198 #define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
199 #define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
200 #define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
201 #define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
202 #define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
203 #define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
204 #define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
205 #define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
206 #define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
207 #define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
208 #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
209 #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
210 #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
212 /* Listing for IEEE-Supported Count Registers */
213 #define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
214 #define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
215 #define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
216 #define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
217 #define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
218 #define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
219 #define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
220 #define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
221 #define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
222 #define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
223 #define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
224 #define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
225 #define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
226 #define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
227 #define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
228 #define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
229 #define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
230 #define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
231 #define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
232 #define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
233 #define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
234 #define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
235 #define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
236 #define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
238 #define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
239 #define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
240 #define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
241 #define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
242 #define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
243 #define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
244 #define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
245 #define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
246 #define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
247 #define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
248 #define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
249 #define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
250 #define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
251 #define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
252 #define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
253 #define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
254 #define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
255 #define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
256 #define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
257 #define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
258 #define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
259 #define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
260 #define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
263 * System MMR Register Bits And Macros
265 * Disclaimer: All macros are intended to make C and Assembly code more readable.
266 * Use these macros carefully, as any that do left shifts for field
267 * depositing will result in the lower order bits being destroyed. Any
268 * macro that shifts left to properly position the bit-field should be
269 * used as part of an OR to initialize a register and NOT as a dynamic
270 * modifier UNLESS the lower order bits are saved and ORed back in when
274 * ETHERNET 10/100 CONTROLLER MASKS
276 /* EMAC_OPMODE Masks */
277 #define RE 0x00000001 /* Receiver Enable */
278 #define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
279 #define HU 0x00000010 /* Hash Filter Unicast Address */
280 #define HM 0x00000020 /* Hash Filter Multicast Address */
281 #define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
282 #define PR 0x00000080 /* Promiscuous Mode Enable */
283 #define IFE 0x00000100 /* Inverse Filtering Enable */
284 #define DBF 0x00000200 /* Disable Broadcast Frame Reception */
285 #define PBF 0x00000400 /* Pass Bad Frames Enable */
286 #define PSF 0x00000800 /* Pass Short Frames Enable */
287 #define RAF 0x00001000 /* Receive-All Mode */
288 #define TE 0x00010000 /* Transmitter Enable */
289 #define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
290 #define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
291 #define DC 0x00080000 /* Deferral Check */
292 #define BOLMT 0x00300000 /* Back-Off Limit */
293 #define BOLMT_10 0x00000000 /* 10-bit range */
294 #define BOLMT_8 0x00100000 /* 8-bit range */
295 #define BOLMT_4 0x00200000 /* 4-bit range */
296 #define BOLMT_1 0x00300000 /* 1-bit range */
297 #define DRTY 0x00400000 /* Disable TX Retry On Collision */
298 #define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
299 #define RMII 0x01000000 /* RMII/MII* Mode */
300 #define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
301 #define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
302 #define LB 0x08000000 /* Internal Loopback Enable */
303 #define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
305 /* EMAC_STAADD Masks */
306 #define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
307 #define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
308 #define STADISPRE 0x00000004 /* Disable Preamble Generation */
309 #define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
310 #define REGAD 0x000007C0 /* STA Register Address */
311 #define PHYAD 0x0000F800 /* PHY Device Address */
313 #define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
314 #define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
316 /* EMAC_STADAT Mask */
317 #define STADATA 0x0000FFFF /* Station Management Data */
320 #define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
321 #define FLCE 0x00000002 /* Flow Control Enable */
322 #define PCF 0x00000004 /* Pass Control Frames */
323 #define BKPRSEN 0x00000008 /* Enable Backpressure */
324 #define FLCPAUSE 0xFFFF0000 /* Pause Time */
326 #define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
328 /* EMAC_WKUP_CTL Masks */
329 #define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
330 #define MPKE 0x00000002 /* Magic Packet Enable */
331 #define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
332 #define GUWKE 0x00000008 /* Global Unicast Wake Enable */
333 #define MPKS 0x00000020 /* Magic Packet Received Status */
334 #define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
336 /* EMAC_WKUP_FFCMD Masks */
337 #define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
338 #define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
339 #define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
340 #define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
341 #define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
342 #define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
343 #define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
344 #define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
346 /* EMAC_WKUP_FFOFF Masks */
347 #define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
348 #define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
349 #define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
350 #define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
352 #define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
353 #define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
354 #define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
355 #define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
356 /* Set ALL Offsets */
357 #define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
359 /* EMAC_WKUP_FFCRC0 Masks */
360 #define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
361 #define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
363 #define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 0 Target CRC */
364 #define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 1 Target CRC */
366 /* EMAC_WKUP_FFCRC1 Masks */
367 #define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
368 #define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
370 #define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 2 Target CRC */
371 #define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 3 Target CRC */
373 /* EMAC_SYSCTL Masks */
374 #define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
375 #define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
376 #define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
377 #define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
379 #define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
381 /* EMAC_SYSTAT Masks */
382 #define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
383 #define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
384 #define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
385 #define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
386 #define WAKEDET 0x00000010 /* Wake-Up Detected Status */
387 #define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
388 #define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
389 #define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
391 /* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
392 #define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
393 #define RX_COMP 0x00001000 /* RX Frame Complete */
394 #define RX_OK 0x00002000 /* RX Frame Received With No Errors */
395 #define RX_LONG 0x00004000 /* RX Frame Too Long Error */
396 #define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
397 #define RX_CRC 0x00010000 /* RX Frame CRC Error */
398 #define RX_LEN 0x00020000 /* RX Frame Length Error */
399 #define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
400 #define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
401 #define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
402 #define RX_PHY 0x00200000 /* RX Frame PHY Error */
403 #define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
404 #define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
405 #define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
406 #define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
407 #define RX_CTL 0x04000000 /* RX Control Frame Indicator */
408 #define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
409 #define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
410 #define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
411 #define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
412 #define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
414 /* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
415 #define TX_COMP 0x00000001 /* TX Frame Complete */
416 #define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
417 #define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
418 #define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
419 #define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
420 #define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
421 #define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
422 #define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
423 #define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
424 #define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
425 #define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
426 #define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
427 #define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
428 #define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
429 #define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
431 /* EMAC_MMC_CTL Masks */
432 #define RSTC 0x00000001 /* Reset All Counters */
433 #define CROLL 0x00000002 /* Counter Roll-Over Enable */
434 #define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
435 #define MMCE 0x00000008 /* Enable MMC Counter Operation */
437 /* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
438 #define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
439 #define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
440 #define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
441 #define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
442 #define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
443 #define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
444 #define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
445 #define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
446 #define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
447 #define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
448 #define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
449 #define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
450 #define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
451 #define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
452 #define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
453 #define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
454 #define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
455 #define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
456 #define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
457 #define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
458 #define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
459 #define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
460 #define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
461 #define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
463 /* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
464 #define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
465 #define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
466 #define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
467 #define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
468 #define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
469 #define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
470 #define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
471 #define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
472 #define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
473 #define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
474 #define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
475 #define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
476 #define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
477 #define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
478 #define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
479 #define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
480 #define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
481 #define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
482 #define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
483 #define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
484 #define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
485 #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
486 #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
488 #endif /* _DEF_BF537_H */