3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef __ASM_ARCH_MX31_REGS_H
25 #define __ASM_ARCH_MX31_REGS_H
27 #define __REG(x) (*((volatile u32 *)(x)))
28 #define __REG16(x) (*((volatile u16 *)(x)))
29 #define __REG8(x) (*((volatile u8 *)(x)))
31 #define CCM_BASE 0x53f80000
32 #define CCM_CCMR (CCM_BASE + 0x00)
33 #define CCM_PDR0 (CCM_BASE + 0x04)
34 #define CCM_PDR1 (CCM_BASE + 0x08)
35 #define CCM_RCSR (CCM_BASE + 0x0c)
36 #define CCM_MPCTL (CCM_BASE + 0x10)
37 #define CCM_UPCTL (CCM_BASE + 0x14)
38 #define CCM_SPCTL (CCM_BASE + 0x18)
39 #define CCM_COSR (CCM_BASE + 0x1C)
40 #define CCM_CGR0 (CCM_BASE + 0x20)
41 #define CCM_CGR1 (CCM_BASE + 0x24)
42 #define CCM_CGR2 (CCM_BASE + 0x28)
44 #define CCMR_MDS (1 << 7)
45 #define CCMR_SBYCS (1 << 4)
46 #define CCMR_MPE (1 << 3)
47 #define CCMR_PRCS_MASK (3 << 1)
48 #define CCMR_FPM (1 << 1)
49 #define CCMR_CKIH (2 << 1)
51 #define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
52 #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
53 #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
54 #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
55 #define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
56 #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
57 #define PDR0_MCU_PODF(x) ((x) & 0x7)
59 #define PLL_PD(x) (((x) & 0xf) << 26)
60 #define PLL_MFD(x) (((x) & 0x3ff) << 16)
61 #define PLL_MFI(x) (((x) & 0xf) << 10)
62 #define PLL_MFN(x) (((x) & 0x3ff) << 0)
64 #define WEIM_ESDCTL0 0xB8001000
65 #define WEIM_ESDCFG0 0xB8001004
66 #define WEIM_ESDCTL1 0xB8001008
67 #define WEIM_ESDCFG1 0xB800100C
68 #define WEIM_ESDMISC 0xB8001010
70 #define ESDCTL_SDE (1 << 31)
71 #define ESDCTL_CMD_RW (0 << 28)
72 #define ESDCTL_CMD_PRECHARGE (1 << 28)
73 #define ESDCTL_CMD_AUTOREFRESH (2 << 28)
74 #define ESDCTL_CMD_LOADMODEREG (3 << 28)
75 #define ESDCTL_CMD_MANUALREFRESH (4 << 28)
76 #define ESDCTL_ROW_13 (2 << 24)
77 #define ESDCTL_ROW(x) ((x) << 24)
78 #define ESDCTL_COL_9 (1 << 20)
79 #define ESDCTL_COL(x) ((x) << 20)
80 #define ESDCTL_DSIZ(x) ((x) << 16)
81 #define ESDCTL_SREFR(x) ((x) << 13)
82 #define ESDCTL_PWDT(x) ((x) << 10)
83 #define ESDCTL_FP(x) ((x) << 8)
84 #define ESDCTL_BL(x) ((x) << 7)
85 #define ESDCTL_PRCT(x) ((x) << 0)
87 #define WEIM_BASE 0xb8002000
88 #define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
89 #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
90 #define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
92 #define IOMUXC_BASE 0x43FAC000
93 #define IOMUXC_GPR (IOMUXC_BASE + 0x8)
94 #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
95 #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
97 #define IPU_BASE 0x53fc0000
98 #define IPU_CONF IPU_BASE
100 #define IPU_CONF_PXL_ENDIAN (1<<8)
101 #define IPU_CONF_DU_EN (1<<7)
102 #define IPU_CONF_DI_EN (1<<6)
103 #define IPU_CONF_ADC_EN (1<<5)
104 #define IPU_CONF_SDC_EN (1<<4)
105 #define IPU_CONF_PF_EN (1<<3)
106 #define IPU_CONF_ROT_EN (1<<2)
107 #define IPU_CONF_IC_EN (1<<1)
108 #define IPU_CONF_SCI_EN (1<<0)
110 #define ARM_PPMRR 0x40000015
112 #define WDOG_BASE 0x53FDC000
117 #define GPIO1_BASE 0x53FCC000
118 #define GPIO2_BASE 0x53FD0000
119 #define GPIO3_BASE 0x53FA4000
120 #define GPIO_DR 0x00000000 /* data register */
121 #define GPIO_GDIR 0x00000004 /* direction register */
122 #define GPIO_PSR 0x00000008 /* pad status register */
125 * Signal Multiplexing (IOMUX)
128 /* bits in the SW_MUX_CTL registers */
129 #define MUX_CTL_OUT_GPIO_DR (0 << 4)
130 #define MUX_CTL_OUT_FUNC (1 << 4)
131 #define MUX_CTL_OUT_ALT1 (2 << 4)
132 #define MUX_CTL_OUT_ALT2 (3 << 4)
133 #define MUX_CTL_OUT_ALT3 (4 << 4)
134 #define MUX_CTL_OUT_ALT4 (5 << 4)
135 #define MUX_CTL_OUT_ALT5 (6 << 4)
136 #define MUX_CTL_OUT_ALT6 (7 << 4)
137 #define MUX_CTL_IN_NONE (0 << 0)
138 #define MUX_CTL_IN_GPIO (1 << 0)
139 #define MUX_CTL_IN_FUNC (2 << 0)
140 #define MUX_CTL_IN_ALT1 (4 << 0)
141 #define MUX_CTL_IN_ALT2 (8 << 0)
143 #define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
144 #define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
145 #define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
146 #define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
148 /* Register offsets based on IOMUXC_BASE */
150 #define MUX_CTL_RTS1 0x7c
151 #define MUX_CTL_CTS1 0x7d
152 #define MUX_CTL_DTR_DCE1 0x7e
153 #define MUX_CTL_DSR_DCE1 0x7f
154 #define MUX_CTL_CSPI2_SCLK 0x80
155 #define MUX_CTL_CSPI2_SPI_RDY 0x81
156 #define MUX_CTL_RXD1 0x82
157 #define MUX_CTL_TXD1 0x83
158 #define MUX_CTL_CSPI2_MISO 0x84
159 #define MUX_CTL_CSPI2_SS0 0x85
160 #define MUX_CTL_CSPI2_SS1 0x86
161 #define MUX_CTL_CSPI2_SS2 0x87
162 #define MUX_CTL_CSPI1_SS2 0x88
163 #define MUX_CTL_CSPI1_SCLK 0x89
164 #define MUX_CTL_CSPI1_SPI_RDY 0x8a
165 #define MUX_CTL_CSPI2_MOSI 0x8b
166 #define MUX_CTL_CSPI1_MOSI 0x8c
167 #define MUX_CTL_CSPI1_MISO 0x8d
168 #define MUX_CTL_CSPI1_SS0 0x8e
169 #define MUX_CTL_CSPI1_SS1 0x8f
172 * Helper macros for the MUX_[contact name]__[pin function] macros
174 #define IOMUX_MODE_POS 9
175 #define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
178 * These macros can be used in mx31_gpio_mux() and have the form
179 * MUX_[contact name]__[pin function]
181 #define MUX_RXD1__UART1_RXD_MUX IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
182 #define MUX_TXD1__UART1_TXD_MUX IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
183 #define MUX_RTS1__UART1_RTS_B IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
184 #define MUX_CTS1__UART1_CTS_B IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
186 #define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
187 #define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
188 #define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
189 #define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
190 #define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
191 #define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
192 IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
193 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
195 #define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
196 #define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
197 #define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
198 #define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
199 #define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
200 #define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
201 IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
202 #define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
204 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
205 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
207 /* PAD control registers for SDR/DDR */
208 #define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
209 #define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)
210 #define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)
211 #define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)
212 #define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)
213 #define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)
214 #define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)
215 #define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288)
216 #define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C)
217 #define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290)
218 #define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294)
219 #define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298)
220 #define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C)
221 #define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0)
222 #define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4)
223 #define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8)
224 #define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC)
225 #define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0)
226 #define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4)
227 #define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8)
228 #define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC)
229 #define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0)
230 #define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4)
231 #define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8)
232 #define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC)
233 #define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0)
234 #define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4)
235 #define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8)
236 #define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC)
239 * Memory regions and CS
241 #define IPU_MEM_BASE 0x70000000
242 #define CSD0_BASE 0x80000000
243 #define CSD1_BASE 0x90000000
244 #define CS0_BASE 0xA0000000
245 #define CS1_BASE 0xA8000000
246 #define CS2_BASE 0xB0000000
247 #define CS3_BASE 0xB2000000
248 #define CS4_BASE 0xB4000000
249 #define CS4_PSRAM_BASE 0xB5000000
250 #define CS5_BASE 0xB6000000
251 #define PCMCIA_MEM_BASE 0xC0000000
256 #define NFC_BASE_ADDR 0xB8000000
258 #endif /* __ASM_ARCH_MX31_REGS_H */