2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * -------------------------------------------------------------------------
8 * linux/include/asm-arm/arch-davinci/hardware.h
10 * Copyright (C) 2006 Texas Instruments.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 #ifndef __ASM_ARCH_HARDWARE_H
34 #define __ASM_ARCH_HARDWARE_H
37 #include <asm/sizes.h>
39 #define REG(addr) (*(volatile unsigned int *)(addr))
40 #define REG_P(addr) ((volatile unsigned int *)(addr))
42 typedef volatile unsigned int dv_reg;
43 typedef volatile unsigned int * dv_reg_p;
46 * Base register addresses
48 * NOTE: some of these DM6446-specific addresses DO NOT WORK
49 * on other DaVinci chips. Double check them before you try
50 * using the addresses ... or PSC module identifiers, etc.
52 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
53 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
54 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
55 #define DAVINCI_UART0_BASE (0x01c20000)
56 #define DAVINCI_UART1_BASE (0x01c20400)
57 #define DAVINCI_I2C_BASE (0x01c21000)
58 #define DAVINCI_TIMER0_BASE (0x01c21400)
59 #define DAVINCI_TIMER1_BASE (0x01c21800)
60 #define DAVINCI_WDOG_BASE (0x01c21c00)
61 #define DAVINCI_PWM0_BASE (0x01c22000)
62 #define DAVINCI_PWM1_BASE (0x01c22400)
63 #define DAVINCI_PWM2_BASE (0x01c22800)
64 #define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
65 #define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
66 #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
67 #define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
68 #define DAVINCI_ARM_INTC_BASE (0x01c48000)
69 #define DAVINCI_USB_OTG_BASE (0x01c64000)
70 #define DAVINCI_CFC_ATA_BASE (0x01c66000)
71 #define DAVINCI_SPI_BASE (0x01c66800)
72 #define DAVINCI_GPIO_BASE (0x01c67000)
73 #define DAVINCI_VPSS_REGS_BASE (0x01c70000)
74 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
75 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
76 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
77 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
79 #ifdef CONFIG_SOC_DM644X
80 #define DAVINCI_UART2_BASE 0x01c20800
81 #define DAVINCI_UHPI_BASE 0x01c67800
82 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
83 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
84 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
85 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
86 #define DAVINCI_IMCOP_BASE 0x01cc0000
87 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
88 #define DAVINCI_VLYNQ_BASE 0x01e01000
89 #define DAVINCI_ASP_BASE 0x01e02000
90 #define DAVINCI_MMC_SD_BASE 0x01e10000
91 #define DAVINCI_MS_BASE 0x01e20000
92 #define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
94 #elif defined(CONFIG_SOC_DM355)
95 #define DAVINCI_MMC_SD1_BASE 0x01e00000
96 #define DAVINCI_ASP0_BASE 0x01e02000
97 #define DAVINCI_ASP1_BASE 0x01e04000
98 #define DAVINCI_UART2_BASE 0x01e06000
99 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
100 #define DAVINCI_MMC_SD0_BASE 0x01e11000
104 /* Power and Sleep Controller (PSC) Domains */
105 #define DAVINCI_GPSC_ARMDOMAIN 0
106 #define DAVINCI_GPSC_DSPDOMAIN 1
108 #define DAVINCI_LPSC_VPSSMSTR 0
109 #define DAVINCI_LPSC_VPSSSLV 1
110 #define DAVINCI_LPSC_TPCC 2
111 #define DAVINCI_LPSC_TPTC0 3
112 #define DAVINCI_LPSC_TPTC1 4
113 #define DAVINCI_LPSC_EMAC 5
114 #define DAVINCI_LPSC_EMAC_WRAPPER 6
115 #define DAVINCI_LPSC_MDIO 7
116 #define DAVINCI_LPSC_IEEE1394 8
117 #define DAVINCI_LPSC_USB 9
118 #define DAVINCI_LPSC_ATA 10
119 #define DAVINCI_LPSC_VLYNQ 11
120 #define DAVINCI_LPSC_UHPI 12
121 #define DAVINCI_LPSC_DDR_EMIF 13
122 #define DAVINCI_LPSC_AEMIF 14
123 #define DAVINCI_LPSC_MMC_SD 15
124 #define DAVINCI_LPSC_MEMSTICK 16
125 #define DAVINCI_LPSC_McBSP 17
126 #define DAVINCI_LPSC_I2C 18
127 #define DAVINCI_LPSC_UART0 19
128 #define DAVINCI_LPSC_UART1 20
129 #define DAVINCI_LPSC_UART2 21
130 #define DAVINCI_LPSC_SPI 22
131 #define DAVINCI_LPSC_PWM0 23
132 #define DAVINCI_LPSC_PWM1 24
133 #define DAVINCI_LPSC_PWM2 25
134 #define DAVINCI_LPSC_GPIO 26
135 #define DAVINCI_LPSC_TIMER0 27
136 #define DAVINCI_LPSC_TIMER1 28
137 #define DAVINCI_LPSC_TIMER2 29
138 #define DAVINCI_LPSC_SYSTEM_SUBSYS 30
139 #define DAVINCI_LPSC_ARM 31
140 #define DAVINCI_LPSC_SCR2 32
141 #define DAVINCI_LPSC_SCR3 33
142 #define DAVINCI_LPSC_SCR4 34
143 #define DAVINCI_LPSC_CROSSBAR 35
144 #define DAVINCI_LPSC_CFG27 36
145 #define DAVINCI_LPSC_CFG3 37
146 #define DAVINCI_LPSC_CFG5 38
147 #define DAVINCI_LPSC_GEM 39
148 #define DAVINCI_LPSC_IMCOP 40
150 void lpsc_on(unsigned int id);
153 void davinci_enable_uart0(void);
154 void davinci_enable_emac(void);
155 void davinci_enable_i2c(void);
156 void davinci_errata_workarounds(void);
158 /* Some PSC defines */
159 #define PSC_CHP_SHRTSW (0x01c40038)
160 #define PSC_GBLCTL (0x01c41010)
161 #define PSC_EPCPR (0x01c41070)
162 #define PSC_EPCCR (0x01c41078)
163 #define PSC_PTCMD (0x01c41120)
164 #define PSC_PTSTAT (0x01c41128)
165 #define PSC_PDSTAT (0x01c41200)
166 #define PSC_PDSTAT1 (0x01c41204)
167 #define PSC_PDCTL (0x01c41300)
168 #define PSC_PDCTL1 (0x01c41304)
170 #define PSC_MDCTL_BASE (0x01c41a00)
171 #define PSC_MDSTAT_BASE (0x01c41800)
173 #define VDD3P3V_PWDN (0x01c40048)
174 #define UART0_PWREMU_MGMT (0x01c20030)
176 #define PSC_SILVER_BULLET (0x01c41a20)
178 /* Some PLL defines */
179 #define PLL1_PLLM (0x01c40910)
180 #define PLL2_PLLM (0x01c40d10)
181 #define PLL2_DIV2 (0x01c40d1c)
184 #define VBPR (0x20000020)
186 /* NOTE: system control modules are *highly* chip-specific, both
187 * as to register content (e.g. for muxing) and which registers exist.
189 #define PINMUX0 0x01c40000
190 #define PINMUX1 0x01c40004
191 #define PINMUX2 0x01c40008
192 #define PINMUX3 0x01c4000c
193 #define PINMUX4 0x01c40010
195 #endif /* __ASM_ARCH_HARDWARE_H */