1 /* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
2 /*----------------------------------------------------------------------------+
4 | This source code has been made available to you by IBM on an AS-IS
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19 | COPYRIGHT I B M CORPORATION 1999
20 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
21 +----------------------------------------------------------------------------*/
22 /*----------------------------------------------------------------------------+
26 | Function: Header file for the MAL (MADMAL) macro on the 405GP.
32 | Date Description of Change BY
33 | --------- --------------------- ---
34 | 29-Apr-99 Created MKW
36 +----------------------------------------------------------------------------*/
37 /*----------------------------------------------------------------------------+
38 | 17-Nov-03 Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
39 | Added register bit definitions to support multiple channels
40 +----------------------------------------------------------------------------*/
43 /* MADMAL transmit and receive status/control bits */
44 /* for COMMAC bits, refer to the COMMAC header file */
46 #define MAL_TX_CTRL_READY 0x8000
47 #define MAL_TX_CTRL_WRAP 0x4000
48 #define MAL_TX_CTRL_CM 0x2000
49 #define MAL_TX_CTRL_LAST 0x1000
50 #define MAL_TX_CTRL_INTR 0x0400
52 #define MAL_RX_CTRL_EMPTY 0x8000
53 #define MAL_RX_CTRL_WRAP 0x4000
54 #define MAL_RX_CTRL_CM 0x2000
55 #define MAL_RX_CTRL_LAST 0x1000
56 #define MAL_RX_CTRL_FIRST 0x0800
57 #define MAL_RX_CTRL_INTR 0x0400
59 /* Configuration Reg */
60 #define MAL_CR_MMSR 0x80000000
61 #define MAL_CR_PLBP_1 0x00400000 /* lowsest is 00 */
62 #define MAL_CR_PLBP_2 0x00800000
63 #define MAL_CR_PLBP_3 0x00C00000 /* highest */
64 #define MAL_CR_GA 0x00200000
65 #define MAL_CR_OA 0x00100000
66 #define MAL_CR_PLBLE 0x00080000
67 #define MAL_CR_PLBLT_1 0x00040000
68 #define MAL_CR_PLBLT_2 0x00020000
69 #define MAL_CR_PLBLT_3 0x00010000
70 #define MAL_CR_PLBLT_4 0x00008000
71 #define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
72 #define MAL_CR_PLBB 0x00004000
73 #define MAL_CR_OPBBL 0x00000080
74 #define MAL_CR_EOPIE 0x00000004
75 #define MAL_CR_LEA 0x00000002
76 #define MAL_CR_MSD 0x00000001
78 /* Error Status Reg */
79 #define MAL_ESR_EVB 0x80000000
80 #define MAL_ESR_CID 0x40000000
81 #define MAL_ESR_DE 0x00100000
82 #define MAL_ESR_ONE 0x00080000
83 #define MAL_ESR_OTE 0x00040000
84 #define MAL_ESR_OSE 0x00020000
85 #define MAL_ESR_PEIN 0x00010000
86 /* same bit position as the IER */
88 #define MAL_ESR_DEI 0x00000010
89 #define MAL_ESR_ONEI 0x00000008
90 #define MAL_ESR_OTEI 0x00000004
91 #define MAL_ESR_OSEI 0x00000002
92 #define MAL_ESR_PBEI 0x00000001
95 #if defined(CONFIG_440SPE) || \
96 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
97 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
99 #define MAL_IER_PT 0x00000080
100 #define MAL_IER_PRE 0x00000040
101 #define MAL_IER_PWE 0x00000020
102 #define MAL_IER_DE 0x00000010
103 #define MAL_IER_OTE 0x00000004
104 #define MAL_IER_OE 0x00000002
105 #define MAL_IER_PE 0x00000001
107 #define MAL_IER_DE 0x00000010
108 #define MAL_IER_NE 0x00000008
109 #define MAL_IER_TE 0x00000004
110 #define MAL_IER_OPBE 0x00000002
111 #define MAL_IER_PLBE 0x00000001
114 /* MAL Channel Active Set and Reset Registers */
115 #define MAL_TXRX_CASR (0x80000000)
117 #define MAL_TXRX_CASR_V(__x) (__x) /* Channel 0 shifts 0, channel 1 shifts 1, etc */
120 /* MAL Buffer Descriptor structure */
122 short ctrl; /* MAL / Commac status control bits */
123 short data_len; /* Max length is 4K-1 (12 bits) */
124 char *data_ptr; /* pointer to actual data buffer */