2 * Copyright © <2010>, Intel Corporation.
4 * This program is licensed under the terms and conditions of the
5 * Eclipse Public License (EPL), version 1.0. The full text of the EPL is at
6 * http://www.opensource.org/licenses/eclipse-1.0.php.
9 // Modual name: IntraFrame.asm
11 // Make intra predition estimation for Intra frame
15 // Now, begin source code....
18 include(`vme_header.inc')
24 mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1};
25 mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1};
28 * Media Read Message -- fetch neighbor edge pixels
31 mul (2) tmp_reg0.0<1>:D orig_xy_ub<2,2,1>:UB 16:UW {align1}; /* (x, y) * 16 */
32 add (1) tmp_reg0.0<1>:D tmp_reg0.0<0,1,0>:D -8:W {align1}; /* X offset */
33 add (1) tmp_reg0.4<1>:D tmp_reg0.4<0,1,0>:D -1:W {align1}; /* Y offset */
34 mov (1) tmp_reg0.8<1>:UD BLOCK_32X1 {align1};
35 mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
36 mov (8) msg_reg0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
37 send (16) 0 INEP_ROW null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
40 mul (2) tmp_reg0.0<1>:D orig_xy_ub<2,2,1>:UB 16:UW {align1}; /* (x, y) * 16 */
41 add (1) tmp_reg0.0<1>:D tmp_reg0.0<0,1,0>:D -4:W {align1}; /* X offset */
42 mov (1) tmp_reg0.8<1>:UD BLOCK_4X16 {align1};
43 mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
44 mov (8) msg_reg0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
45 send (16) 0 INEP_COL0 null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
51 mul (2) tmp_reg0.8<1>:UW orig_xy_ub<2,2,1>:UB 16:UW {align1}; /* (x, y) * 16 */
52 mov (1) tmp_reg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
53 mov (8) msg_reg0.0<1>:UD tmp_reg0.0<8,8,1>:UD {align1};
56 mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE + LUMA_INTRA_4x4_DISABLE {align1};
58 cmp.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB 0:UW {align1}; /* X != 0 */
59 (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_AE {align1}; /* A */
61 cmp.nz.f0.0 (1) null<1>:UW orig_y_ub<0,1,0>:UB 0:UW {align1}; /* Y != 0 */
62 (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_B {align1}; /* B */
64 mul.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB orig_y_ub<0,1,0>:UB {align1}; /* X * Y != 0 */
65 (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_D {align1}; /* D */
67 add (1) tmp_x_w<1>:W orig_x_ub<0,1,0>:UB 1:UW {align1}; /* X + 1 */
68 add (1) tmp_x_w<1>:W w_in_mb_uw<0,1,0>:UW -tmp_x_w<0,1,0>:W {align1}; /* width - (X + 1) */
69 mul.nz.f0.0 (1) null<1>:UD tmp_x_w<0,1,0>:W orig_y_ub<0,1,0>:UB {align1}; /* (width - (X + 1)) * Y != 0 */
70 (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_C {align1}; /* C */
72 mov (8) msg_reg1<1>:UD tmp_reg1.0<8,8,1>:UD {align1};
75 mov (8) msg_reg2<1>:UD INEP_ROW.0<8,8,1>:UD {align1};
78 mov (8) msg_reg3<1>:UD 0x0 {align1};
79 mov (16) msg_reg3.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1};
80 mov (1) msg_reg3.16<1>:UD INTRA_PREDICTORE_MODE {align1};
81 send (8) 0 vme_wb null vme(BIND_IDX_VME,0,0,VME_MESSAGE_TYPE_INTRA) mlen 4 rlen 1 {align1};
84 * Oword Block Write message
86 mul (1) tmp_reg3.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1};
87 add (1) tmp_reg3.8<1>:UD tmp_reg3.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1};
88 mov (1) tmp_reg3.20<1>:UB thread_id_ub {align1}; /* dispatch id */
89 mov (8) msg_reg0.0<1>:UD tmp_reg3<8,8,1>:UD {align1};
91 mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1};
92 mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1};
93 mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1};
94 mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1};
95 /* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */
96 send (16) 0 obw_wb null write(BIND_IDX_OUTPUT, 0, 8, 1) mlen 2 rlen 1 {align1};
101 mov (8) msg_reg0<1>:UD r0<8,8,1>:UD {align1};
102 send (16) 0 acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};