1 #ifndef _INTEL_DRIVER_H_
2 #define _INTEL_DRIVER_H_
10 #include <intel_bufmgr.h>
12 #include "va_backend.h"
15 #define INLINE __inline__
20 #define BATCH_SIZE 0x10000
21 #define BATCH_RESERVED 0x10
23 #define CMD_MI (0x0 << 29)
24 #define CMD_2D (0x2 << 29)
26 #define MI_NOOP (CMD_MI | 0)
28 #define MI_BATCH_BUFFER_END (CMD_MI | (0xA << 23))
30 #define MI_FLUSH (CMD_MI | (0x4 << 23))
31 #define STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0)
33 #define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04)
34 #define XY_COLOR_BLT_WRITE_ALPHA (1 << 21)
35 #define XY_COLOR_BLT_WRITE_RGB (1 << 20)
36 #define XY_COLOR_BLT_DST_TILED (1 << 11)
39 #define BR13_565 (0x1 << 24)
40 #define BR13_8888 (0x3 << 24)
42 struct intel_batchbuffer;
44 #define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1))
45 #define MIN(a, b) ((a) < (b) ? (a) : (b))
46 #define MAX(a, b) ((a) > (b) ? (a) : (b))
48 #define SET_BLOCKED_SIGSET() do { \
50 sigfillset(&bl_mask); \
51 sigdelset(&bl_mask, SIGFPE); \
52 sigdelset(&bl_mask, SIGILL); \
53 sigdelset(&bl_mask, SIGSEGV); \
54 sigdelset(&bl_mask, SIGBUS); \
55 sigdelset(&bl_mask, SIGKILL); \
56 pthread_sigmask(SIG_SETMASK, &bl_mask, &intel->sa_mask); \
59 #define RESTORE_BLOCKED_SIGSET() do { \
60 pthread_sigmask(SIG_SETMASK, &intel->sa_mask, NULL); \
63 #define PPTHREAD_MUTEX_LOCK() do { \
64 SET_BLOCKED_SIGSET(); \
65 pthread_mutex_lock(&intel->ctxmutex); \
68 #define PPTHREAD_MUTEX_UNLOCK() do { \
69 pthread_mutex_unlock(&intel->ctxmutex); \
70 RESTORE_BLOCKED_SIGSET(); \
73 struct intel_driver_data
79 drm_context_t hHWContext;
80 drm_i915_sarea_t *pPrivSarea;
84 pthread_mutex_t ctxmutex;
87 struct intel_batchbuffer *batch;
91 Bool intel_driver_init(VADriverContextP ctx);
92 Bool intel_driver_terminate(VADriverContextP ctx);
93 void intel_lock_hardware(VADriverContextP ctx);
94 void intel_unlock_hardware(VADriverContextP ctx);
96 static INLINE struct intel_driver_data *
97 intel_driver_data(VADriverContextP ctx)
99 return (struct intel_driver_data *)ctx->pDriverData;
111 unsigned int swizzle;
115 #define PCI_CHIP_GM45_GM 0x2A42
116 #define PCI_CHIP_IGD_E_G 0x2E02
117 #define PCI_CHIP_Q45_G 0x2E12
118 #define PCI_CHIP_G45_G 0x2E22
119 #define PCI_CHIP_G41_G 0x2E32
121 #define PCI_CHIP_IGDNG_D_G 0x0042
122 #define PCI_CHIP_IGDNG_M_G 0x0046
124 #define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
125 devid == PCI_CHIP_Q45_G || \
126 devid == PCI_CHIP_G45_G || \
127 devid == PCI_CHIP_G41_G)
128 #define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
129 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
131 #define IS_IGDNG_D(devid) (devid == PCI_CHIP_IGDNG_D_G)
132 #define IS_IGDNG_M(devid) (devid == PCI_CHIP_IGDNG_M_G)
133 #define IS_IGDNG(devid) (IS_IGDNG_D(devid) || IS_IGDNG_M(devid))
135 #endif /* _INTEL_DRIVER_H_ */