i965_drv_video/i965_post_processing.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #ifndef __I965_POST_PROCESSING_H__
  30 #define __I965_POST_PROCESSING_H__
  31
  32 #define MAX_PP_SURFACES 32
  33
  34 #define I965_PP_FLAG_DEINTERLACING      1
  35 #define I965_PP_FLAG_AVS                2
  36
  37 enum
  38 {
  39     PP_NULL = 0,
  40     PP_NV12_LOAD_SAVE,
  41     PP_NV12_SCALING,
  42     PP_NV12_AVS,
  43     PP_NV12_DNDI,
  44 };
  45
  46 #define NUM_PP_MODULES                  5
  47
  48 struct pp_load_save_context
  49 {
  50     int dest_w;
  51     int dest_h;
  52 };
  53
  54 struct pp_scaling_context
  55 {
  56     int dest_w;
  57     int dest_h;
  58 };
  59
  60 struct pp_avs_context
  61 {
  62     int dest_w;
  63     int dest_h;
  64     int src_w;
  65     int src_h;
  66 };
  67
  68 struct pp_dndi_context
  69 {
  70     int dest_w;
  71     int dest_h;
  72
  73 };
  74
  75 struct pp_module
  76 {
  77     struct i965_kernel kernel;
  78
  79     /* others */
  80     void (*initialize)(VADriverContextP ctx, VASurfaceID surface, int input,
  81                        unsigned short srcw, unsigned short srch,
  82                        unsigned short destw, unsigned short desth);
  83 };
  84
  85 struct pp_static_parameter
  86 {
  87     struct {
  88         /* Procamp r1.0 */
  89         float procamp_constant_c0;
  90
  91         /* Load and Same r1.1 */
  92         unsigned int source_packed_y_offset:8;
  93         unsigned int source_packed_u_offset:8;
  94         unsigned int source_packed_v_offset:8;
  95         unsigned int pad0:8;
  96
  97         union {
  98             /* Load and Save r1.2 */
  99             struct {
 100                 unsigned int destination_packed_y_offset:8;
 101                 unsigned int destination_packed_u_offset:8;
 102                 unsigned int destination_packed_v_offset:8;
 103                 unsigned int pad0:8;
 104             } load_and_save;
 105
 106             /* CSC r1.2 */
 107             struct {
 108                 unsigned int destination_rgb_format:8;
 109                 unsigned int pad0:24;
 110             } csc;
 111         } r1_2;
 112
 113         /* Procamp r1.3 */
 114         float procamp_constant_c1;
 115
 116         /* Procamp r1.4 */
 117         float procamp_constant_c2;
 118
 119         /* DI r1.5 */
 120         unsigned int statistics_surface_picth:16;  /* Devided by 2 */
 121         unsigned int pad1:16;
 122
 123         union {
 124             /* DI r1.6 */
 125             struct {
 126                 unsigned int pad0:24;
 127                 unsigned int top_field_first:8;
 128             } di;
 129
 130             /* AVS/Scaling r1.6 */
 131             float normalized_video_y_scaling_step;
 132         } r1_6;
 133
 134         /* Procamp r1.7 */
 135         float procamp_constant_c5;
 136     } grf1;
 137
 138     struct {
 139         /* Procamp r2.0 */
 140         float procamp_constant_c3;
 141
 142         /* MBZ r2.1*/
 143         unsigned int pad0;
 144
 145         /* WG+CSC r2.2 */
 146         float wg_csc_constant_c4;
 147
 148         /* WG+CSC r2.3 */
 149         float wg_csc_constant_c8;
 150
 151         /* Procamp r2.4 */
 152         float procamp_constant_c4;
 153
 154         /* MBZ r2.5 */
 155         unsigned int pad1;
 156
 157         /* MBZ r2.6 */
 158         unsigned int pad2;
 159
 160         /* WG+CSC r2.7 */
 161         float wg_csc_constant_c9;
 162     } grf2;
 163
 164     struct {
 165         /* WG+CSC r3.0 */
 166         float wg_csc_constant_c0;
 167
 168         /* Blending r3.1 */
 169         float scaling_step_ratio;
 170
 171         /* Blending r3.2 */
 172         float normalized_alpha_y_scaling;
 173
 174         /* WG+CSC r3.3 */
 175         float wg_csc_constant_c4;
 176
 177         /* WG+CSC r3.4 */
 178         float wg_csc_constant_c1;
 179
 180         /* ALL r3.5 */
 181         int horizontal_origin_offset:16;
 182         int vertical_origin_offset:16;
 183
 184         /* Shared r3.6*/
 185         union {
 186             /* Color filll */
 187             unsigned int color_pixel;
 188
 189             /* WG+CSC */
 190             float wg_csc_constant_c2;
 191         } r3_6;
 192
 193         /* WG+CSC r3.7 */
 194         float wg_csc_constant_c3;
 195     } grf3;
 196
 197     struct {
 198         /* WG+CSC r4.0 */
 199         float wg_csc_constant_c6;
 200
 201         /* ALL r4.1 MBZ ???*/
 202         unsigned int pad0;
 203
 204         /* Shared r4.2 */
 205         union {
 206             /* AVS */
 207             struct {
 208                 unsigned int pad1:15;
 209                 unsigned int nlas:1;
 210                 unsigned int pad2:16;
 211             } avs;
 212
 213             /* DI */
 214             struct {
 215                 unsigned int motion_history_coefficient_m2:8;
 216                 unsigned int motion_history_coefficient_m1:8;
 217                 unsigned int pad0:16;
 218             } di;
 219         } r4_2;
 220
 221         /* WG+CSC r4.3 */
 222         float wg_csc_constant_c7;
 223
 224         /* WG+CSC r4.4 */
 225         float wg_csc_constant_c10;
 226
 227         /* AVS r4.5 */
 228         float source_video_frame_normalized_horizontal_origin;
 229
 230         /* MBZ r4.6 */
 231         unsigned int pad1;
 232
 233         /* WG+CSC r4.7 */
 234         float wg_csc_constant_c11;
 235     } grf4;
 236 };
 237
 238 struct pp_inline_parameter
 239 {
 240     struct {
 241         /* ALL r5.0 */
 242         int destination_block_horizontal_origin:16;
 243         int destination_block_vertical_origin:16;
 244
 245         /* Shared r5.1 */
 246         union {
 247             /* AVS/Scaling */
 248             float source_surface_block_normalized_horizontal_origin;
 249
 250             /* FMD */
 251             struct {
 252                 unsigned int variance_surface_vertical_origin:16;
 253                 unsigned int pad0:16;
 254             } fmd;
 255         } r5_1;
 256
 257         /* AVS/Scaling r5.2 */
 258         float source_surface_block_normalized_vertical_origin;
 259
 260         /* Alpha r5.3 */
 261         float alpha_surface_block_normalized_horizontal_origin;
 262
 263         /* Alpha r5.4 */
 264         float alpha_surface_block_normalized_vertical_origin;
 265
 266         /* Alpha r5.5 */
 267         unsigned int alpha_mask_x:16;
 268         unsigned int alpha_mask_y:8;
 269         unsigned int block_count_x:8;
 270
 271         /* r5.6 */
 272         unsigned int block_horizontal_mask:16;
 273         unsigned int block_vertical_mask:8;
 274         unsigned int number_blocks:8;
 275
 276         /* AVS/Scaling r5.7 */
 277         float normalized_video_x_scaling_step;
 278     } grf5;
 279
 280     struct {
 281         /* AVS r6.0 */
 282         float video_step_delta;
 283
 284         /* r6.1-r6.7 */
 285         unsigned int padx[7];
 286     } grf6;
 287 };
 288
 289 struct i965_post_processing_context
 290 {
 291     int current_pp;
 292     struct pp_module pp_modules[NUM_PP_MODULES];
 293     struct pp_static_parameter pp_static_parameter;
 294     struct pp_inline_parameter pp_inline_parameter;
 295
 296     struct {
 297         dri_bo *bo;
 298     } curbe;
 299
 300     struct {
 301         dri_bo *ss_bo;
 302         dri_bo *s_bo;
 303     } surfaces[MAX_PP_SURFACES];
 304
 305     struct {
 306         dri_bo *bo;
 307     } binding_table;
 308
 309     struct {
 310         dri_bo *bo;
 311         int num_interface_descriptors;
 312     } idrt;
 313
 314     struct {
 315         dri_bo *bo;
 316     } vfe_state;
 317
 318     struct {
 319         dri_bo *bo;
 320         dri_bo *bo_8x8;
 321         dri_bo *bo_8x8_uv;
 322     } sampler_state_table;
 323
 324     struct {
 325         unsigned int size;
 326
 327         unsigned int vfe_start;
 328         unsigned int cs_start;
 329
 330         unsigned int num_vfe_entries;
 331         unsigned int num_cs_entries;
 332
 333         unsigned int size_vfe_entry;
 334         unsigned int size_cs_entry;
 335     } urb;
 336
 337     struct {
 338         dri_bo *bo;
 339     } stmm;
 340
 341     union {
 342         struct pp_load_save_context pp_load_save_context;
 343         struct pp_scaling_context pp_scaling_context;
 344         struct pp_avs_context pp_avs_context;
 345         struct pp_dndi_context pp_dndi_context;
 346     } private_context;
 347
 348     int (*pp_x_steps)(void *private_context);
 349     int (*pp_y_steps)(void *private_context);
 350     int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
 351 };
 352
 353 void
 354 i965_post_processing(VADriverContextP ctx,
 355                      VASurfaceID surface,
 356                      short srcx,
 357                      short srcy,
 358                      unsigned short srcw,
 359                      unsigned short srch,
 360                      short destx,
 361                      short desty,
 362                      unsigned short destw,
 363                      unsigned short desth,
 364                      unsigned int pp_index);
 365 Bool
 366 i965_post_processing_terminate(VADriverContextP ctx);
 367 Bool
 368 i965_post_processing_init(VADriverContextP ctx);
 369
 370 #endif /* __I965_POST_PROCESSING_H__ */