i965_drv_video/i965_avc_ildb.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <string.h>
  31 #include <assert.h>
  32
  33 #include "va_backend.h"
  34
  35 #include "intel_batchbuffer.h"
  36 #include "intel_driver.h"
  37
  38 #include "i965_defines.h"
  39 #include "i965_drv_video.h"
  40 #include "i965_avc_ildb.h"
  41 #include "i965_media_h264.h"
  42 #include "i965_media.h"
  43
  44 /* On Cantiga */
  45 #include "shaders/h264/mc/export.inc"
  46
  47 /* On Ironlake */
  48 #include "shaders/h264/mc/export.inc.gen5"
  49
  50 #define PICTURE_FRAME   0
  51 #define PICTURE_FIELD   1
  52 #define PICTURE_MBAFF   2
  53
  54 enum {
  55     AVC_ILDB_ROOT_Y_ILDB_FRAME,
  56     AVC_ILDB_CHILD_Y_ILDB_FRAME,
  57     AVC_ILDB_ROOT_UV_ILDB_FRAME,
  58     AVC_ILDB_CHILD_UV_ILDB_FRAME,
  59     AVC_ILDB_ROOT_Y_ILDB_FIELD,
  60     AVC_ILDB_CHILD_Y_ILDB_FIELD,
  61     AVC_ILDB_ROOT_UV_ILDB_FIELD,
  62     AVC_ILDB_CHILD_UV_ILDB_FIELD,
  63     AVC_ILDB_ROOT_Y_ILDB_MBAFF,
  64     AVC_ILDB_CHILD_Y_ILDB_MBAFF,
  65     AVC_ILDB_ROOT_UV_ILDB_MBAFF,
  66     AVC_ILDB_CHILD_UV_ILDB_MBAFF
  67 };
  68
  69 static unsigned long avc_ildb_kernel_offset_gen4[] = {
  70     AVC_ILDB_ROOT_Y_ILDB_FRAME_IP * INST_UNIT_GEN4,
  71     AVC_ILDB_CHILD_Y_ILDB_FRAME_IP * INST_UNIT_GEN4,
  72     AVC_ILDB_ROOT_UV_ILDB_FRAME_IP * INST_UNIT_GEN4,
  73     AVC_ILDB_CHILD_UV_ILDB_FRAME_IP * INST_UNIT_GEN4,
  74     AVC_ILDB_ROOT_Y_ILDB_FIELD_IP * INST_UNIT_GEN4,
  75     AVC_ILDB_CHILD_Y_ILDB_FIELD_IP * INST_UNIT_GEN4,
  76     AVC_ILDB_ROOT_UV_ILDB_FIELD_IP * INST_UNIT_GEN4,
  77     AVC_ILDB_CHILD_UV_ILDB_FIELD_IP * INST_UNIT_GEN4,
  78     AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP * INST_UNIT_GEN4,
  79     AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP * INST_UNIT_GEN4,
  80     AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP * INST_UNIT_GEN4,
  81     AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP * INST_UNIT_GEN4
  82 };
  83
  84 static unsigned long avc_ildb_kernel_offset_gen5[] = {
  85     AVC_ILDB_ROOT_Y_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
  86     AVC_ILDB_CHILD_Y_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
  87     AVC_ILDB_ROOT_UV_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
  88     AVC_ILDB_CHILD_UV_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
  89     AVC_ILDB_ROOT_Y_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
  90     AVC_ILDB_CHILD_Y_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
  91     AVC_ILDB_ROOT_UV_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
  92     AVC_ILDB_CHILD_UV_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
  93     AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
  94     AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
  95     AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
  96     AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5
  97 };
  98
  99 struct avc_ildb_root_input
 100 {
 101     unsigned int blocks_per_row : 16;
 102     unsigned int blocks_per_column : 16;
 103
 104     unsigned int picture_type : 16;
 105     unsigned int max_concurrent_threads : 16;
 106
 107     unsigned int debug_field : 16;
 108     unsigned int mbaff_frame_flag : 1;
 109     unsigned int bottom_field_flag : 1;
 110     unsigned int control_data_expansion_flag : 1;
 111     unsigned int chroma_format : 1;
 112     unsigned int pad0 : 12;
 113
 114     unsigned int ramp_constant_0;
 115
 116     unsigned int ramp_constant_1;
 117
 118     int constant_0 : 8;
 119     int constant_1 : 8;
 120     int pad1 : 16;
 121
 122     unsigned int pad2;
 123     unsigned int pad3;
 124 };
 125
 126 extern struct media_kernel *h264_avc_kernels;
 127
 128 #define NUM_AVC_ILDB_INTERFACES ARRAY_ELEMS(avc_ildb_kernel_offset_gen4)
 129 static unsigned long *avc_ildb_kernel_offset = NULL;
 130
 131 static void
 132 i965_avc_ildb_surface_state(VADriverContextP ctx,
 133                             struct decode_state *decode_state,
 134                             struct i965_h264_context *i965_h264_context)
 135 {
 136     struct i965_driver_data *i965 = i965_driver_data(ctx);
 137     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 138     struct i965_surface_state *ss;
 139     struct object_surface *obj_surface;
 140     VAPictureParameterBufferH264 *pic_param;
 141     VAPictureH264 *va_pic;
 142     dri_bo *bo;
 143     int i;
 144
 145     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 146     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 147     va_pic = &pic_param->CurrPic;
 148     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 149     obj_surface = SURFACE(va_pic->picture_id);
 150     assert(obj_surface);
 151
 152     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].s_bo = i965_h264_context->avc_ildb_data.bo;
 153     dri_bo_reference(avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].s_bo);
 154     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].offset = 0;
 155     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].surface_type = I965_SURFACE_BUFFER;
 156     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].width = ((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) & 0x7f);
 157     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].height = (((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) >> 7) & 0x1fff);
 158     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].depth = (((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) >> 20) & 0x7f);
 159     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].pitch = EDGE_CONTROL_DATA_IN_BTYES - 1;
 160     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].is_target = 0;
 161
 162     avc_ildb_context->surface[SURFACE_SRC_Y].s_bo = obj_surface->bo;
 163     dri_bo_reference(avc_ildb_context->surface[SURFACE_SRC_Y].s_bo);
 164     avc_ildb_context->surface[SURFACE_SRC_Y].offset = 0;
 165     avc_ildb_context->surface[SURFACE_SRC_Y].surface_type = I965_SURFACE_2D;
 166     avc_ildb_context->surface[SURFACE_SRC_Y].format = I965_SURFACEFORMAT_R8_SINT;
 167     avc_ildb_context->surface[SURFACE_SRC_Y].width = obj_surface->width / 4 - 1;
 168     avc_ildb_context->surface[SURFACE_SRC_Y].height = obj_surface->height - 1;
 169     avc_ildb_context->surface[SURFACE_SRC_Y].depth = 0;
 170     avc_ildb_context->surface[SURFACE_SRC_Y].pitch = obj_surface->width - 1;
 171     avc_ildb_context->surface[SURFACE_SRC_Y].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
 172     avc_ildb_context->surface[SURFACE_SRC_Y].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
 173     avc_ildb_context->surface[SURFACE_SRC_Y].is_target = 0;
 174
 175     avc_ildb_context->surface[SURFACE_SRC_UV].s_bo = obj_surface->bo;
 176     dri_bo_reference(avc_ildb_context->surface[SURFACE_SRC_UV].s_bo);
 177     avc_ildb_context->surface[SURFACE_SRC_UV].offset = obj_surface->width * obj_surface->height;
 178     avc_ildb_context->surface[SURFACE_SRC_UV].surface_type = I965_SURFACE_2D;
 179     avc_ildb_context->surface[SURFACE_SRC_UV].format = I965_SURFACEFORMAT_R8G8_SINT;
 180     avc_ildb_context->surface[SURFACE_SRC_UV].width = obj_surface->width / 4 - 1;
 181     avc_ildb_context->surface[SURFACE_SRC_UV].height = obj_surface->height / 2 - 1;
 182     avc_ildb_context->surface[SURFACE_SRC_UV].depth = 0;
 183     avc_ildb_context->surface[SURFACE_SRC_UV].pitch = obj_surface->width - 1;
 184     avc_ildb_context->surface[SURFACE_SRC_UV].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
 185     avc_ildb_context->surface[SURFACE_SRC_UV].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
 186     avc_ildb_context->surface[SURFACE_SRC_UV].is_target = 0;
 187
 188     avc_ildb_context->surface[SURFACE_DEST_Y].s_bo = obj_surface->bo;
 189     dri_bo_reference(avc_ildb_context->surface[SURFACE_DEST_Y].s_bo);
 190     avc_ildb_context->surface[SURFACE_DEST_Y].offset = 0;
 191     avc_ildb_context->surface[SURFACE_DEST_Y].surface_type = I965_SURFACE_2D;
 192     avc_ildb_context->surface[SURFACE_DEST_Y].format = I965_SURFACEFORMAT_R8_SINT;
 193     avc_ildb_context->surface[SURFACE_DEST_Y].width = obj_surface->width / 4 - 1;
 194     avc_ildb_context->surface[SURFACE_DEST_Y].height = obj_surface->height - 1;
 195     avc_ildb_context->surface[SURFACE_DEST_Y].depth = 0;
 196     avc_ildb_context->surface[SURFACE_DEST_Y].pitch = obj_surface->width - 1;
 197     avc_ildb_context->surface[SURFACE_DEST_Y].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
 198     avc_ildb_context->surface[SURFACE_DEST_Y].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
 199     avc_ildb_context->surface[SURFACE_DEST_Y].is_target = 1;
 200
 201     avc_ildb_context->surface[SURFACE_DEST_UV].s_bo = obj_surface->bo;
 202     dri_bo_reference(avc_ildb_context->surface[SURFACE_DEST_UV].s_bo);
 203     avc_ildb_context->surface[SURFACE_DEST_UV].offset = obj_surface->width * obj_surface->height;
 204     avc_ildb_context->surface[SURFACE_DEST_UV].surface_type = I965_SURFACE_2D;
 205     avc_ildb_context->surface[SURFACE_DEST_UV].format = I965_SURFACEFORMAT_R8G8_SINT;
 206     avc_ildb_context->surface[SURFACE_DEST_UV].width = obj_surface->width / 4 - 1;
 207     avc_ildb_context->surface[SURFACE_DEST_UV].height = obj_surface->height / 2 - 1;
 208     avc_ildb_context->surface[SURFACE_DEST_UV].depth = 0;
 209     avc_ildb_context->surface[SURFACE_DEST_UV].pitch = obj_surface->width - 1;
 210     avc_ildb_context->surface[SURFACE_DEST_UV].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
 211     avc_ildb_context->surface[SURFACE_DEST_UV].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
 212     avc_ildb_context->surface[SURFACE_DEST_UV].is_target = 1;
 213
 214     for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
 215         bo = avc_ildb_context->surface[i].ss_bo;
 216         dri_bo_map(bo, 1);
 217         assert(bo->virtual);
 218         ss = bo->virtual;
 219         memset(ss, 0, sizeof(*ss));
 220         ss->ss0.surface_type = avc_ildb_context->surface[i].surface_type;
 221         ss->ss0.surface_format = avc_ildb_context->surface[i].format;
 222         ss->ss0.vert_line_stride = avc_ildb_context->surface[i].vert_line_stride;
 223         ss->ss0.vert_line_stride_ofs = avc_ildb_context->surface[i].vert_line_stride_ofs;
 224         ss->ss1.base_addr = avc_ildb_context->surface[i].s_bo->offset + avc_ildb_context->surface[i].offset;
 225         ss->ss2.width = avc_ildb_context->surface[i].width;
 226         ss->ss2.height = avc_ildb_context->surface[i].height;
 227         ss->ss3.depth = avc_ildb_context->surface[i].depth;
 228         ss->ss3.pitch = avc_ildb_context->surface[i].pitch;
 229         dri_bo_emit_reloc(bo,
 230                           I915_GEM_DOMAIN_RENDER,
 231                           avc_ildb_context->surface[i].is_target ? I915_GEM_DOMAIN_RENDER : 0,
 232                           avc_ildb_context->surface[i].offset,
 233                           offsetof(struct i965_surface_state, ss1),
 234                           avc_ildb_context->surface[i].s_bo);
 235         dri_bo_unmap(bo);
 236     }
 237 }
 238
 239 static void
 240 i965_avc_ildb_binding_table(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 241 {
 242     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 243     unsigned int *binding_table;
 244     dri_bo *bo = avc_ildb_context->binding_table.bo;
 245     int i;
 246
 247     dri_bo_map(bo, 1);
 248     assert(bo->virtual);
 249     binding_table = bo->virtual;
 250     memset(binding_table, 0, bo->size);
 251
 252     for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
 253         binding_table[i] = avc_ildb_context->surface[i].ss_bo->offset;
 254         dri_bo_emit_reloc(bo,
 255                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 256                           0,
 257                           i * sizeof(*binding_table),
 258                           avc_ildb_context->surface[i].ss_bo);
 259     }
 260
 261     dri_bo_unmap(bo);
 262 }
 263
 264 static void
 265 i965_avc_ildb_interface_descriptor_table(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 266 {
 267     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 268     struct i965_interface_descriptor *desc;
 269     dri_bo *bo;
 270     int i;
 271
 272     bo = avc_ildb_context->idrt.bo;
 273     dri_bo_map(bo, 1);
 274     assert(bo->virtual);
 275     desc = bo->virtual;
 276
 277     for (i = 0; i < NUM_AVC_ILDB_INTERFACES; i++) {
 278         int kernel_offset = avc_ildb_kernel_offset[i];
 279         memset(desc, 0, sizeof(*desc));
 280         desc->desc0.grf_reg_blocks = 7;
 281         desc->desc0.kernel_start_pointer = (h264_avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */
 282         desc->desc1.const_urb_entry_read_offset = 0;
 283         desc->desc1.const_urb_entry_read_len = ((i == AVC_ILDB_ROOT_Y_ILDB_FRAME ||
 284                                                  i == AVC_ILDB_ROOT_Y_ILDB_FIELD ||
 285                                                  i == AVC_ILDB_ROOT_Y_ILDB_MBAFF) ? 1 : 0);
 286         desc->desc3.binding_table_entry_count = 0;
 287         desc->desc3.binding_table_pointer =
 288             avc_ildb_context->binding_table.bo->offset >> 5; /*reloc */
 289
 290         dri_bo_emit_reloc(bo,
 291                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 292                           desc->desc0.grf_reg_blocks + kernel_offset,
 293                           i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0),
 294                           h264_avc_kernels[H264_AVC_COMBINED].bo);
 295
 296         dri_bo_emit_reloc(bo,
 297                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 298                           desc->desc3.binding_table_entry_count,
 299                           i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc3),
 300                           avc_ildb_context->binding_table.bo);
 301         desc++;
 302     }
 303
 304     dri_bo_unmap(bo);
 305 }
 306
 307 static void
 308 i965_avc_ildb_vfe_state(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 309 {
 310     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 311     struct i965_vfe_state *vfe_state;
 312     dri_bo *bo;
 313
 314     bo = avc_ildb_context->vfe_state.bo;
 315     dri_bo_map(bo, 1);
 316     assert(bo->virtual);
 317     vfe_state = bo->virtual;
 318     memset(vfe_state, 0, sizeof(*vfe_state));
 319     vfe_state->vfe1.max_threads = 0;
 320     vfe_state->vfe1.urb_entry_alloc_size = avc_ildb_context->urb.size_vfe_entry - 1;
 321     vfe_state->vfe1.num_urb_entries = avc_ildb_context->urb.num_vfe_entries;
 322     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 323     vfe_state->vfe1.children_present = 1;
 324     vfe_state->vfe2.interface_descriptor_base =
 325         avc_ildb_context->idrt.bo->offset >> 4; /* reloc */
 326     dri_bo_emit_reloc(bo,
 327                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 328                       0,
 329                       offsetof(struct i965_vfe_state, vfe2),
 330                       avc_ildb_context->idrt.bo);
 331     dri_bo_unmap(bo);
 332 }
 333
 334 static void
 335 i965_avc_ildb_upload_constants(VADriverContextP ctx,
 336                                struct decode_state *decode_state,
 337                                struct i965_h264_context *i965_h264_context)
 338 {
 339     struct i965_driver_data *i965 = i965_driver_data(ctx);
 340     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 341     VAPictureParameterBufferH264 *pic_param;
 342     struct avc_ildb_root_input *root_input;
 343
 344     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 345     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 346
 347     dri_bo_map(avc_ildb_context->curbe.bo, 1);
 348     assert(avc_ildb_context->curbe.bo->virtual);
 349     root_input = avc_ildb_context->curbe.bo->virtual;
 350
 351     if (IS_IRONLAKE(i965->intel.device_id)) {
 352         root_input->max_concurrent_threads = 76; /* 72 - 2 + 8 - 2 */
 353     } else {
 354         root_input->max_concurrent_threads = 54; /* 50 - 2 + 8 - 2 */
 355     }
 356
 357     if (pic_param->pic_fields.bits.field_pic_flag)
 358         root_input->picture_type = PICTURE_FIELD;
 359     else {
 360         if (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag)
 361             root_input->picture_type = PICTURE_MBAFF;
 362         else
 363             root_input->picture_type = PICTURE_FRAME;
 364     }
 365
 366     avc_ildb_context->picture_type = root_input->picture_type;
 367     root_input->blocks_per_row = pic_param->picture_width_in_mbs_minus1 + 1;
 368     root_input->blocks_per_column = (pic_param->picture_height_in_mbs_minus1 + 1) /
 369         (1 + (root_input->picture_type != PICTURE_FRAME));
 370     avc_ildb_context->mbs_per_picture = (pic_param->picture_width_in_mbs_minus1 + 1) *
 371         (pic_param->picture_height_in_mbs_minus1 + 1);
 372
 373     root_input->mbaff_frame_flag = (root_input->picture_type == PICTURE_MBAFF);
 374     root_input->bottom_field_flag = !!(pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD);
 375     root_input->control_data_expansion_flag = 1; /* Always 1 on G4x+ */
 376     root_input->chroma_format = (pic_param->seq_fields.bits.chroma_format_idc != 1); /* 0=4:0:0, 1=4:2:0 */
 377
 378     root_input->ramp_constant_0 = 0x03020100;
 379
 380     root_input->ramp_constant_1 = 0x07060504;
 381
 382     root_input->constant_0 = -2;
 383     root_input->constant_1 = 1;
 384
 385     dri_bo_unmap(avc_ildb_context->curbe.bo);
 386 }
 387
 388 static void
 389 i965_avc_ildb_states_setup(VADriverContextP ctx,
 390                            struct decode_state *decode_state,
 391                            struct i965_h264_context *i965_h264_context)
 392 {
 393     i965_avc_ildb_surface_state(ctx, decode_state, i965_h264_context);
 394     i965_avc_ildb_binding_table(ctx, i965_h264_context);
 395     i965_avc_ildb_interface_descriptor_table(ctx, i965_h264_context);
 396     i965_avc_ildb_vfe_state(ctx, i965_h264_context);
 397     i965_avc_ildb_upload_constants(ctx, decode_state, i965_h264_context);
 398 }
 399
 400 static void
 401 i965_avc_ildb_pipeline_select(VADriverContextP ctx)
 402 {
 403     BEGIN_BATCH(ctx, 1);
 404     OUT_BATCH(ctx, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 405     ADVANCE_BATCH(ctx);
 406 }
 407
 408 static void
 409 i965_avc_ildb_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 410 {
 411     struct i965_driver_data *i965 = i965_driver_data(ctx);
 412     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 413
 414     unsigned int vfe_fence, cs_fence;
 415
 416     vfe_fence = avc_ildb_context->urb.cs_start;
 417     cs_fence = URB_SIZE((&i965->intel));
 418
 419     BEGIN_BATCH(ctx, 3);
 420     OUT_BATCH(ctx, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 421     OUT_BATCH(ctx, 0);
 422     OUT_BATCH(ctx,
 423               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 424               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 425     ADVANCE_BATCH(ctx);
 426 }
 427
 428 static void
 429 i965_avc_ildb_state_base_address(VADriverContextP ctx)
 430 {
 431     struct i965_driver_data *i965 = i965_driver_data(ctx);
 432
 433     if (IS_IRONLAKE(i965->intel.device_id)) {
 434         BEGIN_BATCH(ctx, 8);
 435         OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 6);
 436         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 437         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 438         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 439         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 440         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 441         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 442         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 443         ADVANCE_BATCH(ctx);
 444     } else {
 445         BEGIN_BATCH(ctx, 6);
 446         OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 4);
 447         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 448         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 449         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 450         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 451         OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);
 452         ADVANCE_BATCH(ctx);
 453     }
 454 }
 455
 456 static void
 457 i965_avc_ildb_state_pointers(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 458 {
 459     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 460
 461     BEGIN_BATCH(ctx, 3);
 462     OUT_BATCH(ctx, CMD_MEDIA_STATE_POINTERS | 1);
 463     OUT_BATCH(ctx, 0);
 464     OUT_RELOC(ctx, avc_ildb_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 465     ADVANCE_BATCH(ctx);
 466 }
 467
 468 static void
 469 i965_avc_ildb_cs_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 470 {
 471     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 472
 473     BEGIN_BATCH(ctx, 2);
 474     OUT_BATCH(ctx, CMD_CS_URB_STATE | 0);
 475     OUT_BATCH(ctx,
 476               ((avc_ildb_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 477               (avc_ildb_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 478     ADVANCE_BATCH(ctx);
 479 }
 480
 481 static void
 482 i965_avc_ildb_constant_buffer(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 483 {
 484     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 485
 486     BEGIN_BATCH(ctx, 2);
 487     OUT_BATCH(ctx, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
 488     OUT_RELOC(ctx, avc_ildb_context->curbe.bo,
 489               I915_GEM_DOMAIN_INSTRUCTION, 0,
 490               avc_ildb_context->urb.size_cs_entry - 1);
 491     ADVANCE_BATCH(ctx);
 492 }
 493
 494 static void
 495 i965_avc_ildb_objects(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 496 {
 497     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
 498
 499     BEGIN_BATCH(ctx, 6);
 500     OUT_BATCH(ctx, CMD_MEDIA_OBJECT | 4);
 501
 502     switch (avc_ildb_context->picture_type) {
 503     case PICTURE_FRAME:
 504         OUT_BATCH(ctx, AVC_ILDB_ROOT_Y_ILDB_FRAME);
 505         break;
 506
 507     case PICTURE_FIELD:
 508         OUT_BATCH(ctx, AVC_ILDB_ROOT_Y_ILDB_FIELD);
 509         break;
 510
 511     case PICTURE_MBAFF:
 512         OUT_BATCH(ctx, AVC_ILDB_ROOT_Y_ILDB_MBAFF);
 513         break;
 514
 515     default:
 516         assert(0);
 517         OUT_BATCH(ctx, 0);
 518         break;
 519     }
 520
 521     OUT_BATCH(ctx, 0); /* no indirect data */
 522     OUT_BATCH(ctx, 0);
 523     OUT_BATCH(ctx, 0);
 524     OUT_BATCH(ctx, 0);
 525     ADVANCE_BATCH(ctx);
 526 }
 527
 528 static void
 529 i965_avc_ildb_pipeline_setup(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 530 {
 531     intel_batchbuffer_emit_mi_flush(ctx);
 532     i965_avc_ildb_pipeline_select(ctx);
 533     i965_avc_ildb_state_base_address(ctx);
 534     i965_avc_ildb_state_pointers(ctx, i965_h264_context);
 535     i965_avc_ildb_urb_layout(ctx, i965_h264_context);
 536     i965_avc_ildb_cs_urb_layout(ctx, i965_h264_context);
 537     i965_avc_ildb_constant_buffer(ctx, i965_h264_context);
 538     i965_avc_ildb_objects(ctx, i965_h264_context);
 539 }
 540
 541 void
 542 i965_avc_ildb(VADriverContextP ctx, struct decode_state *decode_state, void *h264_context)
 543 {
 544     struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
 545
 546     if (i965_h264_context->enable_avc_ildb) {
 547         i965_avc_ildb_states_setup(ctx, decode_state, i965_h264_context);
 548         i965_avc_ildb_pipeline_setup(ctx, i965_h264_context);
 549     }
 550 }
 551
 552 void
 553 i965_avc_ildb_decode_init(VADriverContextP ctx, void *h264_context)
 554 {
 555     struct i965_driver_data *i965 = i965_driver_data(ctx);
 556     struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
 557     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;;
 558     dri_bo *bo;
 559     int i;
 560
 561     dri_bo_unreference(avc_ildb_context->curbe.bo);
 562     bo = dri_bo_alloc(i965->intel.bufmgr,
 563                       "constant buffer",
 564                       4096, 64);
 565     assert(bo);
 566     avc_ildb_context->curbe.bo = bo;
 567
 568     dri_bo_unreference(avc_ildb_context->binding_table.bo);
 569     bo = dri_bo_alloc(i965->intel.bufmgr,
 570                       "binding table",
 571                       NUM_AVC_ILDB_SURFACES * sizeof(unsigned int), 32);
 572     assert(bo);
 573     avc_ildb_context->binding_table.bo = bo;
 574
 575     dri_bo_unreference(avc_ildb_context->idrt.bo);
 576     bo = dri_bo_alloc(i965->intel.bufmgr,
 577                       "interface discriptor",
 578                       NUM_AVC_ILDB_INTERFACES * sizeof(struct i965_interface_descriptor), 16);
 579     assert(bo);
 580     avc_ildb_context->idrt.bo = bo;
 581
 582     dri_bo_unreference(avc_ildb_context->vfe_state.bo);
 583     bo = dri_bo_alloc(i965->intel.bufmgr,
 584                       "vfe state",
 585                       sizeof(struct i965_vfe_state), 32);
 586     assert(bo);
 587     avc_ildb_context->vfe_state.bo = bo;
 588
 589     avc_ildb_context->urb.num_vfe_entries = 1;
 590     avc_ildb_context->urb.size_vfe_entry = 640;
 591     avc_ildb_context->urb.num_cs_entries = 1;
 592     avc_ildb_context->urb.size_cs_entry = 1;
 593     avc_ildb_context->urb.vfe_start = 0;
 594     avc_ildb_context->urb.cs_start = avc_ildb_context->urb.vfe_start +
 595         avc_ildb_context->urb.num_vfe_entries * avc_ildb_context->urb.size_vfe_entry;
 596     assert(avc_ildb_context->urb.cs_start +
 597            avc_ildb_context->urb.num_cs_entries * avc_ildb_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
 598
 599     for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
 600         dri_bo_unreference(avc_ildb_context->surface[i].s_bo);
 601         avc_ildb_context->surface[i].s_bo = NULL;
 602
 603         dri_bo_unreference(avc_ildb_context->surface[i].ss_bo);
 604         bo = dri_bo_alloc(i965->intel.bufmgr,
 605                           "surface state",
 606                           sizeof(struct i965_surface_state), 32);
 607         assert(bo);
 608         avc_ildb_context->surface[i].ss_bo = bo;
 609     }
 610
 611     /* kernel offset */
 612     assert(NUM_AVC_ILDB_INTERFACES == ARRAY_ELEMS(avc_ildb_kernel_offset_gen5));
 613
 614     if (IS_IRONLAKE(i965->intel.device_id)) {
 615         avc_ildb_kernel_offset = avc_ildb_kernel_offset_gen5;
 616     } else {
 617         avc_ildb_kernel_offset = avc_ildb_kernel_offset_gen4;
 618     }
 619 }
 620
 621 Bool
 622 i965_avc_ildb_ternimate(struct i965_avc_ildb_context *avc_ildb_context)
 623 {
 624     int i;
 625
 626     dri_bo_unreference(avc_ildb_context->curbe.bo);
 627     avc_ildb_context->curbe.bo = NULL;
 628
 629     dri_bo_unreference(avc_ildb_context->binding_table.bo);
 630     avc_ildb_context->binding_table.bo = NULL;
 631
 632     dri_bo_unreference(avc_ildb_context->idrt.bo);
 633     avc_ildb_context->idrt.bo = NULL;
 634
 635     dri_bo_unreference(avc_ildb_context->vfe_state.bo);
 636     avc_ildb_context->vfe_state.bo = NULL;
 637
 638     for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
 639         dri_bo_unreference(avc_ildb_context->surface[i].ss_bo);
 640         avc_ildb_context->surface[i].ss_bo = NULL;
 641
 642         dri_bo_unreference(avc_ildb_context->surface[i].s_bo);
 643         avc_ildb_context->surface[i].s_bo = NULL;
 644     }
 645
 646     return True;
 647 }