i965_drv_video/i965_avc_hw_scoreboard.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <string.h>
  31 #include <assert.h>
  32
  33 #include "va_backend.h"
  34
  35 #include "intel_batchbuffer.h"
  36 #include "intel_driver.h"
  37
  38 #include "i965_defines.h"
  39 #include "i965_drv_video.h"
  40 #include "i965_avc_hw_scoreboard.h"
  41 #include "i965_media_h264.h"
  42 #include "i965_media.h"
  43
  44 /* On Ironlake */
  45 #include "shaders/h264/mc/export.inc.gen5"
  46
  47 enum {
  48     AVC_HW_SCOREBOARD = 0,
  49     AVC_HW_SCOREBOARD_MBAFF
  50 };
  51
  52 static unsigned long avc_hw_scoreboard_kernel_offset[] = {
  53     SETHWSCOREBOARD_IP_GEN5 * INST_UNIT_GEN5,
  54     SETHWSCOREBOARD_MBAFF_IP_GEN5 * INST_UNIT_GEN5
  55 };
  56
  57 static unsigned int avc_hw_scoreboard_constants[] = {
  58     0x08040201,
  59     0x00000010,
  60     0x08000210,
  61     0x00000000,
  62     0x08040201,
  63     0x08040210,
  64     0x01000010,
  65     0x08040200
  66 };
  67
  68 static void
  69 i965_avc_hw_scoreboard_surface_state(struct i965_h264_context *i965_h264_context)
  70 {
  71     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
  72     struct i965_surface_state *ss;
  73     dri_bo *bo;
  74
  75     bo = avc_hw_scoreboard_context->surface.ss_bo;
  76     dri_bo_map(bo, 1);
  77     assert(bo->virtual);
  78     ss = bo->virtual;
  79     memset(ss, 0, sizeof(*ss));
  80     ss->ss0.surface_type = I965_SURFACE_BUFFER;
  81     ss->ss1.base_addr = avc_hw_scoreboard_context->surface.s_bo->offset;
  82     ss->ss2.width = ((avc_hw_scoreboard_context->surface.total_mbs * MB_CMD_IN_OWS - 1) & 0x7f);
  83     ss->ss2.height = (((avc_hw_scoreboard_context->surface.total_mbs * MB_CMD_IN_OWS - 1) >> 7) & 0x1fff);
  84     ss->ss3.depth = (((avc_hw_scoreboard_context->surface.total_mbs * MB_CMD_IN_OWS - 1) >> 20) & 0x7f);
  85     dri_bo_emit_reloc(bo,
  86                       I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  87                       0,
  88                       offsetof(struct i965_surface_state, ss1),
  89                       avc_hw_scoreboard_context->surface.s_bo);
  90     dri_bo_unmap(bo);
  91 }
  92
  93 static void
  94 i965_avc_hw_scoreboard_interface_descriptor_table(struct i965_h264_context *i965_h264_context)
  95 {
  96     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
  97     struct i965_interface_descriptor *desc;
  98     dri_bo *bo;
  99
 100     bo = avc_hw_scoreboard_context->idrt.bo;
 101     dri_bo_map(bo, 1);
 102     assert(bo->virtual);
 103     desc = bo->virtual;
 104     memset(desc, 0, sizeof(*desc));
 105     desc->desc0.grf_reg_blocks = 7;
 106     desc->desc0.kernel_start_pointer = (avc_hw_scoreboard_context->hw_kernel.bo->offset +
 107                                         avc_hw_scoreboard_context->hw_kernel.offset) >> 6; /* reloc */
 108     desc->desc1.const_urb_entry_read_offset = 0;
 109     desc->desc1.const_urb_entry_read_len = 1;
 110     desc->desc3.binding_table_entry_count = 0;
 111     desc->desc3.binding_table_pointer =
 112         avc_hw_scoreboard_context->binding_table.bo->offset >> 5; /*reloc */
 113
 114     dri_bo_emit_reloc(bo,
 115                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 116                       desc->desc0.grf_reg_blocks + avc_hw_scoreboard_context->hw_kernel.offset,
 117                       offsetof(struct i965_interface_descriptor, desc0),
 118                       avc_hw_scoreboard_context->hw_kernel.bo);
 119
 120     dri_bo_emit_reloc(bo,
 121                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 122                       desc->desc3.binding_table_entry_count,
 123                       offsetof(struct i965_interface_descriptor, desc3),
 124                       avc_hw_scoreboard_context->binding_table.bo);
 125
 126     dri_bo_unmap(bo);
 127 }
 128
 129 static void
 130 i965_avc_hw_scoreboard_binding_table(struct i965_h264_context *i965_h264_context)
 131 {
 132     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 133     unsigned int *binding_table;
 134     dri_bo *bo = avc_hw_scoreboard_context->binding_table.bo;
 135
 136     dri_bo_map(bo, 1);
 137     assert(bo->virtual);
 138     binding_table = bo->virtual;
 139     memset(binding_table, 0, bo->size);
 140     binding_table[0] = avc_hw_scoreboard_context->surface.ss_bo->offset;
 141     dri_bo_emit_reloc(bo,
 142                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 143                       0,
 144                       0,
 145                       avc_hw_scoreboard_context->surface.ss_bo);
 146     dri_bo_unmap(bo);
 147 }
 148
 149 static void
 150 i965_avc_hw_scoreboard_vfe_state(struct i965_h264_context *i965_h264_context)
 151 {
 152     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 153     struct i965_vfe_state *vfe_state;
 154     dri_bo *bo;
 155
 156     bo = avc_hw_scoreboard_context->vfe_state.bo;
 157     dri_bo_map(bo, 1);
 158     assert(bo->virtual);
 159     vfe_state = bo->virtual;
 160     memset(vfe_state, 0, sizeof(*vfe_state));
 161     vfe_state->vfe1.max_threads = avc_hw_scoreboard_context->urb.num_vfe_entries - 1;
 162     vfe_state->vfe1.urb_entry_alloc_size = avc_hw_scoreboard_context->urb.size_vfe_entry - 1;
 163     vfe_state->vfe1.num_urb_entries = avc_hw_scoreboard_context->urb.num_vfe_entries;
 164     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
 165     vfe_state->vfe1.children_present = 0;
 166     vfe_state->vfe2.interface_descriptor_base =
 167         avc_hw_scoreboard_context->idrt.bo->offset >> 4; /* reloc */
 168     dri_bo_emit_reloc(bo,
 169                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 170                       0,
 171                       offsetof(struct i965_vfe_state, vfe2),
 172                       avc_hw_scoreboard_context->idrt.bo);
 173     dri_bo_unmap(bo);
 174 }
 175
 176 static void
 177 i965_avc_hw_scoreboard_upload_constants(struct i965_h264_context *i965_h264_context)
 178 {
 179     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 180     unsigned char *constant_buffer;
 181
 182     if (avc_hw_scoreboard_context->curbe.upload)
 183         return;
 184
 185     dri_bo_map(avc_hw_scoreboard_context->curbe.bo, 1);
 186     assert(avc_hw_scoreboard_context->curbe.bo->virtual);
 187     constant_buffer = avc_hw_scoreboard_context->curbe.bo->virtual;
 188     memcpy(constant_buffer, avc_hw_scoreboard_constants, sizeof(avc_hw_scoreboard_constants));
 189     dri_bo_unmap(avc_hw_scoreboard_context->curbe.bo);
 190     avc_hw_scoreboard_context->curbe.upload = 1;
 191 }
 192
 193 static void
 194 i965_avc_hw_scoreboard_states_setup(struct i965_h264_context *i965_h264_context)
 195 {
 196     i965_avc_hw_scoreboard_surface_state(i965_h264_context);
 197     i965_avc_hw_scoreboard_binding_table(i965_h264_context);
 198     i965_avc_hw_scoreboard_interface_descriptor_table(i965_h264_context);
 199     i965_avc_hw_scoreboard_vfe_state(i965_h264_context);
 200     i965_avc_hw_scoreboard_upload_constants(i965_h264_context);
 201 }
 202
 203 static void
 204 i965_avc_hw_scoreboard_pipeline_select(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 205 {
 206     struct intel_batchbuffer *batch = i965_h264_context->batch;
 207
 208     BEGIN_BATCH(batch, 1);
 209     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 210     ADVANCE_BATCH(batch);
 211 }
 212
 213 static void
 214 i965_avc_hw_scoreboard_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 215 {
 216     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 217     struct i965_driver_data *i965 = i965_driver_data(ctx);
 218     struct intel_batchbuffer *batch = i965_h264_context->batch;
 219     unsigned int vfe_fence, cs_fence;
 220
 221     vfe_fence = avc_hw_scoreboard_context->urb.cs_start;
 222     cs_fence = URB_SIZE((&i965->intel));
 223
 224     BEGIN_BATCH(batch, 3);
 225     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
 226     OUT_BATCH(batch, 0);
 227     OUT_BATCH(batch,
 228               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
 229               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
 230     ADVANCE_BATCH(batch);
 231 }
 232
 233 static void
 234 i965_avc_hw_scoreboard_state_base_address(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 235 {
 236     struct intel_batchbuffer *batch = i965_h264_context->batch;
 237
 238     BEGIN_BATCH(batch, 8);
 239     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
 240     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 241     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 242     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 243     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 244     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 245     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 246     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
 247     ADVANCE_BATCH(batch);
 248 }
 249
 250 static void
 251 i965_avc_hw_scoreboard_state_pointers(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 252 {
 253     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 254     struct intel_batchbuffer *batch = i965_h264_context->batch;
 255
 256     BEGIN_BATCH(batch, 3);
 257     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
 258     OUT_BATCH(batch, 0);
 259     OUT_RELOC(batch, avc_hw_scoreboard_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 260     ADVANCE_BATCH(batch);
 261 }
 262
 263 static void
 264 i965_avc_hw_scoreboard_cs_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 265 {
 266     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 267     struct intel_batchbuffer *batch = i965_h264_context->batch;
 268
 269     BEGIN_BATCH(batch, 2);
 270     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
 271     OUT_BATCH(batch,
 272               ((avc_hw_scoreboard_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
 273               (avc_hw_scoreboard_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
 274     ADVANCE_BATCH(batch);
 275 }
 276
 277 static void
 278 i965_avc_hw_scoreboard_constant_buffer(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 279 {
 280     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 281     struct intel_batchbuffer *batch = i965_h264_context->batch;
 282
 283     BEGIN_BATCH(batch, 2);
 284     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
 285     OUT_RELOC(batch, avc_hw_scoreboard_context->curbe.bo,
 286               I915_GEM_DOMAIN_INSTRUCTION, 0,
 287               avc_hw_scoreboard_context->urb.size_cs_entry - 1);
 288     ADVANCE_BATCH(batch);
 289 }
 290
 291 static void
 292 i965_avc_hw_scoreboard_objects(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 293 {
 294     struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 295     struct intel_batchbuffer *batch = i965_h264_context->batch;
 296     int number_mb_cmds = 512;
 297     int starting_mb_number = avc_hw_scoreboard_context->inline_data.starting_mb_number;
 298     int i;
 299
 300     for (i = 0; i < avc_hw_scoreboard_context->inline_data.num_mb_cmds / 512; i++) {
 301         BEGIN_BATCH(batch, 6);
 302         OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4);
 303         OUT_BATCH(batch, 0); /* interface descriptor offset: 0 */
 304         OUT_BATCH(batch, 0); /* no indirect data */
 305         OUT_BATCH(batch, 0);
 306         OUT_BATCH(batch, ((number_mb_cmds << 16) |
 307                         (starting_mb_number << 0)));
 308         OUT_BATCH(batch, avc_hw_scoreboard_context->inline_data.pic_width_in_mbs);
 309         ADVANCE_BATCH(batch);
 310
 311         starting_mb_number += 512;
 312     }
 313
 314     number_mb_cmds = avc_hw_scoreboard_context->inline_data.num_mb_cmds % 512;
 315
 316     if (number_mb_cmds) {
 317         BEGIN_BATCH(batch, 6);
 318         OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4);
 319         OUT_BATCH(batch, 0); /* interface descriptor offset: 0 */
 320         OUT_BATCH(batch, 0); /* no indirect data */
 321         OUT_BATCH(batch, 0);
 322         OUT_BATCH(batch, ((number_mb_cmds << 16) |
 323                         (starting_mb_number << 0)));
 324         OUT_BATCH(batch, avc_hw_scoreboard_context->inline_data.pic_width_in_mbs);
 325         ADVANCE_BATCH(batch);
 326     }
 327 }
 328
 329 static void
 330 i965_avc_hw_scoreboard_pipeline_setup(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
 331 {
 332     struct intel_batchbuffer *batch = i965_h264_context->batch;
 333
 334     intel_batchbuffer_start_atomic(batch, 0x1000);
 335     intel_batchbuffer_emit_mi_flush(batch);
 336     i965_avc_hw_scoreboard_pipeline_select(ctx, i965_h264_context);
 337     i965_avc_hw_scoreboard_state_base_address(ctx, i965_h264_context);
 338     i965_avc_hw_scoreboard_state_pointers(ctx, i965_h264_context);
 339     i965_avc_hw_scoreboard_urb_layout(ctx, i965_h264_context);
 340     i965_avc_hw_scoreboard_cs_urb_layout(ctx, i965_h264_context);
 341     i965_avc_hw_scoreboard_constant_buffer(ctx, i965_h264_context);
 342     i965_avc_hw_scoreboard_objects(ctx, i965_h264_context);
 343     intel_batchbuffer_end_atomic(batch);
 344 }
 345
 346 void
 347 i965_avc_hw_scoreboard(VADriverContextP ctx, struct decode_state *decode_state, void *h264_context)
 348 {
 349     struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
 350
 351     if (i965_h264_context->use_avc_hw_scoreboard) {
 352         struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 353
 354         avc_hw_scoreboard_context->inline_data.num_mb_cmds = i965_h264_context->avc_it_command_mb_info.mbs;
 355         avc_hw_scoreboard_context->inline_data.starting_mb_number = i965_h264_context->avc_it_command_mb_info.mbs;
 356         avc_hw_scoreboard_context->inline_data.pic_width_in_mbs = i965_h264_context->picture.width_in_mbs;
 357         avc_hw_scoreboard_context->surface.total_mbs = i965_h264_context->avc_it_command_mb_info.mbs * 2;
 358
 359         dri_bo_unreference(avc_hw_scoreboard_context->hw_kernel.bo);
 360         avc_hw_scoreboard_context->hw_kernel.bo = i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo;
 361         assert(avc_hw_scoreboard_context->hw_kernel.bo != NULL);
 362         dri_bo_reference(avc_hw_scoreboard_context->hw_kernel.bo);
 363
 364         if (i965_h264_context->picture.mbaff_frame_flag)
 365             avc_hw_scoreboard_context->hw_kernel.offset = avc_hw_scoreboard_kernel_offset[AVC_HW_SCOREBOARD_MBAFF];
 366         else
 367             avc_hw_scoreboard_context->hw_kernel.offset = avc_hw_scoreboard_kernel_offset[AVC_HW_SCOREBOARD];
 368
 369         i965_avc_hw_scoreboard_states_setup(i965_h264_context);
 370         i965_avc_hw_scoreboard_pipeline_setup(ctx, i965_h264_context);
 371     }
 372 }
 373
 374 void
 375 i965_avc_hw_scoreboard_decode_init(VADriverContextP ctx, void *h264_context)
 376 {
 377     struct i965_driver_data *i965 = i965_driver_data(ctx);
 378     struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
 379
 380     if (i965_h264_context->use_avc_hw_scoreboard) {
 381         struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context = &i965_h264_context->avc_hw_scoreboard_context;
 382         dri_bo *bo;
 383
 384         if (avc_hw_scoreboard_context->curbe.bo == NULL) {
 385             bo = dri_bo_alloc(i965->intel.bufmgr,
 386                               "constant buffer",
 387                               4096, 64);
 388             assert(bo);
 389             avc_hw_scoreboard_context->curbe.bo = bo;
 390             avc_hw_scoreboard_context->curbe.upload = 0;
 391         }
 392
 393         dri_bo_unreference(avc_hw_scoreboard_context->surface.s_bo);
 394         avc_hw_scoreboard_context->surface.s_bo = i965_h264_context->avc_it_command_mb_info.bo;
 395         assert(avc_hw_scoreboard_context->surface.s_bo != NULL);
 396         dri_bo_reference(avc_hw_scoreboard_context->surface.s_bo);
 397
 398         dri_bo_unreference(avc_hw_scoreboard_context->surface.ss_bo);
 399         bo = dri_bo_alloc(i965->intel.bufmgr,
 400                           "surface state",
 401                           sizeof(struct i965_surface_state), 32);
 402         assert(bo);
 403         avc_hw_scoreboard_context->surface.ss_bo = bo;
 404
 405         dri_bo_unreference(avc_hw_scoreboard_context->binding_table.bo);
 406         bo = dri_bo_alloc(i965->intel.bufmgr,
 407                           "binding table",
 408                           MAX_MEDIA_SURFACES * sizeof(unsigned int), 32);
 409         assert(bo);
 410         avc_hw_scoreboard_context->binding_table.bo = bo;
 411
 412         dri_bo_unreference(avc_hw_scoreboard_context->idrt.bo);
 413         bo = dri_bo_alloc(i965->intel.bufmgr,
 414                           "interface discriptor",
 415                           MAX_INTERFACE_DESC * sizeof(struct i965_interface_descriptor), 16);
 416         assert(bo);
 417         avc_hw_scoreboard_context->idrt.bo = bo;
 418
 419         dri_bo_unreference(avc_hw_scoreboard_context->vfe_state.bo);
 420         bo = dri_bo_alloc(i965->intel.bufmgr,
 421                           "vfe state",
 422                           sizeof(struct i965_vfe_state), 32);
 423         assert(bo);
 424         avc_hw_scoreboard_context->vfe_state.bo = bo;
 425
 426         avc_hw_scoreboard_context->urb.num_vfe_entries = 32;
 427         avc_hw_scoreboard_context->urb.size_vfe_entry = 2;
 428         avc_hw_scoreboard_context->urb.num_cs_entries = 1;
 429         avc_hw_scoreboard_context->urb.size_cs_entry = 1;
 430         avc_hw_scoreboard_context->urb.vfe_start = 0;
 431         avc_hw_scoreboard_context->urb.cs_start = avc_hw_scoreboard_context->urb.vfe_start +
 432             avc_hw_scoreboard_context->urb.num_vfe_entries * avc_hw_scoreboard_context->urb.size_vfe_entry;
 433         assert(avc_hw_scoreboard_context->urb.cs_start +
 434                avc_hw_scoreboard_context->urb.num_cs_entries * avc_hw_scoreboard_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
 435     }
 436 }
 437
 438 Bool
 439 i965_avc_hw_scoreboard_ternimate(struct i965_avc_hw_scoreboard_context *avc_hw_scoreboard_context)
 440 {
 441     dri_bo_unreference(avc_hw_scoreboard_context->curbe.bo);
 442     avc_hw_scoreboard_context->curbe.bo = NULL;
 443
 444     dri_bo_unreference(avc_hw_scoreboard_context->surface.ss_bo);
 445     avc_hw_scoreboard_context->surface.ss_bo = NULL;
 446
 447     dri_bo_unreference(avc_hw_scoreboard_context->surface.s_bo);
 448     avc_hw_scoreboard_context->surface.s_bo = NULL;
 449
 450     dri_bo_unreference(avc_hw_scoreboard_context->binding_table.bo);
 451     avc_hw_scoreboard_context->binding_table.bo = NULL;
 452
 453     dri_bo_unreference(avc_hw_scoreboard_context->idrt.bo);
 454     avc_hw_scoreboard_context->idrt.bo = NULL;
 455
 456     dri_bo_unreference(avc_hw_scoreboard_context->vfe_state.bo);
 457     avc_hw_scoreboard_context->vfe_state.bo = NULL;
 458
 459     dri_bo_unreference(avc_hw_scoreboard_context->hw_kernel.bo);
 460     avc_hw_scoreboard_context->hw_kernel.bo = NULL;
 461
 462     return True;
 463 }