2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
33 #include "va_backend.h"
35 #include "intel_batchbuffer.h"
36 #include "intel_driver.h"
38 #include "i965_defines.h"
39 #include "i965_drv_video.h"
40 #include "i965_avc_bsd.h"
41 #include "i965_media_h264.h"
42 #include "i965_media.h"
45 i965_avc_bsd_free_avc_bsd_surface(void **data)
47 struct i965_avc_bsd_surface *avc_bsd_surface = *data;
52 dri_bo_unreference(avc_bsd_surface->dmv_top);
53 avc_bsd_surface->dmv_top = NULL;
54 dri_bo_unreference(avc_bsd_surface->dmv_bottom);
55 avc_bsd_surface->dmv_bottom = NULL;
57 free(avc_bsd_surface);
62 i965_avc_bsd_init_avc_bsd_surface(VADriverContextP ctx,
63 struct object_surface *obj_surface,
64 VAPictureParameterBufferH264 *pic_param,
65 struct i965_h264_context *i965_h264_context)
67 struct i965_driver_data *i965 = i965_driver_data(ctx);
68 struct i965_avc_bsd_context *i965_avc_bsd_context = &i965_h264_context->i965_avc_bsd_context;
69 struct i965_avc_bsd_surface *avc_bsd_surface = obj_surface->private_data;
71 obj_surface->free_private_data = i965_avc_bsd_free_avc_bsd_surface;
73 if (!avc_bsd_surface) {
74 avc_bsd_surface = calloc(sizeof(struct i965_avc_bsd_surface), 1);
75 assert((obj_surface->size & 0x3f) == 0);
76 obj_surface->private_data = avc_bsd_surface;
79 avc_bsd_surface->ctx = i965_avc_bsd_context;
80 avc_bsd_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
81 !pic_param->seq_fields.bits.direct_8x8_inference_flag);
83 if (avc_bsd_surface->dmv_top == NULL) {
84 avc_bsd_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
85 "direct mv w/r buffer",
90 if (avc_bsd_surface->dmv_bottom_flag &&
91 avc_bsd_surface->dmv_bottom == NULL) {
92 avc_bsd_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
93 "direct mv w/r buffer",
100 i965_bsd_ind_obj_base_address(VADriverContextP ctx,
101 struct decode_state *decode_state,
103 struct i965_h264_context *i965_h264_context)
106 struct intel_batchbuffer *batch = i965_h264_context->batch;
108 dri_bo *ind_bo = decode_state->slice_datas[slice]->bo;
110 BEGIN_BCS_BATCH(batch, 3);
111 OUT_BCS_BATCH(batch, CMD_BSD_IND_OBJ_BASE_ADDR | (3 - 2));
112 OUT_BCS_RELOC(batch, ind_bo,
113 I915_GEM_DOMAIN_INSTRUCTION, 0,
115 OUT_BCS_BATCH(batch, 0);
116 ADVANCE_BCS_BATCH(batch);
120 i965_avc_bsd_img_state(VADriverContextP ctx,
121 struct decode_state *decode_state,
122 struct i965_h264_context *i965_h264_context)
124 struct intel_batchbuffer *batch = i965_h264_context->batch;
127 int mbaff_frame_flag;
128 unsigned int avc_it_command_header;
129 unsigned int width_in_mbs, height_in_mbs;
130 VAPictureParameterBufferH264 *pic_param;
132 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
135 qm_present_flag = 0; /* built-in QM matrices */
137 assert(decode_state->pic_param && decode_state->pic_param->buffer);
138 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
140 assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID));
142 if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
144 else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
149 if ((img_struct & 0x1) == 0x1) {
150 assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
152 assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
155 if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
156 assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
157 assert(pic_param->pic_fields.bits.field_pic_flag == 0);
159 assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
162 mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
163 !pic_param->pic_fields.bits.field_pic_flag);
165 width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
166 height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
168 assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */
170 /* BSD unit doesn't support 4:2:2 and 4:4:4 picture */
171 assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
172 pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */
173 assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
175 avc_it_command_header = (CMD_MEDIA_OBJECT_EX | (12 - 2));
177 BEGIN_BCS_BATCH(batch, 6);
178 OUT_BCS_BATCH(batch, CMD_AVC_BSD_IMG_STATE | (6 - 2));
180 ((width_in_mbs * height_in_mbs) & 0x7fff));
182 (height_in_mbs << 16) |
183 (width_in_mbs << 0));
185 ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
186 ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
187 (SCAN_RASTER_ORDER << 15) | /* AVC ILDB Data */
188 (SCAN_SPECIAL_ORDER << 14) | /* AVC IT Command */
189 (SCAN_RASTER_ORDER << 13) | /* AVC IT Data */
190 (1 << 12) | /* always 1, hardware requirement */
191 (qm_present_flag << 10) |
193 (16 << 0)); /* FIXME: always support 16 reference frames ??? */
195 (RESIDUAL_DATA_OFFSET << 24) | /* residual data offset */
196 (0 << 17) | /* don't overwrite SRT */
197 (0 << 16) | /* Un-SRT (Unsynchronized Root Thread) */
198 (0 << 12) | /* FIXME: no 16MV ??? */
199 (pic_param->seq_fields.bits.chroma_format_idc << 10) |
200 (i965_h264_context->enable_avc_ildb << 8) | /* Enable ILDB writing output */
201 (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
202 ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
203 (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
204 (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
205 (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
206 (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
207 (mbaff_frame_flag << 1) |
208 (pic_param->pic_fields.bits.field_pic_flag << 0));
209 OUT_BCS_BATCH(batch, avc_it_command_header);
210 ADVANCE_BCS_BATCH(batch);
214 i965_avc_bsd_qm_state(VADriverContextP ctx,
215 struct decode_state *decode_state,
216 struct i965_h264_context *i965_h264_context)
218 struct intel_batchbuffer *batch = i965_h264_context->batch;
220 VAIQMatrixBufferH264 *iq_matrix;
221 VAPictureParameterBufferH264 *pic_param;
223 if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
226 iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
228 assert(decode_state->pic_param && decode_state->pic_param->buffer);
229 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
231 cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */
233 if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
234 cmd_len += 2 * 16; /* load two 8x8 scaling matrices */
236 BEGIN_BCS_BATCH(batch, cmd_len);
237 OUT_BCS_BATCH(batch, CMD_AVC_BSD_QM_STATE | (cmd_len - 2));
239 if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
241 (0x0 << 8) | /* don't use default built-in matrices */
242 (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */
245 (0x0 << 8) | /* don't use default built-in matrices */
246 (0x3f << 0)); /* six 4x4 scaling matrices */
248 intel_batchbuffer_data(batch, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4);
250 if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
251 intel_batchbuffer_data(batch, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4);
253 ADVANCE_BCS_BATCH(batch);
257 i965_avc_bsd_slice_state(VADriverContextP ctx,
258 VAPictureParameterBufferH264 *pic_param,
259 VASliceParameterBufferH264 *slice_param,
260 struct i965_h264_context *i965_h264_context)
262 struct intel_batchbuffer *batch = i965_h264_context->batch;
263 int present_flag, cmd_len, list, j;
265 unsigned char bottom_idc:1;
266 unsigned char frame_store_index:4;
267 unsigned char field_picture:1;
268 unsigned char long_term:1;
269 unsigned char non_exist:1;
271 char weightoffsets[32 * 6];
273 /* don't issue SLICE_STATE for intra-prediction decoding */
274 if (slice_param->slice_type == SLICE_TYPE_I ||
275 slice_param->slice_type == SLICE_TYPE_SI)
280 if (slice_param->slice_type == SLICE_TYPE_P ||
281 slice_param->slice_type == SLICE_TYPE_SP) {
282 present_flag = PRESENT_REF_LIST0;
285 present_flag = PRESENT_REF_LIST0 | PRESENT_REF_LIST1;
289 if ((slice_param->slice_type == SLICE_TYPE_P ||
290 slice_param->slice_type == SLICE_TYPE_SP) &&
291 (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
292 present_flag |= PRESENT_WEIGHT_OFFSET_L0;
296 if ((slice_param->slice_type == SLICE_TYPE_B) &&
297 (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
298 present_flag |= PRESENT_WEIGHT_OFFSET_L0 | PRESENT_WEIGHT_OFFSET_L1;
302 BEGIN_BCS_BATCH(batch, cmd_len);
303 OUT_BCS_BATCH(batch, CMD_AVC_BSD_SLICE_STATE | (cmd_len - 2));
304 OUT_BCS_BATCH(batch, present_flag);
306 for (list = 0; list < 2; list++) {
308 VAPictureH264 *va_pic;
311 flag = PRESENT_REF_LIST0;
312 va_pic = slice_param->RefPicList0;
314 flag = PRESENT_REF_LIST1;
315 va_pic = slice_param->RefPicList1;
318 if (!(present_flag & flag))
321 for (j = 0; j < 32; j++) {
322 if (va_pic->flags & VA_PICTURE_H264_INVALID) {
323 refs[j].non_exist = 1;
324 refs[j].long_term = 1;
325 refs[j].field_picture = 1;
326 refs[j].frame_store_index = 0xf;
327 refs[j].bottom_idc = 1;
331 for (frame_idx = 0; frame_idx < ARRAY_ELEMS(i965_h264_context->fsid_list); frame_idx++) {
332 if (i965_h264_context->fsid_list[frame_idx].surface_id != VA_INVALID_ID &&
333 va_pic->picture_id == i965_h264_context->fsid_list[frame_idx].surface_id) {
334 assert(frame_idx == i965_h264_context->fsid_list[frame_idx].frame_store_id);
339 assert(frame_idx < ARRAY_ELEMS(i965_h264_context->fsid_list));
341 refs[j].non_exist = 0;
342 refs[j].long_term = !!(va_pic->flags & VA_PICTURE_H264_LONG_TERM_REFERENCE);
343 refs[j].field_picture = !!(va_pic->flags &
344 (VA_PICTURE_H264_TOP_FIELD |
345 VA_PICTURE_H264_BOTTOM_FIELD));
346 refs[j].frame_store_index = frame_idx;
347 refs[j].bottom_idc = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
353 intel_batchbuffer_data(batch, refs, sizeof(refs));
356 i965_h264_context->weight128_luma_l0 = 0;
357 i965_h264_context->weight128_luma_l1 = 0;
358 i965_h264_context->weight128_chroma_l0 = 0;
359 i965_h264_context->weight128_chroma_l1 = 0;
361 i965_h264_context->weight128_offset0_flag = 0;
362 i965_h264_context->weight128_offset0 = 0;
364 if (present_flag & PRESENT_WEIGHT_OFFSET_L0) {
365 for (j = 0; j < 32; j++) {
366 weightoffsets[j * 6 + 0] = slice_param->luma_offset_l0[j];
367 weightoffsets[j * 6 + 1] = slice_param->luma_weight_l0[j];
368 weightoffsets[j * 6 + 2] = slice_param->chroma_offset_l0[j][0];
369 weightoffsets[j * 6 + 3] = slice_param->chroma_weight_l0[j][0];
370 weightoffsets[j * 6 + 4] = slice_param->chroma_offset_l0[j][1];
371 weightoffsets[j * 6 + 5] = slice_param->chroma_weight_l0[j][1];
373 if (pic_param->pic_fields.bits.weighted_pred_flag == 1 ||
374 pic_param->pic_fields.bits.weighted_bipred_idc == 1) {
375 if (i965_h264_context->use_hw_w128) {
376 if (slice_param->luma_weight_l0[j] == 128)
377 i965_h264_context->weight128_luma_l0 |= (1 << j);
379 if (slice_param->chroma_weight_l0[j][0] == 128 ||
380 slice_param->chroma_weight_l0[j][1] == 128)
381 i965_h264_context->weight128_chroma_l0 |= (1 << j);
383 /* FIXME: workaround for weight 128 */
384 if (slice_param->luma_weight_l0[j] == 128 ||
385 slice_param->chroma_weight_l0[j][0] == 128 ||
386 slice_param->chroma_weight_l0[j][1] == 128)
387 i965_h264_context->weight128_offset0_flag = 1;
392 intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
395 if (present_flag & PRESENT_WEIGHT_OFFSET_L1) {
396 for (j = 0; j < 32; j++) {
397 weightoffsets[j * 6 + 0] = slice_param->luma_offset_l1[j];
398 weightoffsets[j * 6 + 1] = slice_param->luma_weight_l1[j];
399 weightoffsets[j * 6 + 2] = slice_param->chroma_offset_l1[j][0];
400 weightoffsets[j * 6 + 3] = slice_param->chroma_weight_l1[j][0];
401 weightoffsets[j * 6 + 4] = slice_param->chroma_offset_l1[j][1];
402 weightoffsets[j * 6 + 5] = slice_param->chroma_weight_l1[j][1];
404 if (pic_param->pic_fields.bits.weighted_bipred_idc == 1) {
405 if (i965_h264_context->use_hw_w128) {
406 if (slice_param->luma_weight_l1[j] == 128)
407 i965_h264_context->weight128_luma_l1 |= (1 << j);
409 if (slice_param->chroma_weight_l1[j][0] == 128 ||
410 slice_param->chroma_weight_l1[j][1] == 128)
411 i965_h264_context->weight128_chroma_l1 |= (1 << j);
413 if (slice_param->luma_weight_l0[j] == 128 ||
414 slice_param->chroma_weight_l0[j][0] == 128 ||
415 slice_param->chroma_weight_l0[j][1] == 128)
416 i965_h264_context->weight128_offset0_flag = 1;
421 intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
424 ADVANCE_BCS_BATCH(batch);
428 i965_avc_bsd_buf_base_state(VADriverContextP ctx,
429 VAPictureParameterBufferH264 *pic_param,
430 VASliceParameterBufferH264 *slice_param,
431 struct i965_h264_context *i965_h264_context)
433 struct i965_driver_data *i965 = i965_driver_data(ctx);
434 struct intel_batchbuffer *batch = i965_h264_context->batch;
435 struct i965_avc_bsd_context *i965_avc_bsd_context;
437 VAPictureH264 *va_pic;
438 struct object_surface *obj_surface;
439 struct i965_avc_bsd_surface *avc_bsd_surface;
441 i965_avc_bsd_context = &i965_h264_context->i965_avc_bsd_context;
443 BEGIN_BCS_BATCH(batch, 74);
444 OUT_BCS_BATCH(batch, CMD_AVC_BSD_BUF_BASE_STATE | (74 - 2));
445 OUT_BCS_RELOC(batch, i965_avc_bsd_context->bsd_raw_store.bo,
446 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
448 OUT_BCS_RELOC(batch, i965_avc_bsd_context->mpr_row_store.bo,
449 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
451 OUT_BCS_RELOC(batch, i965_h264_context->avc_it_command_mb_info.bo,
452 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
453 i965_h264_context->avc_it_command_mb_info.mbs * i965_h264_context->use_avc_hw_scoreboard * MB_CMD_IN_BYTES);
454 OUT_BCS_RELOC(batch, i965_h264_context->avc_it_data.bo,
455 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
456 (i965_h264_context->avc_it_data.write_offset << 6));
458 if (i965_h264_context->enable_avc_ildb)
459 OUT_BCS_RELOC(batch, i965_h264_context->avc_ildb_data.bo,
460 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
463 OUT_BCS_BATCH(batch, 0);
465 for (i = 0; i < ARRAY_ELEMS(i965_h264_context->fsid_list); i++) {
466 if (i965_h264_context->fsid_list[i].surface_id != VA_INVALID_ID) {
468 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
469 va_pic = &pic_param->ReferenceFrames[j];
471 if (va_pic->flags & VA_PICTURE_H264_INVALID)
474 if (va_pic->picture_id == i965_h264_context->fsid_list[i].surface_id) {
482 if (!(va_pic->flags & VA_PICTURE_H264_INVALID)) {
483 obj_surface = SURFACE(va_pic->picture_id);
485 avc_bsd_surface = obj_surface->private_data;
487 if (avc_bsd_surface == NULL) {
488 OUT_BCS_BATCH(batch, 0);
489 OUT_BCS_BATCH(batch, 0);
491 OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_top,
492 I915_GEM_DOMAIN_INSTRUCTION, 0,
495 if (avc_bsd_surface->dmv_bottom_flag == 1)
496 OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_bottom,
497 I915_GEM_DOMAIN_INSTRUCTION, 0,
500 OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_top,
501 I915_GEM_DOMAIN_INSTRUCTION, 0,
506 OUT_BCS_BATCH(batch, 0);
507 OUT_BCS_BATCH(batch, 0);
511 va_pic = &pic_param->CurrPic;
512 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
513 obj_surface = SURFACE(va_pic->picture_id);
515 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
516 obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
517 i965_avc_bsd_init_avc_bsd_surface(ctx, obj_surface, pic_param, i965_h264_context);
518 avc_bsd_surface = obj_surface->private_data;
519 i965_check_alloc_surface_bo(ctx, obj_surface, 0);
521 OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_top,
522 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
525 if (avc_bsd_surface->dmv_bottom_flag == 1)
526 OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_bottom,
527 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
530 OUT_BCS_RELOC(batch, avc_bsd_surface->dmv_top,
531 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
535 for (i = 0; i < ARRAY_ELEMS(i965_h264_context->fsid_list); i++) {
536 if (i965_h264_context->fsid_list[i].surface_id != VA_INVALID_ID) {
538 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
539 va_pic = &pic_param->ReferenceFrames[j];
541 if (va_pic->flags & VA_PICTURE_H264_INVALID)
544 if (va_pic->picture_id == i965_h264_context->fsid_list[i].surface_id) {
552 if (!(va_pic->flags & VA_PICTURE_H264_INVALID)) {
553 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
554 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
557 OUT_BCS_BATCH(batch, 0);
558 OUT_BCS_BATCH(batch, 0);
562 va_pic = &pic_param->CurrPic;
563 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
564 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
566 ADVANCE_BCS_BATCH(batch);
570 * Return the bit offset to the first bit of the slice data
572 * VASliceParameterBufferH264.slice_data_bit_offset will point into the part
573 * of slice header if there are some escaped bytes in the slice header. The offset
574 * to slice data is needed for BSD unit so that BSD unit can fetch right slice data
575 * for processing. This fixes conformance case BASQP1_Sony_C.jsv
578 i965_avc_bsd_get_slice_bit_offset(uint8_t *buf, int mode_flag, int in_slice_data_bit_offset)
580 int out_slice_data_bit_offset;
581 int slice_header_size = in_slice_data_bit_offset / 8;
584 for (i = 0, j = 0; i < slice_header_size; i++, j++) {
585 if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3) {
590 out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
592 if (mode_flag == ENTROPY_CABAC)
593 out_slice_data_bit_offset = ALIGN(out_slice_data_bit_offset, 0x8);
595 return out_slice_data_bit_offset;
599 g4x_avc_bsd_object(VADriverContextP ctx,
600 struct decode_state *decode_state,
601 VAPictureParameterBufferH264 *pic_param,
602 VASliceParameterBufferH264 *slice_param,
604 struct i965_h264_context *i965_h264_context)
606 struct intel_batchbuffer *batch = i965_h264_context->batch;
607 int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
608 int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
611 int encrypted, counter_value, cmd_len;
612 int slice_hor_pos, slice_ver_pos;
613 int num_ref_idx_l0, num_ref_idx_l1;
614 int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
615 pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
616 int slice_data_bit_offset;
617 int weighted_pred_idc = 0;
618 int first_mb_in_slice = 0;
620 uint8_t *slice_data = NULL;
622 encrypted = 0; /* FIXME: which flag in VAAPI is used for encryption? */
626 counter_value = 0; /* FIXME: ??? */
630 dri_bo_map(decode_state->slice_datas[slice_index]->bo, 0);
631 slice_data = (uint8_t *)(decode_state->slice_datas[slice_index]->bo->virtual + slice_param->slice_data_offset);
632 slice_data_bit_offset = i965_avc_bsd_get_slice_bit_offset(slice_data,
633 pic_param->pic_fields.bits.entropy_coding_mode_flag,
634 slice_param->slice_data_bit_offset);
635 dri_bo_unmap(decode_state->slice_datas[slice_index]->bo);
637 if (slice_param->slice_type == SLICE_TYPE_I ||
638 slice_param->slice_type == SLICE_TYPE_SI)
639 slice_type = SLICE_TYPE_I;
640 else if (slice_param->slice_type == SLICE_TYPE_P ||
641 slice_param->slice_type == SLICE_TYPE_SP)
642 slice_type = SLICE_TYPE_P;
644 assert(slice_param->slice_type == SLICE_TYPE_B);
645 slice_type = SLICE_TYPE_B;
648 if (slice_type == SLICE_TYPE_I) {
649 assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
650 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
653 } else if (slice_type == SLICE_TYPE_P) {
654 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
655 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
658 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
659 num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
662 if (slice_type == SLICE_TYPE_P)
663 weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
664 else if (slice_type == SLICE_TYPE_B)
665 weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
667 first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
668 slice_hor_pos = first_mb_in_slice % width_in_mbs;
669 slice_ver_pos = first_mb_in_slice / width_in_mbs;
671 BEGIN_BCS_BATCH(batch, cmd_len);
672 OUT_BCS_BATCH(batch, CMD_AVC_BSD_OBJECT | (cmd_len - 2));
675 ((slice_param->slice_data_size - (slice_data_bit_offset >> 3)) << 0));
677 (slice_param->slice_data_offset +
678 (slice_data_bit_offset >> 3)));
680 (0 << 31) | /* concealment mode: 0->intra 16x16 prediction, 1->inter P Copy */
681 (0 << 14) | /* ignore BSDPrematureComplete Error handling */
682 (0 << 13) | /* FIXME: ??? */
683 (0 << 12) | /* ignore MPR Error handling */
684 (0 << 10) | /* ignore Entropy Error handling */
685 (0 << 8) | /* ignore MB Header Error handling */
688 (num_ref_idx_l1 << 24) |
689 (num_ref_idx_l0 << 16) |
690 (slice_param->chroma_log2_weight_denom << 8) |
691 (slice_param->luma_log2_weight_denom << 0));
693 (weighted_pred_idc << 30) |
694 (slice_param->direct_spatial_mv_pred_flag << 29) |
695 (slice_param->disable_deblocking_filter_idc << 27) |
696 (slice_param->cabac_init_idc << 24) |
697 ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
698 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
699 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
701 (slice_ver_pos << 24) |
702 (slice_hor_pos << 16) |
703 (first_mb_in_slice << 0));
705 (0 << 7) | /* FIXME: ??? */
706 ((0x7 - (slice_data_bit_offset & 0x7)) << 0));
709 OUT_BCS_BATCH(batch, counter_value);
712 ADVANCE_BCS_BATCH(batch);
714 BEGIN_BCS_BATCH(batch, 8);
715 OUT_BCS_BATCH(batch, CMD_AVC_BSD_OBJECT | (8 - 2));
716 OUT_BCS_BATCH(batch, 0); /* indirect data length for phantom slice is 0 */
717 OUT_BCS_BATCH(batch, 0); /* indirect data start address for phantom slice is 0 */
718 OUT_BCS_BATCH(batch, 0);
719 OUT_BCS_BATCH(batch, 0);
720 OUT_BCS_BATCH(batch, 0);
721 OUT_BCS_BATCH(batch, width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag));
722 OUT_BCS_BATCH(batch, 0);
723 ADVANCE_BCS_BATCH(batch);
728 ironlake_avc_bsd_object(VADriverContextP ctx,
729 struct decode_state *decode_state,
730 VAPictureParameterBufferH264 *pic_param,
731 VASliceParameterBufferH264 *slice_param,
733 struct i965_h264_context *i965_h264_context)
735 struct intel_batchbuffer *batch = i965_h264_context->batch;
736 int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
737 int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
740 int encrypted, counter_value;
741 int slice_hor_pos, slice_ver_pos;
742 int num_ref_idx_l0, num_ref_idx_l1;
743 int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
744 pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
745 int slice_data_bit_offset;
746 int weighted_pred_idc = 0;
747 int first_mb_in_slice;
749 uint8_t *slice_data = NULL;
751 encrypted = 0; /* FIXME: which flag in VAAPI is used for encryption? */
754 counter_value = 0; /* FIXME: ??? */
758 dri_bo_map(decode_state->slice_datas[slice_index]->bo, 0);
759 slice_data = (uint8_t *)(decode_state->slice_datas[slice_index]->bo->virtual + slice_param->slice_data_offset);
760 slice_data_bit_offset = i965_avc_bsd_get_slice_bit_offset(slice_data,
761 pic_param->pic_fields.bits.entropy_coding_mode_flag,
762 slice_param->slice_data_bit_offset);
763 dri_bo_unmap(decode_state->slice_datas[slice_index]->bo);
765 if (slice_param->slice_type == SLICE_TYPE_I ||
766 slice_param->slice_type == SLICE_TYPE_SI)
767 slice_type = SLICE_TYPE_I;
768 else if (slice_param->slice_type == SLICE_TYPE_P ||
769 slice_param->slice_type == SLICE_TYPE_SP)
770 slice_type = SLICE_TYPE_P;
772 assert(slice_param->slice_type == SLICE_TYPE_B);
773 slice_type = SLICE_TYPE_B;
776 if (slice_type == SLICE_TYPE_I) {
777 assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
778 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
781 } else if (slice_type == SLICE_TYPE_P) {
782 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
783 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
786 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
787 num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
790 if (slice_type == SLICE_TYPE_P)
791 weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
792 else if (slice_type == SLICE_TYPE_B)
793 weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
795 first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
796 slice_hor_pos = first_mb_in_slice % width_in_mbs;
797 slice_ver_pos = first_mb_in_slice / width_in_mbs;
799 BEGIN_BCS_BATCH(batch, 16);
800 OUT_BCS_BATCH(batch, CMD_AVC_BSD_OBJECT | (16 - 2));
803 (0 << 30) | /* FIXME: packet based bit stream */
804 (0 << 29) | /* FIXME: packet format */
805 ((slice_param->slice_data_size - (slice_data_bit_offset >> 3)) << 0));
807 (slice_param->slice_data_offset +
808 (slice_data_bit_offset >> 3)));
810 (0 << 31) | /* concealment mode: 0->intra 16x16 prediction, 1->inter P Copy */
811 (0 << 14) | /* ignore BSDPrematureComplete Error handling */
812 (0 << 13) | /* FIXME: ??? */
813 (0 << 12) | /* ignore MPR Error handling */
814 (0 << 10) | /* ignore Entropy Error handling */
815 (0 << 8) | /* ignore MB Header Error handling */
818 (num_ref_idx_l1 << 24) |
819 (num_ref_idx_l0 << 16) |
820 (slice_param->chroma_log2_weight_denom << 8) |
821 (slice_param->luma_log2_weight_denom << 0));
823 (weighted_pred_idc << 30) |
824 (slice_param->direct_spatial_mv_pred_flag << 29) |
825 (slice_param->disable_deblocking_filter_idc << 27) |
826 (slice_param->cabac_init_idc << 24) |
827 ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
828 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
829 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
831 (slice_ver_pos << 24) |
832 (slice_hor_pos << 16) |
833 (first_mb_in_slice << 0));
835 (0 << 7) | /* FIXME: ??? */
836 ((0x7 - (slice_data_bit_offset & 0x7)) << 0));
837 OUT_BCS_BATCH(batch, counter_value);
839 /* FIXME: dw9-dw11 */
840 OUT_BCS_BATCH(batch, 0);
841 OUT_BCS_BATCH(batch, 0);
842 OUT_BCS_BATCH(batch, 0);
843 OUT_BCS_BATCH(batch, i965_h264_context->weight128_luma_l0);
844 OUT_BCS_BATCH(batch, i965_h264_context->weight128_luma_l1);
845 OUT_BCS_BATCH(batch, i965_h264_context->weight128_chroma_l0);
846 OUT_BCS_BATCH(batch, i965_h264_context->weight128_chroma_l1);
848 ADVANCE_BCS_BATCH(batch);
850 BEGIN_BCS_BATCH(batch, 16);
851 OUT_BCS_BATCH(batch, CMD_AVC_BSD_OBJECT | (16 - 2));
852 OUT_BCS_BATCH(batch, 0); /* indirect data length for phantom slice is 0 */
853 OUT_BCS_BATCH(batch, 0); /* indirect data start address for phantom slice is 0 */
854 OUT_BCS_BATCH(batch, 0);
855 OUT_BCS_BATCH(batch, 0);
856 OUT_BCS_BATCH(batch, 0);
857 OUT_BCS_BATCH(batch, width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag));
858 OUT_BCS_BATCH(batch, 0);
859 OUT_BCS_BATCH(batch, 0);
860 OUT_BCS_BATCH(batch, 0);
861 OUT_BCS_BATCH(batch, 0);
862 OUT_BCS_BATCH(batch, 0);
863 OUT_BCS_BATCH(batch, 0);
864 OUT_BCS_BATCH(batch, 0);
865 OUT_BCS_BATCH(batch, 0);
866 OUT_BCS_BATCH(batch, 0);
867 ADVANCE_BCS_BATCH(batch);
872 i965_avc_bsd_object(VADriverContextP ctx,
873 struct decode_state *decode_state,
874 VAPictureParameterBufferH264 *pic_param,
875 VASliceParameterBufferH264 *slice_param,
877 struct i965_h264_context *i965_h264_context)
879 struct i965_driver_data *i965 = i965_driver_data(ctx);
881 if (IS_IRONLAKE(i965->intel.device_id))
882 ironlake_avc_bsd_object(ctx, decode_state, pic_param, slice_param, slice_index, i965_h264_context);
884 g4x_avc_bsd_object(ctx, decode_state, pic_param, slice_param, slice_index, i965_h264_context);
888 i965_avc_bsd_phantom_slice(VADriverContextP ctx,
889 struct decode_state *decode_state,
890 VAPictureParameterBufferH264 *pic_param,
891 struct i965_h264_context *i965_h264_context)
893 i965_avc_bsd_object(ctx, decode_state, pic_param, NULL, 0, i965_h264_context);
897 i965_avc_bsd_frame_store_index(VADriverContextP ctx,
898 VAPictureParameterBufferH264 *pic_param,
899 struct i965_h264_context *i965_h264_context)
901 struct i965_driver_data *i965 = i965_driver_data(ctx);
904 assert(ARRAY_ELEMS(i965_h264_context->fsid_list) == ARRAY_ELEMS(pic_param->ReferenceFrames));
906 for (i = 0; i < ARRAY_ELEMS(i965_h264_context->fsid_list); i++) {
909 if (i965_h264_context->fsid_list[i].surface_id == VA_INVALID_ID)
912 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
913 VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[j];
914 if (ref_pic->flags & VA_PICTURE_H264_INVALID)
917 if (i965_h264_context->fsid_list[i].surface_id == ref_pic->picture_id) {
924 struct object_surface *obj_surface = SURFACE(i965_h264_context->fsid_list[i].surface_id);
925 obj_surface->flags &= ~SURFACE_REFERENCED;
927 if ((obj_surface->flags & SURFACE_ALL_MASK) == SURFACE_DISPLAYED) {
928 dri_bo_unreference(obj_surface->bo);
929 obj_surface->bo = NULL;
930 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
933 if (obj_surface->free_private_data)
934 obj_surface->free_private_data(&obj_surface->private_data);
936 i965_h264_context->fsid_list[i].surface_id = VA_INVALID_ID;
937 i965_h264_context->fsid_list[i].frame_store_id = -1;
941 for (i = 0; i < ARRAY_ELEMS(pic_param->ReferenceFrames); i++) {
942 VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[i];
945 if (ref_pic->flags & VA_PICTURE_H264_INVALID)
948 for (j = 0; j < ARRAY_ELEMS(i965_h264_context->fsid_list); j++) {
949 if (i965_h264_context->fsid_list[j].surface_id == VA_INVALID_ID)
952 if (i965_h264_context->fsid_list[j].surface_id == ref_pic->picture_id) {
960 struct object_surface *obj_surface = SURFACE(ref_pic->picture_id);
962 i965_check_alloc_surface_bo(ctx, obj_surface, 0);
964 for (frame_idx = 0; frame_idx < ARRAY_ELEMS(i965_h264_context->fsid_list); frame_idx++) {
965 for (j = 0; j < ARRAY_ELEMS(i965_h264_context->fsid_list); j++) {
966 if (i965_h264_context->fsid_list[j].surface_id == VA_INVALID_ID)
969 if (i965_h264_context->fsid_list[j].frame_store_id == frame_idx)
973 if (j == ARRAY_ELEMS(i965_h264_context->fsid_list))
977 assert(frame_idx < ARRAY_ELEMS(i965_h264_context->fsid_list));
979 for (j = 0; j < ARRAY_ELEMS(i965_h264_context->fsid_list); j++) {
980 if (i965_h264_context->fsid_list[j].surface_id == VA_INVALID_ID) {
981 i965_h264_context->fsid_list[j].surface_id = ref_pic->picture_id;
982 i965_h264_context->fsid_list[j].frame_store_id = frame_idx;
989 for (i = 0; i < ARRAY_ELEMS(i965_h264_context->fsid_list) - 1; i++) {
990 if (i965_h264_context->fsid_list[i].surface_id != VA_INVALID_ID &&
991 i965_h264_context->fsid_list[i].frame_store_id == i)
994 for (j = i + 1; j < ARRAY_ELEMS(i965_h264_context->fsid_list); j++) {
995 if (i965_h264_context->fsid_list[j].surface_id != VA_INVALID_ID &&
996 i965_h264_context->fsid_list[j].frame_store_id == i) {
997 VASurfaceID id = i965_h264_context->fsid_list[i].surface_id;
998 int frame_idx = i965_h264_context->fsid_list[i].frame_store_id;
1000 i965_h264_context->fsid_list[i].surface_id = i965_h264_context->fsid_list[j].surface_id;
1001 i965_h264_context->fsid_list[i].frame_store_id = i965_h264_context->fsid_list[j].frame_store_id;
1002 i965_h264_context->fsid_list[j].surface_id = id;
1003 i965_h264_context->fsid_list[j].frame_store_id = frame_idx;
1011 i965_avc_bsd_pipeline(VADriverContextP ctx, struct decode_state *decode_state, void *h264_context)
1013 struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
1014 struct intel_batchbuffer *batch = i965_h264_context->batch;
1015 VAPictureParameterBufferH264 *pic_param;
1016 VASliceParameterBufferH264 *slice_param;
1019 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1020 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1021 i965_avc_bsd_frame_store_index(ctx, pic_param, i965_h264_context);
1023 i965_h264_context->enable_avc_ildb = 0;
1024 i965_h264_context->picture.i_flag = 1;
1026 for (j = 0; j < decode_state->num_slice_params && i965_h264_context->enable_avc_ildb == 0; j++) {
1027 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1028 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1030 assert(decode_state->slice_params[j]->num_elements == 1); /* FIXME */
1031 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1032 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1033 assert((slice_param->slice_type == SLICE_TYPE_I) ||
1034 (slice_param->slice_type == SLICE_TYPE_SI) ||
1035 (slice_param->slice_type == SLICE_TYPE_P) ||
1036 (slice_param->slice_type == SLICE_TYPE_SP) ||
1037 (slice_param->slice_type == SLICE_TYPE_B));
1039 if (slice_param->disable_deblocking_filter_idc != 1) {
1040 i965_h264_context->enable_avc_ildb = 1;
1048 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1050 i965_avc_bsd_img_state(ctx, decode_state, i965_h264_context);
1051 i965_avc_bsd_qm_state(ctx, decode_state, i965_h264_context);
1053 for (j = 0; j < decode_state->num_slice_params; j++) {
1054 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1055 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1057 i965_bsd_ind_obj_base_address(ctx, decode_state, j, i965_h264_context);
1059 assert(decode_state->slice_params[j]->num_elements == 1); /* FIXME */
1060 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1061 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1062 assert((slice_param->slice_type == SLICE_TYPE_I) ||
1063 (slice_param->slice_type == SLICE_TYPE_SI) ||
1064 (slice_param->slice_type == SLICE_TYPE_P) ||
1065 (slice_param->slice_type == SLICE_TYPE_SP) ||
1066 (slice_param->slice_type == SLICE_TYPE_B));
1068 if (i965_h264_context->picture.i_flag &&
1069 (slice_param->slice_type != SLICE_TYPE_I ||
1070 slice_param->slice_type != SLICE_TYPE_SI))
1071 i965_h264_context->picture.i_flag = 0;
1073 i965_avc_bsd_slice_state(ctx, pic_param, slice_param, i965_h264_context);
1074 i965_avc_bsd_buf_base_state(ctx, pic_param, slice_param, i965_h264_context);
1075 i965_avc_bsd_object(ctx, decode_state, pic_param, slice_param, j, i965_h264_context);
1080 i965_avc_bsd_phantom_slice(ctx, decode_state, pic_param, i965_h264_context);
1081 intel_batchbuffer_emit_mi_flush(batch);
1082 intel_batchbuffer_end_atomic(batch);
1083 intel_batchbuffer_flush(batch);
1087 i965_avc_bsd_decode_init(VADriverContextP ctx, void *h264_context)
1089 struct i965_driver_data *i965 = i965_driver_data(ctx);
1090 struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
1091 struct i965_avc_bsd_context *i965_avc_bsd_context;
1094 assert(i965_h264_context);
1095 i965_avc_bsd_context = &i965_h264_context->i965_avc_bsd_context;
1097 dri_bo_unreference(i965_avc_bsd_context->bsd_raw_store.bo);
1098 bo = dri_bo_alloc(i965->intel.bufmgr,
1100 0x3000, /* at least 11520 bytes to support 120 MBs per row */
1103 i965_avc_bsd_context->bsd_raw_store.bo = bo;
1105 dri_bo_unreference(i965_avc_bsd_context->mpr_row_store.bo);
1106 bo = dri_bo_alloc(i965->intel.bufmgr,
1108 0x2000, /* at least 7680 bytes to support 120 MBs per row */
1111 i965_avc_bsd_context->mpr_row_store.bo = bo;
1115 i965_avc_bsd_ternimate(struct i965_avc_bsd_context *i965_avc_bsd_context)
1117 dri_bo_unreference(i965_avc_bsd_context->bsd_raw_store.bo);
1118 dri_bo_unreference(i965_avc_bsd_context->mpr_row_store.bo);