i965_drv_video/gen6_vme.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <string.h>
  31 #include <assert.h>
  32
  33 #include <va/va_backend.h>
  34
  35 #include "intel_batchbuffer.h"
  36 #include "intel_driver.h"
  37
  38 #include "i965_defines.h"
  39 #include "i965_drv_video.h"
  40 #include "gen6_vme.h"
  41 #include "i965_encoder.h"
  42
  43 #define VME_INTRA_SHADER        0
  44 #define VME_INTER_SHADER        1
  45
  46 #define CURBE_ALLOCATION_SIZE   37              /* in 256-bit */
  47 #define CURBE_TOTAL_DATA_LENGTH (4 * 32)        /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
  48 #define CURBE_URB_ENTRY_LENGTH  4               /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
  49
  50 static const uint32_t gen6_vme_intra_frame[][4] = {
  51 #include "shaders/vme/intra_frame.g6b"
  52     {0,0,0,0}
  53 };
  54
  55 static const uint32_t gen6_vme_inter_frame[][4] = {
  56 #include "shaders/vme/inter_frame.g6b"
  57     {0,0,0,0}
  58 };
  59
  60 static struct i965_kernel gen6_vme_kernels[] = {
  61     {
  62         "VME Intra Frame",
  63         VME_INTRA_SHADER,                                                                               /*index*/
  64         gen6_vme_intra_frame,
  65         sizeof(gen6_vme_intra_frame),
  66         NULL
  67     },
  68     {
  69         "VME inter Frame",
  70         VME_INTER_SHADER,
  71         gen6_vme_inter_frame,
  72         sizeof(gen6_vme_inter_frame),
  73         NULL
  74     }
  75 };
  76
  77 static void
  78 gen6_vme_set_common_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
  79 {
  80     switch (tiling) {
  81     case I915_TILING_NONE:
  82         ss->ss3.tiled_surface = 0;
  83         ss->ss3.tile_walk = 0;
  84         break;
  85     case I915_TILING_X:
  86         ss->ss3.tiled_surface = 1;
  87         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
  88         break;
  89     case I915_TILING_Y:
  90         ss->ss3.tiled_surface = 1;
  91         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
  92         break;
  93     }
  94 }
  95
  96 static void
  97 gen6_vme_set_source_surface_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
  98 {
  99     switch (tiling) {
 100     case I915_TILING_NONE:
 101         ss->ss2.tiled_surface = 0;
 102         ss->ss2.tile_walk = 0;
 103         break;
 104     case I915_TILING_X:
 105         ss->ss2.tiled_surface = 1;
 106         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 107         break;
 108     case I915_TILING_Y:
 109         ss->ss2.tiled_surface = 1;
 110         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 111         break;
 112     }
 113 }
 114
 115 /* only used for VME source surface state */
 116 static void gen6_vme_source_surface_state(VADriverContextP ctx,
 117                                           int index,
 118                                           struct object_surface *obj_surface,
 119                                           struct gen6_encoder_context *gen6_encoder_context)
 120 {
 121     struct i965_driver_data *i965 = i965_driver_data(ctx);
 122     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 123     struct i965_surface_state2 *ss;
 124     dri_bo *bo;
 125     int w, h, w_pitch, h_pitch;
 126     unsigned int tiling, swizzle;
 127
 128     assert(obj_surface->bo);
 129     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 130
 131     w = obj_surface->orig_width;
 132     h = obj_surface->orig_height;
 133     w_pitch = obj_surface->width;
 134     h_pitch = obj_surface->height;
 135
 136     bo = dri_bo_alloc(i965->intel.bufmgr,
 137                       "VME surface state",
 138                       sizeof(struct i965_surface_state2),
 139                       0x1000);
 140     assert(bo);
 141     dri_bo_map(bo, 1);
 142     assert(bo->virtual);
 143     ss = bo->virtual;
 144     memset(ss, 0, sizeof(*ss));
 145
 146     ss->ss0.surface_base_address = obj_surface->bo->offset;
 147
 148     ss->ss1.cbcr_pixel_offset_v_direction = 2;
 149     ss->ss1.width = w - 1;
 150     ss->ss1.height = h - 1;
 151
 152     ss->ss2.surface_format = MFX_SURFACE_PLANAR_420_8;
 153     ss->ss2.interleave_chroma = 1;
 154     ss->ss2.pitch = w_pitch - 1;
 155     ss->ss2.half_pitch_for_chroma = 0;
 156
 157     gen6_vme_set_source_surface_tiling(ss, tiling);
 158
 159     /* UV offset for interleave mode */
 160     ss->ss3.x_offset_for_cb = 0;
 161     ss->ss3.y_offset_for_cb = h_pitch;
 162
 163     dri_bo_unmap(bo);
 164
 165     dri_bo_emit_reloc(bo,
 166                       I915_GEM_DOMAIN_RENDER, 0,
 167                       0,
 168                       offsetof(struct i965_surface_state2, ss0),
 169                       obj_surface->bo);
 170
 171     assert(index < MAX_MEDIA_SURFACES_GEN6);
 172     vme_context->surface_state[index].bo = bo;
 173 }
 174
 175 static void
 176 gen6_vme_media_source_surface_state(VADriverContextP ctx,
 177                                     int index,
 178                                     struct object_surface *obj_surface,
 179                                     struct gen6_encoder_context *gen6_encoder_context)
 180 {
 181     struct i965_driver_data *i965 = i965_driver_data(ctx);
 182     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 183     struct i965_surface_state *ss;
 184     dri_bo *bo;
 185     int w, h, w_pitch;
 186     unsigned int tiling, swizzle;
 187
 188     w = obj_surface->orig_width;
 189     h = obj_surface->orig_height;
 190     w_pitch = obj_surface->width;
 191
 192     /* Y plane */
 193     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 194     bo = dri_bo_alloc(i965->intel.bufmgr,
 195                       "surface state",
 196                       sizeof(struct i965_surface_state),
 197                       0x1000);
 198     assert(bo);
 199
 200     dri_bo_map(bo, True);
 201     assert(bo->virtual);
 202     ss = bo->virtual;
 203     memset(ss, 0, sizeof(*ss));
 204     ss->ss0.surface_type = I965_SURFACE_2D;
 205     ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM;
 206     ss->ss1.base_addr = obj_surface->bo->offset;
 207     ss->ss2.width = w / 4 - 1;
 208     ss->ss2.height = h - 1;
 209     ss->ss3.pitch = w_pitch - 1;
 210     gen6_vme_set_common_surface_tiling(ss, tiling);
 211     dri_bo_emit_reloc(bo,
 212                       I915_GEM_DOMAIN_RENDER,
 213                       0,
 214                       0,
 215                       offsetof(struct i965_surface_state, ss1),
 216                       obj_surface->bo);
 217     dri_bo_unmap(bo);
 218
 219     assert(index < MAX_MEDIA_SURFACES_GEN6);
 220     vme_context->surface_state[index].bo = bo;
 221 }
 222
 223 static VAStatus
 224 gen6_vme_output_buffer_setup(VADriverContextP ctx,
 225                              struct encode_state *encode_state,
 226                              int index,
 227                              struct gen6_encoder_context *gen6_encoder_context)
 228
 229 {
 230     struct i965_driver_data *i965 = i965_driver_data(ctx);
 231     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 232     struct i965_surface_state *ss;
 233     dri_bo *bo;
 234     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer;
 235     VAEncSliceParameterBuffer *pSliceParameter = (VAEncSliceParameterBuffer *)encode_state->slice_params[0]->buffer;
 236     int is_intra = pSliceParameter->slice_flags.bits.is_intra;
 237     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 238     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 239     int num_entries;
 240
 241     if ( is_intra ) {
 242         vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
 243     } else {
 244         vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs * 4;
 245     }
 246     vme_context->vme_output.size_block = 16; /* an OWORD */
 247     vme_context->vme_output.pitch = ALIGN(vme_context->vme_output.size_block, 16);
 248     bo = dri_bo_alloc(i965->intel.bufmgr,
 249                       "VME output buffer",
 250                       vme_context->vme_output.num_blocks * vme_context->vme_output.pitch,
 251                       0x1000);
 252     assert(bo);
 253     vme_context->vme_output.bo = bo;
 254
 255     bo = dri_bo_alloc(i965->intel.bufmgr,
 256                       "VME output buffer state",
 257                       sizeof(struct i965_surface_state),
 258                       0x1000);
 259     assert(bo);
 260     dri_bo_map(bo, 1);
 261     assert(bo->virtual);
 262     ss = bo->virtual;
 263     memset(ss, 0, sizeof(*ss));
 264
 265     /* always use 16 bytes as pitch on Sandy Bridge */
 266     num_entries = vme_context->vme_output.num_blocks * vme_context->vme_output.pitch / 16;
 267     ss->ss0.render_cache_read_mode = 1;
 268     ss->ss0.surface_type = I965_SURFACE_BUFFER;
 269     ss->ss1.base_addr = vme_context->vme_output.bo->offset;
 270     ss->ss2.width = ((num_entries - 1) & 0x7f);
 271     ss->ss2.height = (((num_entries - 1) >> 7) & 0x1fff);
 272     ss->ss3.depth = (((num_entries - 1) >> 20) & 0x7f);
 273     ss->ss3.pitch = vme_context->vme_output.pitch - 1;
 274     dri_bo_emit_reloc(bo,
 275                       I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 276                       0,
 277                       offsetof(struct i965_surface_state, ss1),
 278                       vme_context->vme_output.bo);
 279
 280     dri_bo_unmap(bo);
 281
 282     assert(index < MAX_MEDIA_SURFACES_GEN6);
 283     vme_context->surface_state[index].bo = bo;
 284     return VA_STATUS_SUCCESS;
 285 }
 286
 287 static VAStatus gen6_vme_surface_setup(VADriverContextP ctx,
 288                                        struct encode_state *encode_state,
 289                                        int is_intra,
 290                                        struct gen6_encoder_context *gen6_encoder_context)
 291 {
 292     struct i965_driver_data *i965 = i965_driver_data(ctx);
 293     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 294     struct object_surface *obj_surface;
 295     unsigned int *binding_table;
 296     dri_bo *bo = vme_context->binding_table.bo;
 297     int i;
 298     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param->buffer;
 299
 300     /*Setup surfaces state*/
 301     /* current picture for encoding */
 302     obj_surface = SURFACE(encode_state->current_render_target);
 303     assert(obj_surface);
 304     gen6_vme_source_surface_state(ctx, 0, obj_surface, gen6_encoder_context);
 305     gen6_vme_media_source_surface_state(ctx, 4, obj_surface, gen6_encoder_context);
 306
 307     if ( ! is_intra ) {
 308         /* reference 0 */
 309         obj_surface = SURFACE(pPicParameter->reference_picture);
 310         assert(obj_surface);
 311         gen6_vme_source_surface_state(ctx, 1, obj_surface, gen6_encoder_context);
 312         /* reference 1, FIXME: */
 313         // obj_surface = SURFACE(pPicParameter->reference_picture);
 314         // assert(obj_surface);
 315         //gen6_vme_source_surface_state(ctx, 2, obj_surface);
 316     }
 317
 318     /* VME output */
 319     gen6_vme_output_buffer_setup(ctx, encode_state, 3, gen6_encoder_context);
 320
 321     /*Building binding table*/
 322     dri_bo_map(bo, 1);
 323     assert(bo->virtual);
 324     binding_table = bo->virtual;
 325     memset(binding_table, 0, bo->size);
 326
 327     for (i = 0; i < MAX_MEDIA_SURFACES_GEN6; i++) {
 328         if (vme_context->surface_state[i].bo) {
 329             binding_table[i] = vme_context->surface_state[i].bo->offset;
 330             dri_bo_emit_reloc(bo,
 331                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 332                               0,
 333                               i * sizeof(*binding_table),
 334                               vme_context->surface_state[i].bo);
 335         }
 336     }
 337
 338     dri_bo_unmap(vme_context->binding_table.bo);
 339
 340     return VA_STATUS_SUCCESS;
 341 }
 342
 343 static VAStatus gen6_vme_interface_setup(VADriverContextP ctx,
 344                                          struct encode_state *encode_state,
 345                                          struct gen6_encoder_context *gen6_encoder_context)
 346 {
 347     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 348     struct gen6_interface_descriptor_data *desc;
 349     int i;
 350     dri_bo *bo;
 351
 352     bo = vme_context->idrt.bo;
 353     dri_bo_map(bo, 1);
 354     assert(bo->virtual);
 355     desc = bo->virtual;
 356
 357     for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
 358         struct i965_kernel *kernel;
 359         kernel = &vme_context->vme_kernels[i];
 360         assert(sizeof(*desc) == 32);
 361         /*Setup the descritor table*/
 362         memset(desc, 0, sizeof(*desc));
 363         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 364         desc->desc2.sampler_count = 1; /* FIXME: */
 365         desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5);
 366         desc->desc3.binding_table_entry_count = 1; /* FIXME: */
 367         desc->desc3.binding_table_pointer = (vme_context->binding_table.bo->offset >> 5);
 368         desc->desc4.constant_urb_entry_read_offset = 0;
 369         desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
 370
 371         /*kernel start*/
 372         dri_bo_emit_reloc(bo,
 373                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 374                           0,
 375                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 376                           kernel->bo);
 377         /*Sampler State(VME state pointer)*/
 378         dri_bo_emit_reloc(bo,
 379                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 380                           (1 << 2),                                                                     //
 381                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2),
 382                           vme_context->vme_state.bo);
 383         /*binding table*/
 384         dri_bo_emit_reloc(bo,
 385                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 386                           4,                                                                    //One Entry
 387                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc3),
 388                           vme_context->binding_table.bo);
 389         desc++;
 390     }
 391     dri_bo_unmap(bo);
 392
 393     return VA_STATUS_SUCCESS;
 394 }
 395
 396 static VAStatus gen6_vme_constant_setup(VADriverContextP ctx,
 397                                         struct encode_state *encode_state,
 398                                         struct gen6_encoder_context *gen6_encoder_context)
 399 {
 400     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 401     unsigned char *constant_buffer;
 402
 403     dri_bo_map(vme_context->curbe.bo, 1);
 404     assert(vme_context->curbe.bo->virtual);
 405     constant_buffer = vme_context->curbe.bo->virtual;
 406
 407     /*TODO copy buffer into CURB*/
 408
 409     dri_bo_unmap( vme_context->curbe.bo);
 410
 411     return VA_STATUS_SUCCESS;
 412 }
 413
 414 static VAStatus gen6_vme_vme_state_setup(VADriverContextP ctx,
 415                                          struct encode_state *encode_state,
 416                                          int is_intra,
 417                                          struct gen6_encoder_context *gen6_encoder_context)
 418 {
 419     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 420     unsigned int *vme_state_message;
 421     int i;
 422
 423     //building VME state message
 424     dri_bo_map(vme_context->vme_state.bo, 1);
 425     assert(vme_context->vme_state.bo->virtual);
 426     vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
 427
 428     for(i = 0;i < 32; i++) {
 429         vme_state_message[i] = 0x11;
 430     }
 431     vme_state_message[16] = 0x42424242;                 //cost function LUT set 0 for Intra
 432
 433     dri_bo_unmap( vme_context->vme_state.bo);
 434     return VA_STATUS_SUCCESS;
 435 }
 436
 437 static void gen6_vme_pipeline_select(VADriverContextP ctx)
 438 {
 439     BEGIN_BATCH(ctx, 1);
 440     OUT_BATCH(ctx, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 441     ADVANCE_BATCH(ctx);
 442 }
 443
 444 static void gen6_vme_state_base_address(VADriverContextP ctx)
 445 {
 446     BEGIN_BATCH(ctx, 10);
 447
 448     OUT_BATCH(ctx, CMD_STATE_BASE_ADDRESS | 8);
 449
 450     OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);                            //General State Base Address
 451     OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);                            //Surface State Base Address
 452     OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);                            //Dynamic State Base Address
 453     OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);                            //Indirect Object Base Address
 454     OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);                            //Instruction Base Address
 455
 456     OUT_BATCH(ctx, 0xFFFFF000 | BASE_ADDRESS_MODIFY);           //General State Access Upper Bound
 457     OUT_BATCH(ctx, 0xFFFFF000 | BASE_ADDRESS_MODIFY);           //Dynamic State Access Upper Bound
 458     OUT_BATCH(ctx, 0xFFFFF000 | BASE_ADDRESS_MODIFY);           //Indirect Object Access Upper Bound
 459     OUT_BATCH(ctx, 0xFFFFF000 | BASE_ADDRESS_MODIFY);           //Instruction Access Upper Bound
 460
 461     /*
 462       OUT_BATCH(ctx, 0 | BASE_ADDRESS_MODIFY);                          //LLC Coherent Base Address
 463       OUT_BATCH(ctx, 0xFFFFF000 | BASE_ADDRESS_MODIFY );                //LLC Coherent Upper Bound
 464     */
 465
 466     ADVANCE_BATCH(ctx);
 467 }
 468
 469 static void gen6_vme_vfe_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 470 {
 471     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 472
 473     BEGIN_BATCH(ctx, 8);
 474
 475     OUT_BATCH(ctx, CMD_MEDIA_VFE_STATE | 6);                                    /*Gen6 CMD_MEDIA_STATE_POINTERS = CMD_MEDIA_STATE */
 476     OUT_BATCH(ctx, 0);                                                                                          /*Scratch Space Base Pointer and Space*/
 477     OUT_BATCH(ctx, (vme_context->vfe_state.max_num_threads << 16)
 478               | (vme_context->vfe_state.num_urb_entries << 8)
 479               | (vme_context->vfe_state.gpgpu_mode << 2) );     /*Maximum Number of Threads , Number of URB Entries, MEDIA Mode*/
 480     OUT_BATCH(ctx, 0);                                                                                          /*Debug: Object ID*/
 481     OUT_BATCH(ctx, (vme_context->vfe_state.urb_entry_size << 16)
 482               | vme_context->vfe_state.curbe_allocation_size);                          /*URB Entry Allocation Size , CURBE Allocation Size*/
 483     OUT_BATCH(ctx, 0);                                                                                  /*Disable Scoreboard*/
 484     OUT_BATCH(ctx, 0);                                                                                  /*Disable Scoreboard*/
 485     OUT_BATCH(ctx, 0);                                                                                  /*Disable Scoreboard*/
 486
 487     ADVANCE_BATCH(ctx);
 488
 489 }
 490
 491 static void gen6_vme_curbe_load(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 492 {
 493     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 494
 495     BEGIN_BATCH(ctx, 4);
 496
 497     OUT_BATCH(ctx, CMD_MEDIA_CURBE_LOAD | 2);
 498     OUT_BATCH(ctx, 0);
 499
 500     OUT_BATCH(ctx, CURBE_TOTAL_DATA_LENGTH);
 501     OUT_RELOC(ctx, vme_context->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 502
 503     ADVANCE_BATCH(ctx);
 504 }
 505
 506 static void gen6_vme_idrt(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 507 {
 508     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 509
 510     BEGIN_BATCH(ctx, 4);
 511
 512     OUT_BATCH(ctx, CMD_MEDIA_INTERFACE_LOAD | 2);
 513     OUT_BATCH(ctx, 0);
 514     OUT_BATCH(ctx, GEN6_VME_KERNEL_NUMBER * sizeof(struct gen6_interface_descriptor_data));
 515     OUT_RELOC(ctx, vme_context->idrt.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 516
 517     ADVANCE_BATCH(ctx);
 518 }
 519
 520 static int gen6_vme_media_object(VADriverContextP ctx,
 521                                  struct encode_state *encode_state,
 522                                  int mb_x, int mb_y,
 523                                  int kernel)
 524 {
 525     struct i965_driver_data *i965 = i965_driver_data(ctx);
 526     struct object_surface *obj_surface = SURFACE(encode_state->current_render_target);
 527     int mb_width = ALIGN(obj_surface->orig_width, 16) / 16;
 528     int len_in_dowrds = 6 + 1;
 529
 530     BEGIN_BATCH(ctx, len_in_dowrds);
 531
 532     OUT_BATCH(ctx, CMD_MEDIA_OBJECT | (len_in_dowrds - 2));
 533     OUT_BATCH(ctx, kernel);             /*Interface Descriptor Offset*/
 534     OUT_BATCH(ctx, 0);
 535     OUT_BATCH(ctx, 0);
 536     OUT_BATCH(ctx, 0);
 537     OUT_BATCH(ctx, 0);
 538
 539     /*inline data */
 540     OUT_BATCH(ctx, mb_width << 16 | mb_y << 8 | mb_x);                  /*M0.0 Refrence0 X,Y, not used in Intra*/
 541     ADVANCE_BATCH(ctx);
 542
 543     return len_in_dowrds * 4;
 544 }
 545
 546 static void gen6_vme_media_init(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 547 {
 548     int i;
 549     struct i965_driver_data *i965 = i965_driver_data(ctx);
 550     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 551     dri_bo *bo;
 552
 553     /* constant buffer */
 554     dri_bo_unreference(vme_context->curbe.bo);
 555     bo = dri_bo_alloc(i965->intel.bufmgr,
 556                       "Buffer",
 557                       CURBE_TOTAL_DATA_LENGTH, 64);
 558     assert(bo);
 559     vme_context->curbe.bo = bo;
 560
 561     /* surface state */
 562     for (i = 0; i < MAX_MEDIA_SURFACES_GEN6; i++) {
 563         dri_bo_unreference(vme_context->surface_state[i].bo);
 564         vme_context->surface_state[i].bo = NULL;
 565     }
 566
 567     /* binding table */
 568     dri_bo_unreference(vme_context->binding_table.bo);
 569     bo = dri_bo_alloc(i965->intel.bufmgr,
 570                       "Buffer",
 571                       MAX_MEDIA_SURFACES_GEN6 * sizeof(unsigned int), 32);
 572     assert(bo);
 573     vme_context->binding_table.bo = bo;
 574
 575     /* interface descriptor remapping table */
 576     dri_bo_unreference(vme_context->idrt.bo);
 577     bo = dri_bo_alloc(i965->intel.bufmgr,
 578                       "Buffer",
 579                       MAX_INTERFACE_DESC_GEN6 * sizeof(struct gen6_interface_descriptor_data), 16);
 580     assert(bo);
 581     vme_context->idrt.bo = bo;
 582
 583     /* VME output buffer */
 584     dri_bo_unreference(vme_context->vme_output.bo);
 585     vme_context->vme_output.bo = NULL;
 586
 587     /* VME state */
 588     dri_bo_unreference(vme_context->vme_state.bo);
 589     bo = dri_bo_alloc(i965->intel.bufmgr,
 590                       "Buffer",
 591                       1024*16, 64);
 592     assert(bo);
 593     vme_context->vme_state.bo = bo;
 594
 595     vme_context->vfe_state.max_num_threads = 60 - 1;
 596     vme_context->vfe_state.num_urb_entries = 16;
 597     vme_context->vfe_state.gpgpu_mode = 0;
 598     vme_context->vfe_state.urb_entry_size = 59 - 1;
 599     vme_context->vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
 600 }
 601
 602 static void gen6_vme_pipeline_programing(VADriverContextP ctx,
 603                                          struct encode_state *encode_state,
 604                                          struct gen6_encoder_context *gen6_encoder_context)
 605 {
 606     VAEncSliceParameterBuffer *pSliceParameter = (VAEncSliceParameterBuffer *)encode_state->slice_params[0]->buffer;
 607     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer;
 608     int is_intra = pSliceParameter->slice_flags.bits.is_intra;
 609     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 610     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 611     int emit_new_state = 1, object_len_in_bytes;
 612     int x, y;
 613
 614     intel_batchbuffer_start_atomic(ctx, 0x1000);
 615
 616     for(y = 0; y < height_in_mbs; y++){
 617         for(x = 0; x < width_in_mbs; x++){
 618
 619             if (emit_new_state) {
 620                 /*Step1: MI_FLUSH/PIPE_CONTROL*/
 621                 BEGIN_BATCH(ctx, 4);
 622                 OUT_BATCH(ctx, CMD_PIPE_CONTROL | 0x02);
 623                 OUT_BATCH(ctx, 0);
 624                 OUT_BATCH(ctx, 0);
 625                 OUT_BATCH(ctx, 0);
 626                 ADVANCE_BATCH(ctx);
 627
 628                 /*Step2: State command PIPELINE_SELECT*/
 629                 gen6_vme_pipeline_select(ctx);
 630
 631                 /*Step3: State commands configuring pipeline states*/
 632                 gen6_vme_state_base_address(ctx);
 633                 gen6_vme_vfe_state(ctx, gen6_encoder_context);
 634                 gen6_vme_curbe_load(ctx, gen6_encoder_context);
 635                 gen6_vme_idrt(ctx, gen6_encoder_context);
 636
 637                 emit_new_state = 0;
 638             }
 639
 640             /*Step4: Primitive commands*/
 641             object_len_in_bytes = gen6_vme_media_object(ctx, encode_state, x, y, is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER);
 642
 643             if (intel_batchbuffer_check_free_space(ctx, object_len_in_bytes) == 0) {
 644                 intel_batchbuffer_end_atomic(ctx);
 645                 intel_batchbuffer_flush(ctx);
 646                 emit_new_state = 1;
 647                 intel_batchbuffer_start_atomic(ctx, 0x1000);
 648             }
 649         }
 650     }
 651
 652     intel_batchbuffer_end_atomic(ctx);
 653 }
 654
 655 static VAStatus gen6_vme_prepare(VADriverContextP ctx,
 656                                  struct encode_state *encode_state,
 657                                  struct gen6_encoder_context *gen6_encoder_context)
 658 {
 659     VAStatus vaStatus = VA_STATUS_SUCCESS;
 660     VAEncSliceParameterBuffer *pSliceParameter = (VAEncSliceParameterBuffer *)encode_state->slice_params[0]->buffer;
 661     int is_intra = pSliceParameter->slice_flags.bits.is_intra;
 662
 663     /*Setup all the memory object*/
 664     gen6_vme_surface_setup(ctx, encode_state, is_intra, gen6_encoder_context);
 665     gen6_vme_interface_setup(ctx, encode_state, gen6_encoder_context);
 666     gen6_vme_constant_setup(ctx, encode_state, gen6_encoder_context);
 667     gen6_vme_vme_state_setup(ctx, encode_state, is_intra, gen6_encoder_context);
 668
 669     /*Programing media pipeline*/
 670     gen6_vme_pipeline_programing(ctx, encode_state, gen6_encoder_context);
 671
 672     return vaStatus;
 673 }
 674
 675 static VAStatus gen6_vme_run(VADriverContextP ctx,
 676                              struct encode_state *encode_state,
 677                              struct gen6_encoder_context *gen6_encoder_context)
 678 {
 679     intel_batchbuffer_flush(ctx);
 680
 681     return VA_STATUS_SUCCESS;
 682 }
 683
 684 static VAStatus gen6_vme_stop(VADriverContextP ctx,
 685                               struct encode_state *encode_state,
 686                               struct gen6_encoder_context *gen6_encoder_context)
 687 {
 688     return VA_STATUS_SUCCESS;
 689 }
 690
 691 VAStatus gen6_vme_pipeline(VADriverContextP ctx,
 692                            VAProfile profile,
 693                            struct encode_state *encode_state,
 694                            struct gen6_encoder_context *gen6_encoder_context)
 695 {
 696     gen6_vme_media_init(ctx, gen6_encoder_context);
 697     gen6_vme_prepare(ctx, encode_state, gen6_encoder_context);
 698     gen6_vme_run(ctx, encode_state, gen6_encoder_context);
 699     gen6_vme_stop(ctx, encode_state, gen6_encoder_context);
 700
 701     return VA_STATUS_SUCCESS;
 702 }
 703
 704 Bool gen6_vme_context_init(VADriverContextP ctx, struct gen6_vme_context *vme_context)
 705 {
 706     struct i965_driver_data *i965 = i965_driver_data(ctx);
 707     int i;
 708
 709     memcpy(vme_context->vme_kernels, gen6_vme_kernels, sizeof(vme_context->vme_kernels));
 710
 711     for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
 712         /*Load kernel into GPU memory*/
 713         struct i965_kernel *kernel = &vme_context->vme_kernels[i];
 714
 715         kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
 716                                   kernel->name,
 717                                   kernel->size,
 718                                   0x1000);
 719         assert(kernel->bo);
 720         dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
 721     }
 722
 723     return True;
 724 }
 725
 726 Bool gen6_vme_context_destroy(struct gen6_vme_context *vme_context)
 727 {
 728     int i;
 729
 730     for (i = 0; i < MAX_MEDIA_SURFACES_GEN6; i++) {
 731         dri_bo_unreference(vme_context->surface_state[i].bo);
 732         vme_context->surface_state[i].bo = NULL;
 733     }
 734
 735     dri_bo_unreference(vme_context->idrt.bo);
 736     vme_context->idrt.bo = NULL;
 737
 738     dri_bo_unreference(vme_context->binding_table.bo);
 739     vme_context->binding_table.bo = NULL;
 740
 741     dri_bo_unreference(vme_context->curbe.bo);
 742     vme_context->curbe.bo = NULL;
 743
 744     dri_bo_unreference(vme_context->vme_output.bo);
 745     vme_context->vme_output.bo = NULL;
 746
 747     dri_bo_unreference(vme_context->vme_state.bo);
 748     vme_context->vme_state.bo = NULL;
 749
 750     for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
 751         /*Load kernel into GPU memory*/
 752         struct i965_kernel *kernel = &vme_context->vme_kernels[i];
 753
 754         dri_bo_unreference(kernel->bo);
 755         kernel->bo = NULL;
 756     }
 757
 758     return True;
 759 }