i965_drv_video/gen6_mfc.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #ifndef _GEN6_MFC_H_
  30 #define _GEN6_MFC_H_
  31
  32 #include <xf86drm.h>
  33 #include <drm.h>
  34 #include <i915_drm.h>
  35 #include <intel_bufmgr.h>
  36
  37 struct encode_state;
  38
  39 #define MAX_MFC_REFERENCE_SURFACES        16
  40 #define NUM_MFC_DMV_BUFFERS                               34
  41
  42 struct gen6_mfc_context
  43 {
  44     struct {
  45         unsigned int width;
  46         unsigned int height;
  47         unsigned int w_pitch;
  48         unsigned int h_pitch;
  49     } surface_state;
  50
  51
  52     //MFX_PIPE_BUF_ADDR_STATE
  53     struct {
  54         dri_bo *bo;
  55     } post_deblocking_output;                                   //OUTPUT: reconstructed picture
  56
  57     struct {
  58         dri_bo *bo;
  59     } pre_deblocking_output;                                    //OUTPUT: reconstructed picture with deblocked
  60
  61     struct {
  62         dri_bo *bo;
  63     } uncompressed_picture_source;                                              //INPUT: original compressed image
  64
  65     struct {
  66         dri_bo *bo;
  67     } intra_row_store_scratch_buffer;                                   //INTERNAL:
  68
  69     struct {
  70         dri_bo *bo;
  71     } deblocking_filter_row_store_scratch_buffer;               //INTERNAL:
  72
  73     struct {
  74        dri_bo *bo;
  75     } reference_surfaces[MAX_MFC_REFERENCE_SURFACES];   //INTERNAL: refrence surfaces
  76
  77     //MFX_IND_OBJ_BASE_ADDR_STATE
  78     struct{
  79         dri_bo *bo;
  80     } mfc_indirect_mv_object;                                                   //INPUT: the blocks' mv info
  81
  82     struct {
  83         dri_bo *bo;
  84         int offset;
  85     } mfc_indirect_pak_bse_object;                                              //OUTPUT: the compressed bitstream
  86
  87     //MFX_BSP_BUF_BASE_ADDR_STATE
  88     struct {
  89         dri_bo *bo;
  90     }bsd_mpc_row_store_scratch_buffer;                                  //INTERNAL:
  91
  92     //MFX_AVC_DIRECTMODE_STATE
  93     struct {
  94         dri_bo *bo;
  95     }direct_mv_buffers[NUM_MFC_DMV_BUFFERS];                            //INTERNAL:     0-31 as input,32 and 33 as output
  96 };
  97
  98 VAStatus
  99 gen6_mfc_pipeline(VADriverContextP ctx,
 100                   VAProfile profile,
 101                   struct encode_state *encode_state,
 102                   struct gen6_encoder_context *gen6_encoder_context);
 103 Bool gen6_mfc_context_init(VADriverContextP ctx, struct gen6_mfc_context *mfc_context);
 104 Bool gen6_mfc_context_destroy(struct gen6_mfc_context *mfc_context);
 105
 106 #endif  /* _GEN6_MFC_BCS_H_ */