2 * Xilinx Zynq Baseboard System emulation.
4 * Copyright (c) 2010 Xilinx.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
6 * Copyright (c) 2012 Petalogix Pty Ltd.
7 * Written by Haibing Ma
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "exec/address-spaces.h"
29 #define NUM_SPI_FLASHES 4
30 #define NUM_QSPI_FLASHES 2
31 #define NUM_QSPI_BUSSES 2
33 #define FLASH_SIZE (64 * 1024 * 1024)
34 #define FLASH_SECTOR_SIZE (128 * 1024)
36 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
38 static struct arm_boot_info zynq_binfo = {};
40 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
45 qemu_check_nic_model(nd, "cadence_gem");
46 dev = qdev_create(NULL, "cadence_gem");
47 qdev_set_nic_properties(dev, nd);
48 qdev_init_nofail(dev);
49 s = sysbus_from_qdev(dev);
50 sysbus_mmio_map(s, 0, base);
51 sysbus_connect_irq(s, 0, irq);
54 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
60 DeviceState *flash_dev;
62 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
63 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
65 dev = qdev_create(NULL, "xilinx,spips");
66 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
67 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
68 qdev_prop_set_uint8(dev, "num-busses", num_busses);
69 qdev_init_nofail(dev);
70 busdev = sysbus_from_qdev(dev);
71 sysbus_mmio_map(busdev, 0, base_addr);
73 sysbus_mmio_map(busdev, 1, 0xFC000000);
75 sysbus_connect_irq(busdev, 0, irq);
77 for (i = 0; i < num_busses; ++i) {
81 snprintf(bus_name, 16, "spi%d", i);
82 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
84 for (j = 0; j < num_ss; ++j) {
85 flash_dev = ssi_create_slave_no_init(spi, "m25p80");
86 qdev_prop_set_string(flash_dev, "partname", "n25q128");
87 qdev_init_nofail(flash_dev);
89 cs_line = qdev_get_gpio_in(flash_dev, 0);
90 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
96 static void zynq_init(QEMUMachineInitArgs *args)
98 ram_addr_t ram_size = args->ram_size;
99 const char *cpu_model = args->cpu_model;
100 const char *kernel_filename = args->kernel_filename;
101 const char *kernel_cmdline = args->kernel_cmdline;
102 const char *initrd_filename = args->initrd_filename;
104 MemoryRegion *address_space_mem = get_system_memory();
105 MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
106 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
108 SysBusDevice *busdev;
116 cpu_model = "cortex-a9";
119 cpu = cpu_arm_init(cpu_model);
121 fprintf(stderr, "Unable to find CPU definition\n");
124 irqp = arm_pic_init_cpu(cpu);
125 cpu_irq = irqp[ARM_PIC_CPU_IRQ];
128 if (ram_size > 0x80000000) {
129 ram_size = 0x80000000;
132 /* DDR remapped to address zero. */
133 memory_region_init_ram(ext_ram, "zynq.ext_ram", ram_size);
134 vmstate_register_ram_global(ext_ram);
135 memory_region_add_subregion(address_space_mem, 0, ext_ram);
137 /* 256K of on-chip memory */
138 memory_region_init_ram(ocm_ram, "zynq.ocm_ram", 256 << 10);
139 vmstate_register_ram_global(ocm_ram);
140 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
142 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
145 pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
146 dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE,
147 FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
148 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
151 dev = qdev_create(NULL, "xilinx,zynq_slcr");
152 qdev_init_nofail(dev);
153 sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xF8000000);
155 dev = qdev_create(NULL, "a9mpcore_priv");
156 qdev_prop_set_uint32(dev, "num-cpu", 1);
157 qdev_init_nofail(dev);
158 busdev = sysbus_from_qdev(dev);
159 sysbus_mmio_map(busdev, 0, 0xF8F00000);
160 sysbus_connect_irq(busdev, 0, cpu_irq);
162 for (n = 0; n < 64; n++) {
163 pic[n] = qdev_get_gpio_in(dev, n);
166 zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
167 zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
168 zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
170 sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
171 sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[75-IRQ_OFFSET]);
173 sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
174 sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
176 sysbus_create_varargs("cadence_ttc", 0xF8001000,
177 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
178 sysbus_create_varargs("cadence_ttc", 0xF8002000,
179 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
181 for (n = 0; n < nb_nics; n++) {
184 gem_init(nd, 0xE000B000, pic[54-IRQ_OFFSET]);
186 gem_init(nd, 0xE000C000, pic[77-IRQ_OFFSET]);
190 zynq_binfo.ram_size = ram_size;
191 zynq_binfo.kernel_filename = kernel_filename;
192 zynq_binfo.kernel_cmdline = kernel_cmdline;
193 zynq_binfo.initrd_filename = initrd_filename;
194 zynq_binfo.nb_cpus = 1;
195 zynq_binfo.board_id = 0xd32;
196 zynq_binfo.loader_start = 0;
197 arm_load_kernel(arm_env_get_cpu(first_cpu), &zynq_binfo);
200 static QEMUMachine zynq_machine = {
201 .name = "xilinx-zynq-a9",
202 .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
204 .block_default_type = IF_SCSI,
209 static void zynq_machine_init(void)
211 qemu_register_machine(&zynq_machine);
214 machine_init(zynq_machine_init);