2 * QEMU model of Xilinx AXI-Ethernet.
4 * Copyright (c) 2011 Edgar E. Iglesias.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu-char.h"
29 #include "net/checksum.h"
35 /* Advertisement control register. */
36 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
37 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
38 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
39 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
46 unsigned int (*read)(struct PHY *phy, unsigned int req);
47 void (*write)(struct PHY *phy, unsigned int req,
51 static unsigned int tdk_read(struct PHY *phy, unsigned int req)
64 /* Speeds and modes. */
65 r |= (1 << 13) | (1 << 14);
66 r |= (1 << 11) | (1 << 12);
67 r |= (1 << 5); /* Autoneg complete. */
68 r |= (1 << 3); /* Autoneg able. */
69 r |= (1 << 2); /* link. */
70 r |= (1 << 1); /* link. */
73 /* Link partner ability.
74 We are kind; always agree with whatever best mode
75 the guest advertises. */
76 r = 1 << 14; /* Success. */
77 /* Copy advertised modes. */
78 r |= phy->regs[4] & (15 << 5);
79 /* Autoneg support. */
83 /* Marvel PHY on many xilinx boards. */
84 r = 0x8000; /* 1000Mb */
88 /* Diagnostics reg. */
96 /* Are we advertising 100 half or 100 duplex ? */
97 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
98 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
100 /* Are we advertising 10 duplex or 100 duplex ? */
101 duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
102 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
103 r = (speed_100 << 10) | (duplex << 11);
108 r = phy->regs[regnum];
111 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
116 tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
121 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
124 phy->regs[regnum] = data;
130 tdk_init(struct PHY *phy)
132 phy->regs[0] = 0x3100;
134 phy->regs[2] = 0x0300;
135 phy->regs[3] = 0xe400;
136 /* Autonegotiation advertisement reg. */
137 phy->regs[4] = 0x01E1;
140 phy->read = tdk_read;
141 phy->write = tdk_write;
167 struct PHY *devs[32];
171 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
173 bus->devs[addr & 0x1f] = phy;
176 #ifdef USE_THIS_DEAD_CODE
178 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
180 bus->devs[addr & 0x1f] = NULL;
184 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr,
190 phy = bus->devs[addr];
191 if (phy && phy->read) {
192 data = phy->read(phy, reg);
196 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
200 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr,
201 unsigned int reg, uint16_t data)
205 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
206 phy = bus->devs[addr];
207 if (phy && phy->write) {
208 phy->write(phy, reg, data);
214 #define R_RAF (0x000 / 4)
216 RAF_MCAST_REJ = (1 << 1),
217 RAF_BCAST_REJ = (1 << 2),
218 RAF_EMCF_EN = (1 << 12),
219 RAF_NEWFUNC_EN = (1 << 11)
222 #define R_IS (0x00C / 4)
224 IS_HARD_ACCESS_COMPLETE = 1,
225 IS_AUTONEG = (1 << 1),
226 IS_RX_COMPLETE = (1 << 2),
227 IS_RX_REJECT = (1 << 3),
228 IS_TX_COMPLETE = (1 << 5),
229 IS_RX_DCM_LOCK = (1 << 6),
230 IS_MGM_RDY = (1 << 7),
231 IS_PHY_RST_DONE = (1 << 8),
234 #define R_IP (0x010 / 4)
235 #define R_IE (0x014 / 4)
236 #define R_UAWL (0x020 / 4)
237 #define R_UAWU (0x024 / 4)
238 #define R_PPST (0x030 / 4)
240 PPST_LINKSTATUS = (1 << 0),
241 PPST_PHY_LINKSTATUS = (1 << 7),
244 #define R_STATS_RX_BYTESL (0x200 / 4)
245 #define R_STATS_RX_BYTESH (0x204 / 4)
246 #define R_STATS_TX_BYTESL (0x208 / 4)
247 #define R_STATS_TX_BYTESH (0x20C / 4)
248 #define R_STATS_RXL (0x290 / 4)
249 #define R_STATS_RXH (0x294 / 4)
250 #define R_STATS_RX_BCASTL (0x2a0 / 4)
251 #define R_STATS_RX_BCASTH (0x2a4 / 4)
252 #define R_STATS_RX_MCASTL (0x2a8 / 4)
253 #define R_STATS_RX_MCASTH (0x2ac / 4)
255 #define R_RCW0 (0x400 / 4)
256 #define R_RCW1 (0x404 / 4)
258 RCW1_VLAN = (1 << 27),
260 RCW1_FCS = (1 << 29),
261 RCW1_JUM = (1 << 30),
262 RCW1_RST = (1 << 31),
265 #define R_TC (0x408 / 4)
274 #define R_EMMC (0x410 / 4)
276 EMMC_LINKSPEED_10MB = (0 << 30),
277 EMMC_LINKSPEED_100MB = (1 << 30),
278 EMMC_LINKSPEED_1000MB = (2 << 30),
281 #define R_PHYC (0x414 / 4)
283 #define R_MC (0x500 / 4)
284 #define MC_EN (1 << 6)
286 #define R_MCR (0x504 / 4)
287 #define R_MWD (0x508 / 4)
288 #define R_MRD (0x50c / 4)
289 #define R_MIS (0x600 / 4)
290 #define R_MIP (0x620 / 4)
291 #define R_MIE (0x640 / 4)
292 #define R_MIC (0x640 / 4)
294 #define R_UAW0 (0x700 / 4)
295 #define R_UAW1 (0x704 / 4)
296 #define R_FMI (0x708 / 4)
297 #define R_AF0 (0x710 / 4)
298 #define R_AF1 (0x714 / 4)
299 #define R_MAX (0x34 / 4)
301 /* Indirect registers. */
303 struct MDIOBus mdio_bus;
309 struct XilinxAXIEnet {
344 /* Receive configuration words. */
346 /* Transmit config. */
351 /* Unicast Address Word. */
353 /* Unicast address filter used with extended mcast. */
357 uint32_t regs[R_MAX];
359 /* Multicast filter addrs. */
360 uint32_t maddr[4][2];
361 /* 32K x 1 lookup filter. */
362 uint32_t ext_mtable[1024];
368 static void axienet_rx_reset(struct XilinxAXIEnet *s)
370 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
373 static void axienet_tx_reset(struct XilinxAXIEnet *s)
375 s->tc = TC_JUM | TC_TX | TC_VLAN;
378 static inline int axienet_rx_resetting(struct XilinxAXIEnet *s)
380 return s->rcw[1] & RCW1_RST;
383 static inline int axienet_rx_enabled(struct XilinxAXIEnet *s)
385 return s->rcw[1] & RCW1_RX;
388 static inline int axienet_extmcf_enabled(struct XilinxAXIEnet *s)
390 return !!(s->regs[R_RAF] & RAF_EMCF_EN);
393 static inline int axienet_newfunc_enabled(struct XilinxAXIEnet *s)
395 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
398 static void axienet_reset(struct XilinxAXIEnet *s)
403 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS;
404 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE;
406 s->emmc = EMMC_LINKSPEED_100MB;
409 static void enet_update_irq(struct XilinxAXIEnet *s)
411 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE];
412 qemu_set_irq(s->irq, !!s->regs[R_IP]);
415 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
417 struct XilinxAXIEnet *s = opaque;
424 r = s->rcw[addr & 1];
440 r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready. */
443 case R_STATS_RX_BYTESL:
444 case R_STATS_RX_BYTESH:
445 r = s->stats.rx_bytes >> (32 * (addr & 1));
448 case R_STATS_TX_BYTESL:
449 case R_STATS_TX_BYTESH:
450 r = s->stats.tx_bytes >> (32 * (addr & 1));
455 r = s->stats.rx >> (32 * (addr & 1));
457 case R_STATS_RX_BCASTL:
458 case R_STATS_RX_BCASTH:
459 r = s->stats.rx_bcast >> (32 * (addr & 1));
461 case R_STATS_RX_MCASTL:
462 case R_STATS_RX_MCASTH:
463 r = s->stats.rx_mcast >> (32 * (addr & 1));
469 r = s->mii.regs[addr & 3];
474 r = s->uaw[addr & 1];
479 r = s->ext_uaw[addr & 1];
488 r = s->maddr[s->fmi & 3][addr & 1];
491 case 0x8000 ... 0x83ff:
492 r = s->ext_mtable[addr - 0x8000];
496 if (addr < ARRAY_SIZE(s->regs)) {
499 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
500 __func__, addr * 4, r));
506 static void enet_write(void *opaque, hwaddr addr,
507 uint64_t value, unsigned size)
509 struct XilinxAXIEnet *s = opaque;
510 struct TEMAC *t = &s->TEMAC;
516 s->rcw[addr & 1] = value;
517 if ((addr & 1) && value & RCW1_RST) {
524 if (value & TC_RST) {
538 value &= ((1 < 7) - 1);
540 /* Enable the MII. */
542 unsigned int miiclkdiv = value & ((1 << 6) - 1);
544 qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
551 unsigned int phyaddr = (value >> 24) & 0x1f;
552 unsigned int regaddr = (value >> 16) & 0x1f;
553 unsigned int op = (value >> 14) & 3;
554 unsigned int initiate = (value >> 11) & 1;
558 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd);
559 } else if (op == 2) {
560 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr);
562 qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
571 s->mii.regs[addr & 3] = value;
577 s->uaw[addr & 1] = value;
582 s->ext_uaw[addr & 1] = value;
591 s->maddr[s->fmi & 3][addr & 1] = value;
595 s->regs[addr] &= ~value;
598 case 0x8000 ... 0x83ff:
599 s->ext_mtable[addr - 0x8000] = value;
603 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
604 __func__, addr * 4, (unsigned)value));
605 if (addr < ARRAY_SIZE(s->regs)) {
606 s->regs[addr] = value;
613 static const MemoryRegionOps enet_ops = {
616 .endianness = DEVICE_LITTLE_ENDIAN,
619 static int eth_can_rx(NetClientState *nc)
621 struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque;
624 return !axienet_rx_resetting(s) && axienet_rx_enabled(s);
627 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1)
631 if (memcmp(buf, &f0, 4)) {
635 if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) {
642 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
644 struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque;
645 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
647 static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52};
648 uint32_t app[6] = {0};
649 int promisc = s->fmi & (1 << 31);
650 int unicast, broadcast, multicast, ip_multicast = 0;
655 DENET(qemu_log("%s: %zd bytes\n", __func__, size));
657 unicast = ~buf[0] & 0x1;
658 broadcast = memcmp(buf, sa_bcast, 6) == 0;
659 multicast = !unicast && !broadcast;
660 if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) {
664 /* Jumbo or vlan sizes ? */
665 if (!(s->rcw[1] & RCW1_JUM)) {
666 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) {
671 /* Basic Address filters. If you want to use the extended filters
672 you'll generally have to place the ethernet mac into promiscuous mode
673 to avoid the basic filtering from dropping most frames. */
676 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) {
682 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
689 if (s->regs[R_RAF] & RAF_MCAST_REJ) {
693 for (i = 0; i < 4; i++) {
694 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) {
707 /* Extended mcast filtering enabled? */
708 if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
710 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) {
716 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
723 if (!memcmp(buf, sa_ipmcast, 3)) {
727 idx = (buf[4] & 0x7f) << 8;
730 bit = 1 << (idx & 0x1f);
733 if (!(s->ext_mtable[idx] & bit)) {
741 s->regs[R_IS] |= IS_RX_REJECT;
746 if (size > (s->c_rxmem - 4)) {
747 size = s->c_rxmem - 4;
750 memcpy(s->rxmem, buf, size);
751 memset(s->rxmem + size, 0, 4); /* Clear the FCS. */
753 if (s->rcw[1] & RCW1_FCS) {
754 size += 4; /* fcs is inband. */
758 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14);
760 csum32 = (csum32 & 0xffff) + (csum32 >> 16);
761 /* And twice to get rid of possible carries. */
762 csum16 = (csum32 & 0xffff) + (csum32 >> 16);
764 app[4] = size & 0xffff;
766 s->stats.rx_bytes += size;
770 app[2] |= 1 | (ip_multicast << 1);
771 } else if (broadcast) {
779 stream_push(s->tx_dev, (void *)s->rxmem, size, app);
781 s->regs[R_IS] |= IS_RX_COMPLETE;
786 static void eth_cleanup(NetClientState *nc)
789 struct XilinxAXIEnet *s = DO_UPCAST(NICState, nc, nc)->opaque;
795 axienet_stream_push(StreamSlave *obj, uint8_t *buf, size_t size, uint32_t *hdr)
797 struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
800 if (!(s->tc & TC_TX)) {
804 /* Jumbo or vlan sizes ? */
805 if (!(s->tc & TC_JUM)) {
806 if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) {
812 unsigned int start_off = hdr[1] >> 16;
813 unsigned int write_off = hdr[1] & 0xffff;
817 tmp_csum = net_checksum_add(size - start_off,
818 (uint8_t *)buf + start_off);
819 /* Accumulate the seed. */
820 tmp_csum += hdr[2] & 0xffff;
822 /* Fold the 32bit partial checksum. */
823 csum = net_checksum_finish(tmp_csum);
826 buf[write_off] = csum >> 8;
827 buf[write_off + 1] = csum & 0xff;
830 qemu_send_packet(&s->nic->nc, buf, size);
832 s->stats.tx_bytes += size;
833 s->regs[R_IS] |= IS_TX_COMPLETE;
837 static NetClientInfo net_xilinx_enet_info = {
838 .type = NET_CLIENT_OPTIONS_KIND_NIC,
839 .size = sizeof(NICState),
840 .can_receive = eth_can_rx,
842 .cleanup = eth_cleanup,
845 static int xilinx_enet_init(SysBusDevice *dev)
847 struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), dev);
849 sysbus_init_irq(dev, &s->irq);
851 memory_region_init_io(&s->iomem, &enet_ops, s, "enet", 0x40000);
852 sysbus_init_mmio(dev, &s->iomem);
854 qemu_macaddr_default_if_unset(&s->conf.macaddr);
855 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,
856 object_get_typename(OBJECT(dev)), dev->qdev.id, s);
857 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
859 tdk_init(&s->TEMAC.phy);
860 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr);
864 s->rxmem = g_malloc(s->c_rxmem);
870 static void xilinx_enet_initfn(Object *obj)
872 struct XilinxAXIEnet *s = FROM_SYSBUS(typeof(*s), SYS_BUS_DEVICE(obj));
874 object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
875 (Object **) &s->tx_dev, NULL);
878 static Property xilinx_enet_properties[] = {
879 DEFINE_PROP_UINT32("phyaddr", struct XilinxAXIEnet, c_phyaddr, 7),
880 DEFINE_PROP_UINT32("rxmem", struct XilinxAXIEnet, c_rxmem, 0x1000),
881 DEFINE_PROP_UINT32("txmem", struct XilinxAXIEnet, c_txmem, 0x1000),
882 DEFINE_NIC_PROPERTIES(struct XilinxAXIEnet, conf),
883 DEFINE_PROP_END_OF_LIST(),
886 static void xilinx_enet_class_init(ObjectClass *klass, void *data)
888 DeviceClass *dc = DEVICE_CLASS(klass);
889 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
890 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
892 k->init = xilinx_enet_init;
893 dc->props = xilinx_enet_properties;
894 ssc->push = axienet_stream_push;
897 static TypeInfo xilinx_enet_info = {
898 .name = "xlnx.axi-ethernet",
899 .parent = TYPE_SYS_BUS_DEVICE,
900 .instance_size = sizeof(struct XilinxAXIEnet),
901 .class_init = xilinx_enet_class_init,
902 .instance_init = xilinx_enet_initfn,
903 .interfaces = (InterfaceInfo[]) {
904 { TYPE_STREAM_SLAVE },
909 static void xilinx_enet_register_types(void)
911 type_register_static(&xilinx_enet_info);
914 type_init(xilinx_enet_register_types)