2 * StrongARM SA-1100/SA-1110 emulation
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Contributions after 2012-01-13 are licensed under the terms of the
27 * GNU GPL, version 2 or (at your option) any later version.
30 #include "strongarm.h"
31 #include "qemu-error.h"
33 #include "qemu-char.h"
41 - Implement cp15, c14 ?
42 - Implement cp15, c15 !!! (idle used in L)
43 - Implement idle mode handling/DIM
44 - Implement sleep mode/Wake sources
45 - Implement reset control
46 - Implement memory control regs
48 - Maybe support MBGNT/MBREQ
53 - Enhance UART with modem signals
57 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
59 # define DPRINTF(format, ...) do { } while (0)
66 { 0x80010000, SA_PIC_UART1 },
67 { 0x80030000, SA_PIC_UART2 },
68 { 0x80050000, SA_PIC_UART3 },
72 /* Interrupt Controller */
92 #define SA_PIC_SRCS 32
95 static void strongarm_pic_update(void *opaque)
97 StrongARMPICState *s = opaque;
99 /* FIXME: reflect DIM */
100 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq);
101 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
104 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
106 StrongARMPICState *s = opaque;
109 s->pending |= 1 << irq;
111 s->pending &= ~(1 << irq);
114 strongarm_pic_update(s);
117 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
120 StrongARMPICState *s = opaque;
124 return s->pending & ~s->is_fiq & s->enabled;
130 return s->int_idle == 0;
132 return s->pending & s->is_fiq & s->enabled;
136 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
142 static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
143 uint64_t value, unsigned size)
145 StrongARMPICState *s = opaque;
155 s->int_idle = (value & 1) ? 0 : ~0;
158 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
162 strongarm_pic_update(s);
165 static const MemoryRegionOps strongarm_pic_ops = {
166 .read = strongarm_pic_mem_read,
167 .write = strongarm_pic_mem_write,
168 .endianness = DEVICE_NATIVE_ENDIAN,
171 static int strongarm_pic_initfn(SysBusDevice *dev)
173 StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);
175 qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);
176 memory_region_init_io(&s->iomem, &strongarm_pic_ops, s, "pic", 0x1000);
177 sysbus_init_mmio(dev, &s->iomem);
178 sysbus_init_irq(dev, &s->irq);
179 sysbus_init_irq(dev, &s->fiq);
184 static int strongarm_pic_post_load(void *opaque, int version_id)
186 strongarm_pic_update(opaque);
190 static VMStateDescription vmstate_strongarm_pic_regs = {
191 .name = "strongarm_pic",
193 .minimum_version_id = 0,
194 .minimum_version_id_old = 0,
195 .post_load = strongarm_pic_post_load,
196 .fields = (VMStateField[]) {
197 VMSTATE_UINT32(pending, StrongARMPICState),
198 VMSTATE_UINT32(enabled, StrongARMPICState),
199 VMSTATE_UINT32(is_fiq, StrongARMPICState),
200 VMSTATE_UINT32(int_idle, StrongARMPICState),
201 VMSTATE_END_OF_LIST(),
205 static void strongarm_pic_class_init(ObjectClass *klass, void *data)
207 DeviceClass *dc = DEVICE_CLASS(klass);
208 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
210 k->init = strongarm_pic_initfn;
211 dc->desc = "StrongARM PIC";
212 dc->vmsd = &vmstate_strongarm_pic_regs;
215 static TypeInfo strongarm_pic_info = {
216 .name = "strongarm_pic",
217 .parent = TYPE_SYS_BUS_DEVICE,
218 .instance_size = sizeof(StrongARMPICState),
219 .class_init = strongarm_pic_class_init,
222 /* Real-Time Clock */
223 #define RTAR 0x00 /* RTC Alarm register */
224 #define RCNR 0x04 /* RTC Counter register */
225 #define RTTR 0x08 /* RTC Timer Trim register */
226 #define RTSR 0x10 /* RTC Status register */
228 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
229 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
230 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
231 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
233 /* 16 LSB of RTTR are clockdiv for internal trim logic,
234 * trim delete isn't emulated, so
235 * f = 32 768 / (RTTR_trim + 1) */
245 QEMUTimer *rtc_alarm;
251 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
253 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
254 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
257 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
259 int64_t rt = qemu_get_clock_ms(rtc_clock);
260 s->last_rcnr += ((rt - s->last_hz) << 15) /
261 (1000 * ((s->rttr & 0xffff) + 1));
265 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
267 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
268 qemu_mod_timer(s->rtc_hz, s->last_hz + 1000);
270 qemu_del_timer(s->rtc_hz);
273 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
274 qemu_mod_timer(s->rtc_alarm, s->last_hz +
275 (((s->rtar - s->last_rcnr) * 1000 *
276 ((s->rttr & 0xffff) + 1)) >> 15));
278 qemu_del_timer(s->rtc_alarm);
282 static inline void strongarm_rtc_alarm_tick(void *opaque)
284 StrongARMRTCState *s = opaque;
286 strongarm_rtc_timer_update(s);
287 strongarm_rtc_int_update(s);
290 static inline void strongarm_rtc_hz_tick(void *opaque)
292 StrongARMRTCState *s = opaque;
294 strongarm_rtc_timer_update(s);
295 strongarm_rtc_int_update(s);
298 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
301 StrongARMRTCState *s = opaque;
311 return s->last_rcnr +
312 ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
313 (1000 * ((s->rttr & 0xffff) + 1));
315 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
320 static void strongarm_rtc_write(void *opaque, hwaddr addr,
321 uint64_t value, unsigned size)
323 StrongARMRTCState *s = opaque;
328 strongarm_rtc_hzupdate(s);
330 strongarm_rtc_timer_update(s);
335 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
336 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
338 if (s->rtsr != old_rtsr) {
339 strongarm_rtc_timer_update(s);
342 strongarm_rtc_int_update(s);
347 strongarm_rtc_timer_update(s);
351 strongarm_rtc_hzupdate(s);
352 s->last_rcnr = value;
353 strongarm_rtc_timer_update(s);
357 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
361 static const MemoryRegionOps strongarm_rtc_ops = {
362 .read = strongarm_rtc_read,
363 .write = strongarm_rtc_write,
364 .endianness = DEVICE_NATIVE_ENDIAN,
367 static int strongarm_rtc_init(SysBusDevice *dev)
369 StrongARMRTCState *s = FROM_SYSBUS(StrongARMRTCState, dev);
375 qemu_get_timedate(&tm, 0);
377 s->last_rcnr = (uint32_t) mktimegm(&tm);
378 s->last_hz = qemu_get_clock_ms(rtc_clock);
380 s->rtc_alarm = qemu_new_timer_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
381 s->rtc_hz = qemu_new_timer_ms(rtc_clock, strongarm_rtc_hz_tick, s);
383 sysbus_init_irq(dev, &s->rtc_irq);
384 sysbus_init_irq(dev, &s->rtc_hz_irq);
386 memory_region_init_io(&s->iomem, &strongarm_rtc_ops, s, "rtc", 0x10000);
387 sysbus_init_mmio(dev, &s->iomem);
392 static void strongarm_rtc_pre_save(void *opaque)
394 StrongARMRTCState *s = opaque;
396 strongarm_rtc_hzupdate(s);
399 static int strongarm_rtc_post_load(void *opaque, int version_id)
401 StrongARMRTCState *s = opaque;
403 strongarm_rtc_timer_update(s);
404 strongarm_rtc_int_update(s);
409 static const VMStateDescription vmstate_strongarm_rtc_regs = {
410 .name = "strongarm-rtc",
412 .minimum_version_id = 0,
413 .minimum_version_id_old = 0,
414 .pre_save = strongarm_rtc_pre_save,
415 .post_load = strongarm_rtc_post_load,
416 .fields = (VMStateField[]) {
417 VMSTATE_UINT32(rttr, StrongARMRTCState),
418 VMSTATE_UINT32(rtsr, StrongARMRTCState),
419 VMSTATE_UINT32(rtar, StrongARMRTCState),
420 VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
421 VMSTATE_INT64(last_hz, StrongARMRTCState),
422 VMSTATE_END_OF_LIST(),
426 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
428 DeviceClass *dc = DEVICE_CLASS(klass);
429 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
431 k->init = strongarm_rtc_init;
432 dc->desc = "StrongARM RTC Controller";
433 dc->vmsd = &vmstate_strongarm_rtc_regs;
436 static TypeInfo strongarm_rtc_sysbus_info = {
437 .name = "strongarm-rtc",
438 .parent = TYPE_SYS_BUS_DEVICE,
439 .instance_size = sizeof(StrongARMRTCState),
440 .class_init = strongarm_rtc_sysbus_class_init,
453 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
454 struct StrongARMGPIOInfo {
457 qemu_irq handler[28];
474 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
477 for (i = 0; i < 11; i++) {
478 qemu_set_irq(s->irqs[i], s->status & (1 << i));
481 qemu_set_irq(s->irqX, (s->status & ~0x7ff));
484 static void strongarm_gpio_set(void *opaque, int line, int level)
486 StrongARMGPIOInfo *s = opaque;
492 s->status |= s->rising & mask &
493 ~s->ilevel & ~s->dir;
496 s->status |= s->falling & mask &
501 if (s->status & mask) {
502 strongarm_gpio_irq_update(s);
506 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
508 uint32_t level, diff;
511 level = s->olevel & s->dir;
513 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
515 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
518 s->prev_level = level;
521 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
524 StrongARMGPIOInfo *s = opaque;
527 case GPDR: /* GPIO Pin-Direction registers */
530 case GPSR: /* GPIO Pin-Output Set registers */
531 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
533 return s->gpsr; /* Return last written value. */
535 case GPCR: /* GPIO Pin-Output Clear registers */
536 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
538 return 31337; /* Specified as unpredictable in the docs. */
540 case GRER: /* GPIO Rising-Edge Detect Enable registers */
543 case GFER: /* GPIO Falling-Edge Detect Enable registers */
546 case GAFR: /* GPIO Alternate Function registers */
549 case GPLR: /* GPIO Pin-Level registers */
550 return (s->olevel & s->dir) |
551 (s->ilevel & ~s->dir);
553 case GEDR: /* GPIO Edge Detect Status registers */
557 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
563 static void strongarm_gpio_write(void *opaque, hwaddr offset,
564 uint64_t value, unsigned size)
566 StrongARMGPIOInfo *s = opaque;
569 case GPDR: /* GPIO Pin-Direction registers */
571 strongarm_gpio_handler_update(s);
574 case GPSR: /* GPIO Pin-Output Set registers */
576 strongarm_gpio_handler_update(s);
580 case GPCR: /* GPIO Pin-Output Clear registers */
582 strongarm_gpio_handler_update(s);
585 case GRER: /* GPIO Rising-Edge Detect Enable registers */
589 case GFER: /* GPIO Falling-Edge Detect Enable registers */
593 case GAFR: /* GPIO Alternate Function registers */
597 case GEDR: /* GPIO Edge Detect Status registers */
599 strongarm_gpio_irq_update(s);
603 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
607 static const MemoryRegionOps strongarm_gpio_ops = {
608 .read = strongarm_gpio_read,
609 .write = strongarm_gpio_write,
610 .endianness = DEVICE_NATIVE_ENDIAN,
613 static DeviceState *strongarm_gpio_init(hwaddr base,
619 dev = qdev_create(NULL, "strongarm-gpio");
620 qdev_init_nofail(dev);
622 sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
623 for (i = 0; i < 12; i++)
624 sysbus_connect_irq(sysbus_from_qdev(dev), i,
625 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
630 static int strongarm_gpio_initfn(SysBusDevice *dev)
632 StrongARMGPIOInfo *s;
635 s = FROM_SYSBUS(StrongARMGPIOInfo, dev);
637 qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28);
638 qdev_init_gpio_out(&dev->qdev, s->handler, 28);
640 memory_region_init_io(&s->iomem, &strongarm_gpio_ops, s, "gpio", 0x1000);
642 sysbus_init_mmio(dev, &s->iomem);
643 for (i = 0; i < 11; i++) {
644 sysbus_init_irq(dev, &s->irqs[i]);
646 sysbus_init_irq(dev, &s->irqX);
651 static const VMStateDescription vmstate_strongarm_gpio_regs = {
652 .name = "strongarm-gpio",
654 .minimum_version_id = 0,
655 .minimum_version_id_old = 0,
656 .fields = (VMStateField[]) {
657 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
658 VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
659 VMSTATE_UINT32(dir, StrongARMGPIOInfo),
660 VMSTATE_UINT32(rising, StrongARMGPIOInfo),
661 VMSTATE_UINT32(falling, StrongARMGPIOInfo),
662 VMSTATE_UINT32(status, StrongARMGPIOInfo),
663 VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
664 VMSTATE_END_OF_LIST(),
668 static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
670 DeviceClass *dc = DEVICE_CLASS(klass);
671 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
673 k->init = strongarm_gpio_initfn;
674 dc->desc = "StrongARM GPIO controller";
677 static TypeInfo strongarm_gpio_info = {
678 .name = "strongarm-gpio",
679 .parent = TYPE_SYS_BUS_DEVICE,
680 .instance_size = sizeof(StrongARMGPIOInfo),
681 .class_init = strongarm_gpio_class_init,
684 /* Peripheral Pin Controller */
691 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
692 struct StrongARMPPCInfo {
695 qemu_irq handler[28];
707 static void strongarm_ppc_set(void *opaque, int line, int level)
709 StrongARMPPCInfo *s = opaque;
712 s->ilevel |= 1 << line;
714 s->ilevel &= ~(1 << line);
718 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
720 uint32_t level, diff;
723 level = s->olevel & s->dir;
725 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
727 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
730 s->prev_level = level;
733 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
736 StrongARMPPCInfo *s = opaque;
739 case PPDR: /* PPC Pin Direction registers */
740 return s->dir | ~0x3fffff;
742 case PPSR: /* PPC Pin State registers */
743 return (s->olevel & s->dir) |
744 (s->ilevel & ~s->dir) |
748 return s->ppar | ~0x41000;
754 return s->ppfr | ~0x7f001;
757 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
763 static void strongarm_ppc_write(void *opaque, hwaddr offset,
764 uint64_t value, unsigned size)
766 StrongARMPPCInfo *s = opaque;
769 case PPDR: /* PPC Pin Direction registers */
770 s->dir = value & 0x3fffff;
771 strongarm_ppc_handler_update(s);
774 case PPSR: /* PPC Pin State registers */
775 s->olevel = value & s->dir & 0x3fffff;
776 strongarm_ppc_handler_update(s);
780 s->ppar = value & 0x41000;
784 s->psdr = value & 0x3fffff;
788 s->ppfr = value & 0x7f001;
792 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
796 static const MemoryRegionOps strongarm_ppc_ops = {
797 .read = strongarm_ppc_read,
798 .write = strongarm_ppc_write,
799 .endianness = DEVICE_NATIVE_ENDIAN,
802 static int strongarm_ppc_init(SysBusDevice *dev)
806 s = FROM_SYSBUS(StrongARMPPCInfo, dev);
808 qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22);
809 qdev_init_gpio_out(&dev->qdev, s->handler, 22);
811 memory_region_init_io(&s->iomem, &strongarm_ppc_ops, s, "ppc", 0x1000);
813 sysbus_init_mmio(dev, &s->iomem);
818 static const VMStateDescription vmstate_strongarm_ppc_regs = {
819 .name = "strongarm-ppc",
821 .minimum_version_id = 0,
822 .minimum_version_id_old = 0,
823 .fields = (VMStateField[]) {
824 VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
825 VMSTATE_UINT32(olevel, StrongARMPPCInfo),
826 VMSTATE_UINT32(dir, StrongARMPPCInfo),
827 VMSTATE_UINT32(ppar, StrongARMPPCInfo),
828 VMSTATE_UINT32(psdr, StrongARMPPCInfo),
829 VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
830 VMSTATE_END_OF_LIST(),
834 static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
836 DeviceClass *dc = DEVICE_CLASS(klass);
837 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
839 k->init = strongarm_ppc_init;
840 dc->desc = "StrongARM PPC controller";
843 static TypeInfo strongarm_ppc_info = {
844 .name = "strongarm-ppc",
845 .parent = TYPE_SYS_BUS_DEVICE,
846 .instance_size = sizeof(StrongARMPPCInfo),
847 .class_init = strongarm_ppc_class_init,
859 #define UTCR0_PE (1 << 0) /* Parity enable */
860 #define UTCR0_OES (1 << 1) /* Even parity */
861 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
862 #define UTCR0_DSS (1 << 3) /* 8-bit data */
864 #define UTCR3_RXE (1 << 0) /* Rx enable */
865 #define UTCR3_TXE (1 << 1) /* Tx enable */
866 #define UTCR3_BRK (1 << 2) /* Force Break */
867 #define UTCR3_RIE (1 << 3) /* Rx int enable */
868 #define UTCR3_TIE (1 << 4) /* Tx int enable */
869 #define UTCR3_LBM (1 << 5) /* Loopback */
871 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
872 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
873 #define UTSR0_RID (1 << 2) /* Receiver Idle */
874 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
875 #define UTSR0_REB (1 << 4) /* Receiver end break */
876 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
878 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
879 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
880 #define UTSR1_PRE (1 << 3) /* Parity error */
881 #define UTSR1_FRE (1 << 4) /* Frame error */
882 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
884 #define RX_FIFO_PRE (1 << 8)
885 #define RX_FIFO_FRE (1 << 9)
886 #define RX_FIFO_ROR (1 << 10)
891 CharDriverState *chr;
903 uint16_t rx_fifo[12]; /* value + error flags in high bits */
907 uint64_t char_transmit_time; /* time to transmit a char in ticks*/
909 QEMUTimer *rx_timeout_timer;
911 } StrongARMUARTState;
913 static void strongarm_uart_update_status(StrongARMUARTState *s)
917 if (s->tx_len != 8) {
921 if (s->rx_len != 0) {
922 uint16_t ent = s->rx_fifo[s->rx_start];
925 if (ent & RX_FIFO_PRE) {
926 s->utsr1 |= UTSR1_PRE;
928 if (ent & RX_FIFO_FRE) {
929 s->utsr1 |= UTSR1_FRE;
931 if (ent & RX_FIFO_ROR) {
932 s->utsr1 |= UTSR1_ROR;
939 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
941 uint16_t utsr0 = s->utsr0 &
942 (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
945 if ((s->utcr3 & UTCR3_TXE) &&
946 (s->utcr3 & UTCR3_TIE) &&
951 if ((s->utcr3 & UTCR3_RXE) &&
952 (s->utcr3 & UTCR3_RIE) &&
957 for (i = 0; i < s->rx_len && i < 4; i++)
958 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
964 qemu_set_irq(s->irq, utsr0);
967 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
969 int speed, parity, data_bits, stop_bits, frame_size;
970 QEMUSerialSetParams ssp;
974 if (s->utcr0 & UTCR0_PE) {
977 if (s->utcr0 & UTCR0_OES) {
985 if (s->utcr0 & UTCR0_SBS) {
991 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
992 frame_size += data_bits + stop_bits;
993 speed = 3686400 / 16 / (s->brd + 1);
996 ssp.data_bits = data_bits;
997 ssp.stop_bits = stop_bits;
998 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
1000 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1003 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
1004 speed, parity, data_bits, stop_bits);
1007 static void strongarm_uart_rx_to(void *opaque)
1009 StrongARMUARTState *s = opaque;
1012 s->utsr0 |= UTSR0_RID;
1013 strongarm_uart_update_int_status(s);
1017 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1019 if ((s->utcr3 & UTCR3_RXE) == 0) {
1024 if (s->wait_break_end) {
1025 s->utsr0 |= UTSR0_REB;
1026 s->wait_break_end = false;
1029 if (s->rx_len < 12) {
1030 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1033 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1036 static int strongarm_uart_can_receive(void *opaque)
1038 StrongARMUARTState *s = opaque;
1040 if (s->rx_len == 12) {
1043 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1044 if (s->rx_len < 8) {
1045 return 8 - s->rx_len;
1050 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1052 StrongARMUARTState *s = opaque;
1055 for (i = 0; i < size; i++) {
1056 strongarm_uart_rx_push(s, buf[i]);
1059 /* call the timeout receive callback in 3 char transmit time */
1060 qemu_mod_timer(s->rx_timeout_timer,
1061 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1063 strongarm_uart_update_status(s);
1064 strongarm_uart_update_int_status(s);
1067 static void strongarm_uart_event(void *opaque, int event)
1069 StrongARMUARTState *s = opaque;
1070 if (event == CHR_EVENT_BREAK) {
1071 s->utsr0 |= UTSR0_RBB;
1072 strongarm_uart_rx_push(s, RX_FIFO_FRE);
1073 s->wait_break_end = true;
1074 strongarm_uart_update_status(s);
1075 strongarm_uart_update_int_status(s);
1079 static void strongarm_uart_tx(void *opaque)
1081 StrongARMUARTState *s = opaque;
1082 uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
1084 if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1085 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1086 } else if (s->chr) {
1087 qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1);
1090 s->tx_start = (s->tx_start + 1) % 8;
1093 qemu_mod_timer(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1095 strongarm_uart_update_status(s);
1096 strongarm_uart_update_int_status(s);
1099 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
1102 StrongARMUARTState *s = opaque;
1113 return s->brd & 0xff;
1119 if (s->rx_len != 0) {
1120 ret = s->rx_fifo[s->rx_start];
1121 s->rx_start = (s->rx_start + 1) % 12;
1123 strongarm_uart_update_status(s);
1124 strongarm_uart_update_int_status(s);
1136 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1141 static void strongarm_uart_write(void *opaque, hwaddr addr,
1142 uint64_t value, unsigned size)
1144 StrongARMUARTState *s = opaque;
1148 s->utcr0 = value & 0x7f;
1149 strongarm_uart_update_parameters(s);
1153 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1154 strongarm_uart_update_parameters(s);
1158 s->brd = (s->brd & 0xf00) | (value & 0xff);
1159 strongarm_uart_update_parameters(s);
1163 s->utcr3 = value & 0x3f;
1164 if ((s->utcr3 & UTCR3_RXE) == 0) {
1167 if ((s->utcr3 & UTCR3_TXE) == 0) {
1170 strongarm_uart_update_status(s);
1171 strongarm_uart_update_int_status(s);
1175 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1176 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1178 strongarm_uart_update_status(s);
1179 strongarm_uart_update_int_status(s);
1180 if (s->tx_len == 1) {
1181 strongarm_uart_tx(s);
1187 s->utsr0 = s->utsr0 & ~(value &
1188 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1189 strongarm_uart_update_int_status(s);
1193 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1197 static const MemoryRegionOps strongarm_uart_ops = {
1198 .read = strongarm_uart_read,
1199 .write = strongarm_uart_write,
1200 .endianness = DEVICE_NATIVE_ENDIAN,
1203 static int strongarm_uart_init(SysBusDevice *dev)
1205 StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev);
1207 memory_region_init_io(&s->iomem, &strongarm_uart_ops, s, "uart", 0x10000);
1208 sysbus_init_mmio(dev, &s->iomem);
1209 sysbus_init_irq(dev, &s->irq);
1211 s->rx_timeout_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_rx_to, s);
1212 s->tx_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_tx, s);
1215 qemu_chr_add_handlers(s->chr,
1216 strongarm_uart_can_receive,
1217 strongarm_uart_receive,
1218 strongarm_uart_event,
1225 static void strongarm_uart_reset(DeviceState *dev)
1227 StrongARMUARTState *s = DO_UPCAST(StrongARMUARTState, busdev.qdev, dev);
1229 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1230 s->brd = 23; /* 9600 */
1231 /* enable send & recv - this actually violates spec */
1232 s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1234 s->rx_len = s->tx_len = 0;
1236 strongarm_uart_update_parameters(s);
1237 strongarm_uart_update_status(s);
1238 strongarm_uart_update_int_status(s);
1241 static int strongarm_uart_post_load(void *opaque, int version_id)
1243 StrongARMUARTState *s = opaque;
1245 strongarm_uart_update_parameters(s);
1246 strongarm_uart_update_status(s);
1247 strongarm_uart_update_int_status(s);
1249 /* tx and restart timer */
1251 strongarm_uart_tx(s);
1254 /* restart rx timeout timer */
1256 qemu_mod_timer(s->rx_timeout_timer,
1257 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1263 static const VMStateDescription vmstate_strongarm_uart_regs = {
1264 .name = "strongarm-uart",
1266 .minimum_version_id = 0,
1267 .minimum_version_id_old = 0,
1268 .post_load = strongarm_uart_post_load,
1269 .fields = (VMStateField[]) {
1270 VMSTATE_UINT8(utcr0, StrongARMUARTState),
1271 VMSTATE_UINT16(brd, StrongARMUARTState),
1272 VMSTATE_UINT8(utcr3, StrongARMUARTState),
1273 VMSTATE_UINT8(utsr0, StrongARMUARTState),
1274 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1275 VMSTATE_UINT8(tx_start, StrongARMUARTState),
1276 VMSTATE_UINT8(tx_len, StrongARMUARTState),
1277 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1278 VMSTATE_UINT8(rx_start, StrongARMUARTState),
1279 VMSTATE_UINT8(rx_len, StrongARMUARTState),
1280 VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1281 VMSTATE_END_OF_LIST(),
1285 static Property strongarm_uart_properties[] = {
1286 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1287 DEFINE_PROP_END_OF_LIST(),
1290 static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1292 DeviceClass *dc = DEVICE_CLASS(klass);
1293 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1295 k->init = strongarm_uart_init;
1296 dc->desc = "StrongARM UART controller";
1297 dc->reset = strongarm_uart_reset;
1298 dc->vmsd = &vmstate_strongarm_uart_regs;
1299 dc->props = strongarm_uart_properties;
1302 static TypeInfo strongarm_uart_info = {
1303 .name = "strongarm-uart",
1304 .parent = TYPE_SYS_BUS_DEVICE,
1305 .instance_size = sizeof(StrongARMUARTState),
1306 .class_init = strongarm_uart_class_init,
1309 /* Synchronous Serial Ports */
1311 SysBusDevice busdev;
1319 uint16_t rx_fifo[8];
1322 } StrongARMSSPState;
1324 #define SSCR0 0x60 /* SSP Control register 0 */
1325 #define SSCR1 0x64 /* SSP Control register 1 */
1326 #define SSDR 0x6c /* SSP Data register */
1327 #define SSSR 0x74 /* SSP Status register */
1329 /* Bitfields for above registers */
1330 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1331 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1332 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1333 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1334 #define SSCR0_SSE (1 << 7)
1335 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1336 #define SSCR1_RIE (1 << 0)
1337 #define SSCR1_TIE (1 << 1)
1338 #define SSCR1_LBM (1 << 2)
1339 #define SSSR_TNF (1 << 2)
1340 #define SSSR_RNE (1 << 3)
1341 #define SSSR_TFS (1 << 5)
1342 #define SSSR_RFS (1 << 6)
1343 #define SSSR_ROR (1 << 7)
1344 #define SSSR_RW 0x0080
1346 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1350 level |= (s->sssr & SSSR_ROR);
1351 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
1352 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
1353 qemu_set_irq(s->irq, level);
1356 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1358 s->sssr &= ~SSSR_TFS;
1359 s->sssr &= ~SSSR_TNF;
1360 if (s->sscr[0] & SSCR0_SSE) {
1361 if (s->rx_level >= 4) {
1362 s->sssr |= SSSR_RFS;
1364 s->sssr &= ~SSSR_RFS;
1367 s->sssr |= SSSR_RNE;
1369 s->sssr &= ~SSSR_RNE;
1371 /* TX FIFO is never filled, so it is always in underrun
1372 condition if SSP is enabled */
1373 s->sssr |= SSSR_TFS;
1374 s->sssr |= SSSR_TNF;
1377 strongarm_ssp_int_update(s);
1380 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
1383 StrongARMSSPState *s = opaque;
1394 if (~s->sscr[0] & SSCR0_SSE) {
1397 if (s->rx_level < 1) {
1398 printf("%s: SSP Rx Underrun\n", __func__);
1402 retval = s->rx_fifo[s->rx_start++];
1404 strongarm_ssp_fifo_update(s);
1407 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1413 static void strongarm_ssp_write(void *opaque, hwaddr addr,
1414 uint64_t value, unsigned size)
1416 StrongARMSSPState *s = opaque;
1420 s->sscr[0] = value & 0xffbf;
1421 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1422 printf("%s: Wrong data size: %i bits\n", __func__,
1423 (int)SSCR0_DSS(value));
1425 if (!(value & SSCR0_SSE)) {
1429 strongarm_ssp_fifo_update(s);
1433 s->sscr[1] = value & 0x2f;
1434 if (value & SSCR1_LBM) {
1435 printf("%s: Attempt to use SSP LBM mode\n", __func__);
1437 strongarm_ssp_fifo_update(s);
1441 s->sssr &= ~(value & SSSR_RW);
1442 strongarm_ssp_int_update(s);
1446 if (SSCR0_UWIRE(s->sscr[0])) {
1449 /* Note how 32bits overflow does no harm here */
1450 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1452 /* Data goes from here to the Tx FIFO and is shifted out from
1453 * there directly to the slave, no need to buffer it.
1455 if (s->sscr[0] & SSCR0_SSE) {
1457 if (s->sscr[1] & SSCR1_LBM) {
1460 readval = ssi_transfer(s->bus, value);
1463 if (s->rx_level < 0x08) {
1464 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1466 s->sssr |= SSSR_ROR;
1469 strongarm_ssp_fifo_update(s);
1473 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1478 static const MemoryRegionOps strongarm_ssp_ops = {
1479 .read = strongarm_ssp_read,
1480 .write = strongarm_ssp_write,
1481 .endianness = DEVICE_NATIVE_ENDIAN,
1484 static int strongarm_ssp_post_load(void *opaque, int version_id)
1486 StrongARMSSPState *s = opaque;
1488 strongarm_ssp_fifo_update(s);
1493 static int strongarm_ssp_init(SysBusDevice *dev)
1495 StrongARMSSPState *s = FROM_SYSBUS(StrongARMSSPState, dev);
1497 sysbus_init_irq(dev, &s->irq);
1499 memory_region_init_io(&s->iomem, &strongarm_ssp_ops, s, "ssp", 0x1000);
1500 sysbus_init_mmio(dev, &s->iomem);
1502 s->bus = ssi_create_bus(&dev->qdev, "ssi");
1506 static void strongarm_ssp_reset(DeviceState *dev)
1508 StrongARMSSPState *s = DO_UPCAST(StrongARMSSPState, busdev.qdev, dev);
1509 s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1514 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1515 .name = "strongarm-ssp",
1517 .minimum_version_id = 0,
1518 .minimum_version_id_old = 0,
1519 .post_load = strongarm_ssp_post_load,
1520 .fields = (VMStateField[]) {
1521 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1522 VMSTATE_UINT16(sssr, StrongARMSSPState),
1523 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1524 VMSTATE_UINT8(rx_start, StrongARMSSPState),
1525 VMSTATE_UINT8(rx_level, StrongARMSSPState),
1526 VMSTATE_END_OF_LIST(),
1530 static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1532 DeviceClass *dc = DEVICE_CLASS(klass);
1533 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1535 k->init = strongarm_ssp_init;
1536 dc->desc = "StrongARM SSP controller";
1537 dc->reset = strongarm_ssp_reset;
1538 dc->vmsd = &vmstate_strongarm_ssp_regs;
1541 static TypeInfo strongarm_ssp_info = {
1542 .name = "strongarm-ssp",
1543 .parent = TYPE_SYS_BUS_DEVICE,
1544 .instance_size = sizeof(StrongARMSSPState),
1545 .class_init = strongarm_ssp_class_init,
1548 /* Main CPU functions */
1549 StrongARMState *sa1110_init(MemoryRegion *sysmem,
1550 unsigned int sdram_size, const char *rev)
1556 s = g_malloc0(sizeof(StrongARMState));
1562 if (strncmp(rev, "sa1110", 6)) {
1563 error_report("Machine requires a SA1110 processor.");
1567 s->cpu = cpu_arm_init(rev);
1570 error_report("Unable to find CPU definition");
1574 memory_region_init_ram(&s->sdram, "strongarm.sdram", sdram_size);
1575 vmstate_register_ram_global(&s->sdram);
1576 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1578 pic = arm_pic_init_cpu(s->cpu);
1579 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1580 pic[ARM_PIC_CPU_IRQ], pic[ARM_PIC_CPU_FIQ], NULL);
1582 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1583 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1584 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1585 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1586 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1589 sysbus_create_simple("strongarm-rtc", 0x90010000,
1590 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1592 s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1594 s->ppc = sysbus_create_varargs("strongarm-ppc", 0x90060000, NULL);
1596 for (i = 0; sa_serial[i].io_base; i++) {
1597 DeviceState *dev = qdev_create(NULL, "strongarm-uart");
1598 qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1599 qdev_init_nofail(dev);
1600 sysbus_mmio_map(sysbus_from_qdev(dev), 0,
1601 sa_serial[i].io_base);
1602 sysbus_connect_irq(sysbus_from_qdev(dev), 0,
1603 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1606 s->ssp = sysbus_create_varargs("strongarm-ssp", 0x80070000,
1607 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1608 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1613 static void strongarm_register_types(void)
1615 type_register_static(&strongarm_pic_info);
1616 type_register_static(&strongarm_rtc_sysbus_info);
1617 type_register_static(&strongarm_gpio_info);
1618 type_register_static(&strongarm_ppc_info);
1619 type_register_static(&strongarm_uart_info);
1620 type_register_static(&strongarm_ssp_info);
1623 type_init(strongarm_register_types)