2 * QEMU SCI/SCIF serial port emulation
4 * Copyright (c) 2007 Magnus Damm
6 * Based on serial.c - QEMU 16450 UART emulation
7 * Copyright (c) 2003-2004 Fabrice Bellard
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #include "qemu-char.h"
30 #include "exec/address-spaces.h"
32 //#define DEBUG_SERIAL
34 #define SH_SERIAL_FLAG_TEND (1 << 0)
35 #define SH_SERIAL_FLAG_TDE (1 << 1)
36 #define SH_SERIAL_FLAG_RDF (1 << 2)
37 #define SH_SERIAL_FLAG_BRK (1 << 3)
38 #define SH_SERIAL_FLAG_DR (1 << 4)
40 #define SH_RX_FIFO_LENGTH (16)
44 MemoryRegion iomem_p4;
45 MemoryRegion iomem_a7;
49 uint8_t dr; /* ftdr / tdr */
50 uint8_t sr; /* fsr / ssr */
54 uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
73 static void sh_serial_clear_fifo(sh_serial_state * s)
75 memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
81 static void sh_serial_write(void *opaque, hwaddr offs,
82 uint64_t val, unsigned size)
84 sh_serial_state *s = opaque;
88 printf("sh_serial: write offs=0x%02x val=0x%02x\n",
93 s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
99 /* TODO : For SH7751, SCIF mask should be 0xfb. */
100 s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
101 if (!(val & (1 << 5)))
102 s->flags |= SH_SERIAL_FLAG_TEND;
103 if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
104 qemu_set_irq(s->txi, val & (1 << 7));
106 if (!(val & (1 << 6))) {
107 qemu_set_irq(s->rxi, 0);
110 case 0x0c: /* FTDR / TDR */
113 qemu_chr_fe_write(s->chr, &ch, 1);
116 s->flags &= ~SH_SERIAL_FLAG_TDE;
119 case 0x14: /* FRDR / RDR */
124 if (s->feat & SH_SERIAL_FEAT_SCIF) {
127 if (!(val & (1 << 6)))
128 s->flags &= ~SH_SERIAL_FLAG_TEND;
129 if (!(val & (1 << 5)))
130 s->flags &= ~SH_SERIAL_FLAG_TDE;
131 if (!(val & (1 << 4)))
132 s->flags &= ~SH_SERIAL_FLAG_BRK;
133 if (!(val & (1 << 1)))
134 s->flags &= ~SH_SERIAL_FLAG_RDF;
135 if (!(val & (1 << 0)))
136 s->flags &= ~SH_SERIAL_FLAG_DR;
138 if (!(val & (1 << 1)) || !(val & (1 << 0))) {
140 qemu_set_irq(s->rxi, 0);
146 switch ((val >> 6) & 3) {
160 if (val & (1 << 1)) {
161 sh_serial_clear_fifo(s);
166 case 0x20: /* SPTR */
167 s->sptr = val & 0xf3;
184 s->sptr = val & 0x8f;
189 fprintf(stderr, "sh_serial: unsupported write to 0x%02"
190 HWADDR_PRIx "\n", offs);
194 static uint64_t sh_serial_read(void *opaque, hwaddr offs,
197 sh_serial_state *s = opaque;
216 if (s->feat & SH_SERIAL_FEAT_SCIF) {
226 if (s->flags & SH_SERIAL_FLAG_TEND)
228 if (s->flags & SH_SERIAL_FLAG_TDE)
230 if (s->flags & SH_SERIAL_FLAG_BRK)
232 if (s->flags & SH_SERIAL_FLAG_RDF)
234 if (s->flags & SH_SERIAL_FLAG_DR)
237 if (s->scr & (1 << 5))
238 s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
243 ret = s->rx_fifo[s->rx_tail++];
245 if (s->rx_tail == SH_RX_FIFO_LENGTH)
247 if (s->rx_cnt < s->rtrg)
248 s->flags &= ~SH_SERIAL_FLAG_RDF;
286 printf("sh_serial: read offs=0x%02x val=0x%x\n",
290 if (ret & ~((1 << 16) - 1)) {
291 fprintf(stderr, "sh_serial: unsupported read from 0x%02"
292 HWADDR_PRIx "\n", offs);
299 static int sh_serial_can_receive(sh_serial_state *s)
301 return s->scr & (1 << 4);
304 static void sh_serial_receive_break(sh_serial_state *s)
306 if (s->feat & SH_SERIAL_FEAT_SCIF)
310 static int sh_serial_can_receive1(void *opaque)
312 sh_serial_state *s = opaque;
313 return sh_serial_can_receive(s);
316 static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
318 sh_serial_state *s = opaque;
320 if (s->feat & SH_SERIAL_FEAT_SCIF) {
322 for (i = 0; i < size; i++) {
323 if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
324 s->rx_fifo[s->rx_head++] = buf[i];
325 if (s->rx_head == SH_RX_FIFO_LENGTH) {
329 if (s->rx_cnt >= s->rtrg) {
330 s->flags |= SH_SERIAL_FLAG_RDF;
331 if (s->scr & (1 << 6) && s->rxi) {
332 qemu_set_irq(s->rxi, 1);
338 s->rx_fifo[0] = buf[0];
342 static void sh_serial_event(void *opaque, int event)
344 sh_serial_state *s = opaque;
345 if (event == CHR_EVENT_BREAK)
346 sh_serial_receive_break(s);
349 static const MemoryRegionOps sh_serial_ops = {
350 .read = sh_serial_read,
351 .write = sh_serial_write,
352 .endianness = DEVICE_NATIVE_ENDIAN,
355 void sh_serial_init(MemoryRegion *sysmem,
356 hwaddr base, int feat,
357 uint32_t freq, CharDriverState *chr,
366 s = g_malloc0(sizeof(sh_serial_state));
369 s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
374 s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
377 if (feat & SH_SERIAL_FEAT_SCIF) {
384 sh_serial_clear_fifo(s);
386 memory_region_init_io(&s->iomem, &sh_serial_ops, s,
387 "serial", 0x100000000ULL);
389 memory_region_init_alias(&s->iomem_p4, "serial-p4", &s->iomem,
391 memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
393 memory_region_init_alias(&s->iomem_a7, "serial-a7", &s->iomem,
395 memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
400 qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,