hw/s5pc1xx_hsmmc_regs.h

   1 /*
   2  * S5C HS-MMC Controller Constants
   3  *
   4  * Copyright (c) 2009 Samsung Electronics.
   5  * Contributed by Vladimir Monakhov <vladimir.monakhov@ispras.ru>
   6  *
   7  * Based on SMDK6400 MMC (hw/regs-hsmmc.h)
   8  */
   9
  10 #ifndef __ASM_ARCH_REGS_HSMMC_H
  11 #define __ASM_ARCH_REGS_HSMMC_H __FILE__
  12
  13 /*
  14  * HS MMC Interface
  15  */
  16
  17 #define S5C_HSMMC_REG(x)                    (x)
  18
  19 /* R/W SDMA System Address register 0x0 */
  20 #define S5C_HSMMC_SYSAD                     0x00
  21
  22 /* R/W Host DMA Buffer Boundary and Transfer Block Size Register 0x0 */
  23 #define S5C_HSMMC_BLKSIZE                   0x04
  24 #define S5C_HSMMC_MAKE_BLKSZ(dma, bblksz)   (((dma & 0x7) << 12) | (blksz & 0xFFF))
  25
  26 /* R/W Blocks count for current transfer 0x0 */
  27 #define S5C_HSMMC_BLKCNT                    0x06
  28 /* R/W Command Argument Register 0x0 */
  29 #define S5C_HSMMC_ARGUMENT                  0x08
  30
  31 /* R/W Transfer Mode Setting Register 0x0 */
  32 #define S5C_HSMMC_TRNMOD                    0x0C
  33 #define S5C_HSMMC_TRNS_DMA                  0x01
  34 #define S5C_HSMMC_TRNS_BLK_CNT_EN           0x02
  35 #define S5C_HSMMC_TRNS_ACMD12               0x04
  36 #define S5C_HSMMC_TRNS_READ                 0x10
  37 #define S5C_HSMMC_TRNS_MULTI                0x20
  38
  39 #define S5C_HSMMC_TRNS_BOOTCMD              0x1000
  40 #define S5C_HSMMC_TRNS_BOOTACK              0x2000
  41
  42 /* R/W Command Register 0x0 */
  43 #define S5C_HSMMC_CMDREG                    0x0E
  44 /* ROC Response Register 0 0x0 */
  45 #define S5C_HSMMC_RSPREG0                   0x10
  46 /* ROC Response Register 1 0x0 */
  47 #define S5C_HSMMC_RSPREG1                   0x14
  48 /* ROC Response Register 2 0x0 */
  49 #define S5C_HSMMC_RSPREG2                   0x18
  50 /* ROC Response Register 3 0x0 */
  51 #define S5C_HSMMC_RSPREG3                   0x1C
  52 #define S5C_HSMMC_CMD_RESP_MASK             0x03
  53 #define S5C_HSMMC_CMD_CRC                   0x08
  54 #define S5C_HSMMC_CMD_INDEX                 0x10
  55 #define S5C_HSMMC_CMD_DATA                  0x20
  56 #define S5C_HSMMC_CMD_RESP_NONE             0x00
  57 #define S5C_HSMMC_CMD_RESP_LONG             0x01
  58 #define S5C_HSMMC_CMD_RESP_SHORT            0x02
  59 #define S5C_HSMMC_CMD_RESP_SHORT_BUSY       0x03
  60 #define S5C_HSMMC_MAKE_CMD(c, f)            (((c & 0xFF) << 8) | (f & 0xFF))
  61
  62 /* R/W Buffer Data Register 0x0 */
  63 #define S5C_HSMMC_BDATA                     0x20
  64 /* R/ROC Present State Register 0x000A0000 */
  65 #define S5C_HSMMC_PRNSTS                    0x24
  66 #define S5C_HSMMC_CMD_INHIBIT               0x00000001
  67 #define S5C_HSMMC_DATA_INHIBIT              0x00000002
  68 #define S5C_HSMMC_DOING_WRITE               0x00000100
  69 #define S5C_HSMMC_DOING_READ                0x00000200
  70 #define S5C_HSMMC_SPACE_AVAILABLE           0x00000400
  71 #define S5C_HSMMC_DATA_AVAILABLE            0x00000800
  72 #define S5C_HSMMC_CARD_PRESENT              0x00010000
  73 #define S5C_HSMMC_WRITE_PROTECT             0x00080000
  74
  75 /* R/W Present State Register 0x0 */
  76 #define S5C_HSMMC_HOSTCTL                   0x28
  77 #define S5C_HSMMC_CTRL_LED                  0x01
  78 #define S5C_HSMMC_CTRL_4BITBUS              0x02
  79 #define S5C_HSMMC_CTRL_HIGHSPEED            0x04
  80 #define S5C_HSMMC_CTRL_1BIT                 0x00
  81 #define S5C_HSMMC_CTRL_4BIT                 0x02
  82 #define S5C_HSMMC_CTRL_8BIT                 0x20
  83 #define S5C_HSMMC_CTRL_SDMA                 0x00
  84 #define S5C_HSMMC_CTRL_ADMA2_32             0x10
  85
  86 /* R/W Present State Register 0x0 */
  87 #define S5C_HSMMC_PWRCON                    0x29
  88 #define S5C_HSMMC_POWER_OFF                 0x00
  89 #define S5C_HSMMC_POWER_ON                  0x01
  90 #define S5C_HSMMC_POWER_180                 0x0A
  91 #define S5C_HSMMC_POWER_300                 0x0C
  92 #define S5C_HSMMC_POWER_330                 0x0E
  93 #define S5C_HSMMC_POWER_ON_ALL              0xFF
  94
  95 /* R/W Block Gap Control Register 0x0 */
  96 #define S5C_HSMMC_BLKGAP                    0x2A
  97 /* R/W Wakeup Control Register 0x0 */
  98 #define S5C_HSMMC_WAKCON                    0x2B
  99
 100 #define S5C_HSMMC_STAWAKEUP                 0x8
 101
 102 /* R/W Command Register 0x0 */
 103 #define S5C_HSMMC_CLKCON                    0x2C
 104 #define S5C_HSMMC_DIVIDER_SHIFT             0x8
 105 #define S5C_HSMMC_CLOCK_EXT_STABLE          0x8
 106 #define S5C_HSMMC_CLOCK_CARD_EN             0x4
 107 #define S5C_HSMMC_CLOCK_INT_STABLE          0x2
 108 #define S5C_HSMMC_CLOCK_INT_EN              0x1
 109
 110 /* R/W Timeout Control Register 0x0 */
 111 #define S5C_HSMMC_TIMEOUTCON                0x2E
 112 #define S5C_HSMMC_TIMEOUT_MAX               0x0E
 113
 114 /* R/W Software Reset Register 0x0 */
 115 #define S5C_HSMMC_SWRST                     0x2F
 116 #define S5C_HSMMC_RESET_ALL                 0x01
 117 #define S5C_HSMMC_RESET_CMD                 0x02
 118 #define S5C_HSMMC_RESET_DATA                0x04
 119
 120 /* ROC/RW1C Normal Interrupt Status Register 0x0 */
 121 #define S5C_HSMMC_NORINTSTS                 0x30
 122 #define S5C_HSMMC_NIS_ERR                   0x00008000
 123 #define S5C_HSMMC_NIS_CMDCMP                0x00000001
 124 #define S5C_HSMMC_NIS_TRSCMP                0x00000002
 125 #define S5C_HSMMC_NIS_DMA                   0x00000008
 126 #define S5C_HSMMC_NIS_INSERT                0x00000040
 127 #define S5C_HSMMC_NIS_REMOVE                0x00000080
 128
 129 /* ROC/RW1C Error Interrupt Status Register 0x0 */
 130 #define S5C_HSMMC_ERRINTSTS                 0x32
 131 #define S5C_HSMMC_EIS_CMDTIMEOUT            0x00000001
 132 #define S5C_HSMMC_EIS_CMDERR                0x0000000E
 133 #define S5C_HSMMC_EIS_DATATIMEOUT           0x00000010
 134 #define S5C_HSMMC_EIS_DATAERR               0x00000060
 135 #define S5C_HSMMC_EIS_CMD12ERR              0x00000100
 136 #define S5C_HSMMC_EIS_ADMAERR               0x00000200
 137 #define S5C_HSMMC_EIS_STABOOTACKERR         0x00000400
 138
 139 /* R/W Normal Interrupt Status Enable Register 0x0 */
 140 #define S5C_HSMMC_NORINTSTSEN               0x34
 141 /* R/W Error Interrupt Status Enable Register 0x0 */
 142 #define S5C_HSMMC_ERRINTSTSEN               0x36
 143 #define S5C_HSMMC_ENSTABOOTACKERR           0x400
 144
 145 /* R/W Normal Interrupt Signal Enable Register 0x0 */
 146 #define S5C_HSMMC_NORINTSIGEN               0x38
 147 #define S5C_HSMMC_INT_MASK_ALL              0x00
 148 #define S5C_HSMMC_INT_RESPONSE              0x00000001
 149 #define S5C_HSMMC_INT_DATA_END              0x00000002
 150 #define S5C_HSMMC_INT_DMA_END               0x00000008
 151 #define S5C_HSMMC_INT_SPACE_AVAIL           0x00000010
 152 #define S5C_HSMMC_INT_DATA_AVAIL            0x00000020
 153 #define S5C_HSMMC_INT_CARD_INSERT           0x00000040
 154 #define S5C_HSMMC_INT_CARD_REMOVE           0x00000080
 155 #define S5C_HSMMC_INT_CARD_CHANGE           0x000000C0
 156 #define S5C_HSMMC_INT_CARD_INT              0x00000100
 157 #define S5C_HSMMC_INT_TIMEOUT               0x00010000
 158 #define S5C_HSMMC_INT_CRC                   0x00020000
 159 #define S5C_HSMMC_INT_END_BIT               0x00040000
 160 #define S5C_HSMMC_INT_INDEX                 0x00080000
 161 #define S5C_HSMMC_INT_DATA_TIMEOUT          0x00100000
 162 #define S5C_HSMMC_INT_DATA_CRC              0x00200000
 163 #define S5C_HSMMC_INT_DATA_END_BIT          0x00400000
 164 #define S5C_HSMMC_INT_BUS_POWER             0x00800000
 165 #define S5C_HSMMC_INT_ACMD12ERR             0x01000000
 166 #define S5C_HSMMC_INT_ADMAERR               0x02000000
 167
 168 #define S5C_HSMMC_INT_NORMAL_MASK           0x00007FFF
 169 #define S5C_HSMMC_INT_ERROR_MASK            0xFFFF8000
 170
 171 #define S5C_HSMMC_INT_CMD_MASK              (S5C_HSMMC_INT_RESPONSE | \
 172                                              S5C_HSMMC_INT_TIMEOUT | \
 173                                              S5C_HSMMC_INT_CRC | \
 174                                              S5C_HSMMC_INT_END_BIT | \
 175                                              S5C_HSMMC_INT_INDEX | \
 176                                              S5C_HSMMC_NIS_ERR)
 177 #define S5C_HSMMC_INT_DATA_MASK             (S5C_HSMMC_INT_DATA_END | \
 178                                              S5C_HSMMC_INT_DMA_END | \
 179                                              S5C_HSMMC_INT_DATA_AVAIL | \
 180                                              S5C_HSMMC_INT_SPACE_AVAIL | \
 181                                              S5C_HSMMC_INT_DATA_TIMEOUT | \
 182                                              S5C_HSMMC_INT_DATA_CRC | \
 183                                              S5C_HSMMC_INT_DATA_END_BIT)
 184
 185 /* R/W Error Interrupt Signal Enable Register 0x0 */
 186 #define S5C_HSMMC_ERRINTSIGEN               0x3A
 187 #define S5C_HSMMC_ENSIGBOOTACKERR           0x400
 188
 189 /* ROC Auto CMD12 error status register 0x0 */
 190 #define S5C_HSMMC_ACMD12ERRSTS              0x3C
 191
 192 /* HWInit Capabilities Register 0x05E80080 */
 193 #define S5C_HSMMC_CAPAREG                   0x40
 194 #define S5C_HSMMC_TIMEOUT_CLK_MASK          0x0000003F
 195 #define S5C_HSMMC_TIMEOUT_CLK_SHIFT         0x0
 196 #define S5C_HSMMC_TIMEOUT_CLK_UNIT          0x00000080
 197 #define S5C_HSMMC_CLOCK_BASE_MASK           0x00003F00
 198 #define S5C_HSMMC_CLOCK_BASE_SHIFT          0x8
 199 #define S5C_HSMMC_MAX_BLOCK_MASK            0x00030000
 200 #define S5C_HSMMC_MAX_BLOCK_SHIFT           0x10
 201 #define S5C_HSMMC_CAN_DO_DMA                0x00400000
 202 #define S5C_HSMMC_CAN_DO_ADMA2              0x00080000
 203 #define S5C_HSMMC_CAN_VDD_330               0x01000000
 204 #define S5C_HSMMC_CAN_VDD_300               0x02000000
 205 #define S5C_HSMMC_CAN_VDD_180               0x04000000
 206
 207 /* HWInit Maximum Current Capabilities Register 0x0 */
 208 #define S5C_HSMMC_MAXCURR                   0x48
 209
 210 /* For ADMA2 */
 211
 212 /* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */
 213 #define S5C_HSMMC_FEAER                     0x50
 214 /* W Force Event Error Interrupt Register Error Interrupt 0x0000 */
 215 #define S5C_HSMMC_FEERR                     0x52
 216
 217 /* R/W ADMA Error Status Register 0x00 */
 218 #define S5C_HSMMC_ADMAERR                   0x54
 219 #define S5C_HSMMC_ADMAERR_CONTINUE_REQUEST  (1 << 9)
 220 #define S5C_HSMMC_ADMAERR_INTRRUPT_STATUS   (1 << 8)
 221 #define S5C_HSMMC_ADMAERR_LENGTH_MISMATCH   (1 << 2)
 222 #define S5C_HSMMC_ADMAERR_STATE_ST_STOP     (0 << 0)
 223 #define S5C_HSMMC_ADMAERR_STATE_ST_FDS      (1 << 0)
 224 #define S5C_HSMMC_ADMAERR_STATE_ST_TFR      (3 << 0)
 225
 226 /* R/W ADMA System Address Register 0x00 */
 227 #define S5C_HSMMC_ADMASYSADDR               0x58
 228 #define S5C_HSMMC_ADMA_ATTR_MSK             0x3F
 229 #define S5C_HSMMC_ADMA_ATTR_ACT_NOP         (0 << 4)
 230 #define S5C_HSMMC_ADMA_ATTR_ACT_RSV         (1 << 4)
 231 #define S5C_HSMMC_ADMA_ATTR_ACT_TRAN        (2 << 4)
 232 #define S5C_HSMMC_ADMA_ATTR_ACT_LINK        (3 << 4)
 233 #define S5C_HSMMC_ADMA_ATTR_INT             (1 << 2)
 234 #define S5C_HSMMC_ADMA_ATTR_END             (1 << 1)
 235 #define S5C_HSMMC_ADMA_ATTR_VALID           (1 << 0)
 236
 237 /* R/W Control register 2 0x0 */
 238 #define S5C_HSMMC_CONTROL2                  0x80
 239 /* R/W FIFO Interrupt Control (Control Register 3) 0x7F5F3F1F */
 240 #define S5C_HSMMC_CONTROL3                  0x84
 241 /* R/W Control register 4 0x0 */
 242 #define S5C_HSMMC_CONTROL4                  0x8C
 243
 244
 245 /* Magic register which is used from kernel! */
 246 #define S5C_HSMMC_SLOT_INT_STATUS           0xFC
 247
 248
 249 /* HWInit Host Controller Version Register 0x0401 */
 250 #define S5C_HSMMC_HCVER                     0xFE
 251 #define S5C_HSMMC_VENDOR_VER_MASK           0xFF00
 252 #define S5C_HSMMC_VENDOR_VER_SHIFT          0x8
 253 #define S5C_HSMMC_SPEC_VER_MASK             0x00FF
 254 #define S5C_HSMMC_SPEC_VER_SHIFT            0x0
 255
 256 #define S5C_HSMMC_REG_SIZE                  0x100
 257
 258 #endif /* __ASM_ARCH_REGS_HSMMC_H */