4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/pci/pci.h"
26 #include "hw/pci/pci_bridge.h"
27 #include "hw/pci/pci_bus.h"
28 #include "monitor/monitor.h"
30 #include "sysemu/sysemu.h"
31 #include "hw/loader.h"
32 #include "qemu/range.h"
33 #include "qmp-commands.h"
34 #include "hw/pci/msi.h"
35 #include "hw/pci/msix.h"
36 #include "exec/address-spaces.h"
40 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
42 # define PCI_DPRINTF(format, ...) do { } while (0)
45 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
46 static char *pcibus_get_dev_path(DeviceState *dev);
47 static char *pcibus_get_fw_dev_path(DeviceState *dev);
48 static int pcibus_reset(BusState *qbus);
50 static Property pci_props[] = {
51 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
52 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
53 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
54 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
55 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
56 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
57 QEMU_PCI_CAP_SERR_BITNR, true),
58 DEFINE_PROP_END_OF_LIST()
61 static void pci_bus_class_init(ObjectClass *klass, void *data)
63 BusClass *k = BUS_CLASS(klass);
65 k->print_dev = pcibus_dev_print;
66 k->get_dev_path = pcibus_get_dev_path;
67 k->get_fw_dev_path = pcibus_get_fw_dev_path;
68 k->reset = pcibus_reset;
71 static const TypeInfo pci_bus_info = {
74 .instance_size = sizeof(PCIBus),
75 .class_init = pci_bus_class_init,
78 static const TypeInfo pcie_bus_info = {
79 .name = TYPE_PCIE_BUS,
80 .parent = TYPE_PCI_BUS,
83 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
84 static void pci_update_mappings(PCIDevice *d);
85 static void pci_set_irq(void *opaque, int irq_num, int level);
86 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
87 static void pci_del_option_rom(PCIDevice *pdev);
89 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
90 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
95 QLIST_ENTRY(PCIHostBus) next;
97 static QLIST_HEAD(, PCIHostBus) host_buses;
99 static const VMStateDescription vmstate_pcibus = {
102 .minimum_version_id = 1,
103 .minimum_version_id_old = 1,
104 .fields = (VMStateField []) {
105 VMSTATE_INT32_EQUAL(nirq, PCIBus),
106 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
107 VMSTATE_END_OF_LIST()
110 static int pci_bar(PCIDevice *d, int reg)
114 if (reg != PCI_ROM_SLOT)
115 return PCI_BASE_ADDRESS_0 + reg * 4;
117 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
118 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
121 static inline int pci_irq_state(PCIDevice *d, int irq_num)
123 return (d->irq_state >> irq_num) & 0x1;
126 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
128 d->irq_state &= ~(0x1 << irq_num);
129 d->irq_state |= level << irq_num;
132 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
137 irq_num = bus->map_irq(pci_dev, irq_num);
140 pci_dev = bus->parent_dev;
142 bus->irq_count[irq_num] += change;
143 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
146 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
148 assert(irq_num >= 0);
149 assert(irq_num < bus->nirq);
150 return !!bus->irq_count[irq_num];
153 /* Update interrupt status bit in config space on interrupt
155 static void pci_update_irq_status(PCIDevice *dev)
157 if (dev->irq_state) {
158 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
160 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
164 void pci_device_deassert_intx(PCIDevice *dev)
167 for (i = 0; i < PCI_NUM_PINS; ++i) {
168 qemu_set_irq(dev->irq[i], 0);
173 * This function is called on #RST and FLR.
174 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
176 void pci_device_reset(PCIDevice *dev)
180 qdev_reset_all(&dev->qdev);
183 pci_update_irq_status(dev);
184 pci_device_deassert_intx(dev);
185 /* Clear all writable bits */
186 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
187 pci_get_word(dev->wmask + PCI_COMMAND) |
188 pci_get_word(dev->w1cmask + PCI_COMMAND));
189 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
190 pci_get_word(dev->wmask + PCI_STATUS) |
191 pci_get_word(dev->w1cmask + PCI_STATUS));
192 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
193 dev->config[PCI_INTERRUPT_LINE] = 0x0;
194 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
195 PCIIORegion *region = &dev->io_regions[r];
200 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
201 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
202 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
204 pci_set_long(dev->config + pci_bar(dev, r), region->type);
207 pci_update_mappings(dev);
214 * Trigger pci bus reset under a given bus.
215 * To be called on RST# assert.
217 void pci_bus_reset(PCIBus *bus)
221 for (i = 0; i < bus->nirq; i++) {
222 bus->irq_count[i] = 0;
224 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
225 if (bus->devices[i]) {
226 pci_device_reset(bus->devices[i]);
231 static int pcibus_reset(BusState *qbus)
233 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
235 /* topology traverse is done by pci_bus_reset().
236 Tell qbus/qdev walker not to traverse the tree */
240 static void pci_host_bus_register(int domain, PCIBus *bus)
242 struct PCIHostBus *host;
243 host = g_malloc0(sizeof(*host));
244 host->domain = domain;
246 QLIST_INSERT_HEAD(&host_buses, host, next);
249 PCIBus *pci_find_root_bus(int domain)
251 struct PCIHostBus *host;
253 QLIST_FOREACH(host, &host_buses, next) {
254 if (host->domain == domain) {
262 int pci_find_domain(const PCIBus *bus)
265 struct PCIHostBus *host;
267 /* obtain root bus */
268 while ((d = bus->parent_dev) != NULL) {
272 QLIST_FOREACH(host, &host_buses, next) {
273 if (host->bus == bus) {
278 abort(); /* should not be reached */
282 static void pci_bus_init(PCIBus *bus, DeviceState *parent,
284 MemoryRegion *address_space_mem,
285 MemoryRegion *address_space_io,
288 assert(PCI_FUNC(devfn_min) == 0);
289 bus->devfn_min = devfn_min;
290 bus->address_space_mem = address_space_mem;
291 bus->address_space_io = address_space_io;
294 QLIST_INIT(&bus->child);
295 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
297 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
300 bool pci_bus_is_express(PCIBus *bus)
302 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
305 bool pci_bus_is_root(PCIBus *bus)
307 return !bus->parent_dev;
310 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
312 MemoryRegion *address_space_mem,
313 MemoryRegion *address_space_io,
314 uint8_t devfn_min, const char *typename)
316 qbus_create_inplace(bus, typename, parent, name);
317 pci_bus_init(bus, parent, name, address_space_mem,
318 address_space_io, devfn_min);
321 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
322 MemoryRegion *address_space_mem,
323 MemoryRegion *address_space_io,
324 uint8_t devfn_min, const char *typename)
328 bus = PCI_BUS(qbus_create(typename, parent, name));
329 pci_bus_init(bus, parent, name, address_space_mem,
330 address_space_io, devfn_min);
334 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
335 void *irq_opaque, int nirq)
337 bus->set_irq = set_irq;
338 bus->map_irq = map_irq;
339 bus->irq_opaque = irq_opaque;
341 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
344 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
346 bus->qbus.allow_hotplug = 1;
347 bus->hotplug = hotplug;
348 bus->hotplug_qdev = qdev;
351 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
352 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
354 MemoryRegion *address_space_mem,
355 MemoryRegion *address_space_io,
356 uint8_t devfn_min, int nirq, const char *typename)
360 bus = pci_bus_new(parent, name, address_space_mem,
361 address_space_io, devfn_min, typename);
362 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
366 int pci_bus_num(PCIBus *s)
368 if (pci_bus_is_root(s))
369 return 0; /* pci host bridge */
370 return s->parent_dev->config[PCI_SECONDARY_BUS];
373 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
375 PCIDevice *s = container_of(pv, PCIDevice, config);
379 assert(size == pci_config_size(s));
380 config = g_malloc(size);
382 qemu_get_buffer(f, config, size);
383 for (i = 0; i < size; ++i) {
384 if ((config[i] ^ s->config[i]) &
385 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
390 memcpy(s->config, config, size);
392 pci_update_mappings(s);
394 memory_region_set_enabled(&s->bus_master_enable_region,
395 pci_get_word(s->config + PCI_COMMAND)
396 & PCI_COMMAND_MASTER);
402 /* just put buffer */
403 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
405 const uint8_t **v = pv;
406 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
407 qemu_put_buffer(f, *v, size);
410 static VMStateInfo vmstate_info_pci_config = {
411 .name = "pci config",
412 .get = get_pci_config_device,
413 .put = put_pci_config_device,
416 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
418 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
419 uint32_t irq_state[PCI_NUM_PINS];
421 for (i = 0; i < PCI_NUM_PINS; ++i) {
422 irq_state[i] = qemu_get_be32(f);
423 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
424 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
430 for (i = 0; i < PCI_NUM_PINS; ++i) {
431 pci_set_irq_state(s, i, irq_state[i]);
437 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
440 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
442 for (i = 0; i < PCI_NUM_PINS; ++i) {
443 qemu_put_be32(f, pci_irq_state(s, i));
447 static VMStateInfo vmstate_info_pci_irq_state = {
448 .name = "pci irq state",
449 .get = get_pci_irq_state,
450 .put = put_pci_irq_state,
453 const VMStateDescription vmstate_pci_device = {
456 .minimum_version_id = 1,
457 .minimum_version_id_old = 1,
458 .fields = (VMStateField []) {
459 VMSTATE_INT32_LE(version_id, PCIDevice),
460 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
461 vmstate_info_pci_config,
462 PCI_CONFIG_SPACE_SIZE),
463 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
464 vmstate_info_pci_irq_state,
465 PCI_NUM_PINS * sizeof(int32_t)),
466 VMSTATE_END_OF_LIST()
470 const VMStateDescription vmstate_pcie_device = {
471 .name = "PCIEDevice",
473 .minimum_version_id = 1,
474 .minimum_version_id_old = 1,
475 .fields = (VMStateField []) {
476 VMSTATE_INT32_LE(version_id, PCIDevice),
477 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
478 vmstate_info_pci_config,
479 PCIE_CONFIG_SPACE_SIZE),
480 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
481 vmstate_info_pci_irq_state,
482 PCI_NUM_PINS * sizeof(int32_t)),
483 VMSTATE_END_OF_LIST()
487 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
489 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
492 void pci_device_save(PCIDevice *s, QEMUFile *f)
494 /* Clear interrupt status bit: it is implicit
495 * in irq_state which we are saving.
496 * This makes us compatible with old devices
497 * which never set or clear this bit. */
498 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
499 vmstate_save_state(f, pci_get_vmstate(s), s);
500 /* Restore the interrupt status bit. */
501 pci_update_irq_status(s);
504 int pci_device_load(PCIDevice *s, QEMUFile *f)
507 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
508 /* Restore the interrupt status bit. */
509 pci_update_irq_status(s);
513 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
515 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
516 pci_default_sub_vendor_id);
517 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
518 pci_default_sub_device_id);
522 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
523 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
525 static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
526 unsigned int *slotp, unsigned int *funcp)
531 unsigned long dom = 0, bus = 0;
532 unsigned int slot = 0;
533 unsigned int func = 0;
536 val = strtoul(p, &e, 16);
542 val = strtoul(p, &e, 16);
549 val = strtoul(p, &e, 16);
562 val = strtoul(p, &e, 16);
569 /* if funcp == NULL func is 0 */
570 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
584 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
587 /* strip legacy tag */
588 if (!strncmp(addr, "pci_addr=", 9)) {
591 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
592 monitor_printf(mon, "Invalid pci address\n");
598 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
605 return pci_find_bus_nr(pci_find_root_bus(0), 0);
608 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
612 *devfnp = PCI_DEVFN(slot, 0);
613 return pci_find_bus_nr(pci_find_root_bus(dom), bus);
616 static void pci_init_cmask(PCIDevice *dev)
618 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
619 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
620 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
621 dev->cmask[PCI_REVISION_ID] = 0xff;
622 dev->cmask[PCI_CLASS_PROG] = 0xff;
623 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
624 dev->cmask[PCI_HEADER_TYPE] = 0xff;
625 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
628 static void pci_init_wmask(PCIDevice *dev)
630 int config_size = pci_config_size(dev);
632 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
633 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
634 pci_set_word(dev->wmask + PCI_COMMAND,
635 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
636 PCI_COMMAND_INTX_DISABLE);
637 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
638 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
641 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
642 config_size - PCI_CONFIG_HEADER_SIZE);
645 static void pci_init_w1cmask(PCIDevice *dev)
648 * Note: It's okay to set w1cmask even for readonly bits as
649 * long as their value is hardwired to 0.
651 pci_set_word(dev->w1cmask + PCI_STATUS,
652 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
653 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
654 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
657 static void pci_init_mask_bridge(PCIDevice *d)
659 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
660 PCI_SEC_LETENCY_TIMER */
661 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
664 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
665 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
666 pci_set_word(d->wmask + PCI_MEMORY_BASE,
667 PCI_MEMORY_RANGE_MASK & 0xffff);
668 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
669 PCI_MEMORY_RANGE_MASK & 0xffff);
670 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
671 PCI_PREF_RANGE_MASK & 0xffff);
672 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
673 PCI_PREF_RANGE_MASK & 0xffff);
675 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
676 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
678 /* Supported memory and i/o types */
679 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
680 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
681 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
682 PCI_PREF_RANGE_TYPE_64);
683 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
684 PCI_PREF_RANGE_TYPE_64);
687 * TODO: Bridges default to 10-bit VGA decoding but we currently only
688 * implement 16-bit decoding (no alias support).
690 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
691 PCI_BRIDGE_CTL_PARITY |
692 PCI_BRIDGE_CTL_SERR |
695 PCI_BRIDGE_CTL_VGA_16BIT |
696 PCI_BRIDGE_CTL_MASTER_ABORT |
697 PCI_BRIDGE_CTL_BUS_RESET |
698 PCI_BRIDGE_CTL_FAST_BACK |
699 PCI_BRIDGE_CTL_DISCARD |
700 PCI_BRIDGE_CTL_SEC_DISCARD |
701 PCI_BRIDGE_CTL_DISCARD_SERR);
702 /* Below does not do anything as we never set this bit, put here for
704 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
705 PCI_BRIDGE_CTL_DISCARD_STATUS);
706 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
707 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
708 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
709 PCI_PREF_RANGE_TYPE_MASK);
710 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
711 PCI_PREF_RANGE_TYPE_MASK);
714 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
716 uint8_t slot = PCI_SLOT(dev->devfn);
719 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
720 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
724 * multifunction bit is interpreted in two ways as follows.
725 * - all functions must set the bit to 1.
727 * - function 0 must set the bit, but the rest function (> 0)
728 * is allowed to leave the bit to 0.
729 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
731 * So OS (at least Linux) checks the bit of only function 0,
732 * and doesn't see the bit of function > 0.
734 * The below check allows both interpretation.
736 if (PCI_FUNC(dev->devfn)) {
737 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
738 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
739 /* function 0 should set multifunction bit */
740 error_report("PCI: single function device can't be populated "
741 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
747 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
750 /* function 0 indicates single function, so function > 0 must be NULL */
751 for (func = 1; func < PCI_FUNC_MAX; ++func) {
752 if (bus->devices[PCI_DEVFN(slot, func)]) {
753 error_report("PCI: %x.0 indicates single function, "
754 "but %x.%x is already populated.",
762 static void pci_config_alloc(PCIDevice *pci_dev)
764 int config_size = pci_config_size(pci_dev);
766 pci_dev->config = g_malloc0(config_size);
767 pci_dev->cmask = g_malloc0(config_size);
768 pci_dev->wmask = g_malloc0(config_size);
769 pci_dev->w1cmask = g_malloc0(config_size);
770 pci_dev->used = g_malloc0(config_size);
773 static void pci_config_free(PCIDevice *pci_dev)
775 g_free(pci_dev->config);
776 g_free(pci_dev->cmask);
777 g_free(pci_dev->wmask);
778 g_free(pci_dev->w1cmask);
779 g_free(pci_dev->used);
782 /* -1 for devfn means auto assign */
783 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
784 const char *name, int devfn)
786 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
787 PCIConfigReadFunc *config_read = pc->config_read;
788 PCIConfigWriteFunc *config_write = pc->config_write;
791 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
792 devfn += PCI_FUNC_MAX) {
793 if (!bus->devices[devfn])
796 error_report("PCI: no slot/function available for %s, all in use", name);
799 } else if (bus->devices[devfn]) {
800 error_report("PCI: slot %d function %d not available for %s, in use by %s",
801 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
805 if (bus->dma_context_fn) {
806 pci_dev->dma = bus->dma_context_fn(bus, bus->dma_context_opaque, devfn);
808 /* FIXME: Make dma_context_fn use MemoryRegions instead, so this path is
809 * taken unconditionally */
810 /* FIXME: inherit memory region from bus creator */
811 memory_region_init_alias(&pci_dev->bus_master_enable_region, "bus master",
812 get_system_memory(), 0,
813 memory_region_size(get_system_memory()));
814 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
815 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region);
816 pci_dev->dma = g_new(DMAContext, 1);
817 dma_context_init(pci_dev->dma, &pci_dev->bus_master_as, NULL, NULL, NULL);
819 pci_dev->devfn = devfn;
820 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
821 pci_dev->irq_state = 0;
822 pci_config_alloc(pci_dev);
824 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
825 pci_config_set_device_id(pci_dev->config, pc->device_id);
826 pci_config_set_revision(pci_dev->config, pc->revision);
827 pci_config_set_class(pci_dev->config, pc->class_id);
829 if (!pc->is_bridge) {
830 if (pc->subsystem_vendor_id || pc->subsystem_id) {
831 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
832 pc->subsystem_vendor_id);
833 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
836 pci_set_default_subsystem_id(pci_dev);
839 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
840 assert(!pc->subsystem_vendor_id);
841 assert(!pc->subsystem_id);
843 pci_init_cmask(pci_dev);
844 pci_init_wmask(pci_dev);
845 pci_init_w1cmask(pci_dev);
847 pci_init_mask_bridge(pci_dev);
849 if (pci_init_multifunction(bus, pci_dev)) {
850 pci_config_free(pci_dev);
855 config_read = pci_default_read_config;
857 config_write = pci_default_write_config;
858 pci_dev->config_read = config_read;
859 pci_dev->config_write = config_write;
860 bus->devices[devfn] = pci_dev;
861 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
862 pci_dev->version_id = 2; /* Current pci device vmstate version */
866 static void do_pci_unregister_device(PCIDevice *pci_dev)
868 qemu_free_irqs(pci_dev->irq);
869 pci_dev->bus->devices[pci_dev->devfn] = NULL;
870 pci_config_free(pci_dev);
872 if (!pci_dev->bus->dma_context_fn) {
873 address_space_destroy(&pci_dev->bus_master_as);
874 memory_region_destroy(&pci_dev->bus_master_enable_region);
875 g_free(pci_dev->dma);
880 static void pci_unregister_io_regions(PCIDevice *pci_dev)
885 for(i = 0; i < PCI_NUM_REGIONS; i++) {
886 r = &pci_dev->io_regions[i];
887 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
889 memory_region_del_subregion(r->address_space, r->memory);
892 pci_unregister_vga(pci_dev);
895 static int pci_unregister_device(DeviceState *dev)
897 PCIDevice *pci_dev = PCI_DEVICE(dev);
898 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
900 pci_unregister_io_regions(pci_dev);
901 pci_del_option_rom(pci_dev);
907 do_pci_unregister_device(pci_dev);
911 void pci_register_bar(PCIDevice *pci_dev, int region_num,
912 uint8_t type, MemoryRegion *memory)
917 pcibus_t size = memory_region_size(memory);
919 assert(region_num >= 0);
920 assert(region_num < PCI_NUM_REGIONS);
921 if (size & (size-1)) {
922 fprintf(stderr, "ERROR: PCI region size must be pow2 "
923 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
927 r = &pci_dev->io_regions[region_num];
928 r->addr = PCI_BAR_UNMAPPED;
934 addr = pci_bar(pci_dev, region_num);
935 if (region_num == PCI_ROM_SLOT) {
936 /* ROM enable bit is writable */
937 wmask |= PCI_ROM_ADDRESS_ENABLE;
939 pci_set_long(pci_dev->config + addr, type);
940 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
941 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
942 pci_set_quad(pci_dev->wmask + addr, wmask);
943 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
945 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
946 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
948 pci_dev->io_regions[region_num].memory = memory;
949 pci_dev->io_regions[region_num].address_space
950 = type & PCI_BASE_ADDRESS_SPACE_IO
951 ? pci_dev->bus->address_space_io
952 : pci_dev->bus->address_space_mem;
955 static void pci_update_vga(PCIDevice *pci_dev)
959 if (!pci_dev->has_vga) {
963 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
965 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
966 cmd & PCI_COMMAND_MEMORY);
967 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
968 cmd & PCI_COMMAND_IO);
969 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
970 cmd & PCI_COMMAND_IO);
973 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
974 MemoryRegion *io_lo, MemoryRegion *io_hi)
976 assert(!pci_dev->has_vga);
978 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
979 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
980 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
981 QEMU_PCI_VGA_MEM_BASE, mem, 1);
983 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
984 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
985 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
986 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
988 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
989 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
990 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
991 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
992 pci_dev->has_vga = true;
994 pci_update_vga(pci_dev);
997 void pci_unregister_vga(PCIDevice *pci_dev)
999 if (!pci_dev->has_vga) {
1003 memory_region_del_subregion(pci_dev->bus->address_space_mem,
1004 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1005 memory_region_del_subregion(pci_dev->bus->address_space_io,
1006 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1007 memory_region_del_subregion(pci_dev->bus->address_space_io,
1008 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1009 pci_dev->has_vga = false;
1012 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1014 return pci_dev->io_regions[region_num].addr;
1017 static pcibus_t pci_bar_address(PCIDevice *d,
1018 int reg, uint8_t type, pcibus_t size)
1020 pcibus_t new_addr, last_addr;
1021 int bar = pci_bar(d, reg);
1022 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1024 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1025 if (!(cmd & PCI_COMMAND_IO)) {
1026 return PCI_BAR_UNMAPPED;
1028 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1029 last_addr = new_addr + size - 1;
1030 /* NOTE: we have only 64K ioports on PC */
1031 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
1032 return PCI_BAR_UNMAPPED;
1037 if (!(cmd & PCI_COMMAND_MEMORY)) {
1038 return PCI_BAR_UNMAPPED;
1040 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1041 new_addr = pci_get_quad(d->config + bar);
1043 new_addr = pci_get_long(d->config + bar);
1045 /* the ROM slot has a specific enable bit */
1046 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1047 return PCI_BAR_UNMAPPED;
1049 new_addr &= ~(size - 1);
1050 last_addr = new_addr + size - 1;
1051 /* NOTE: we do not support wrapping */
1052 /* XXX: as we cannot support really dynamic
1053 mappings, we handle specific values as invalid
1055 if (last_addr <= new_addr || new_addr == 0 ||
1056 last_addr == PCI_BAR_UNMAPPED) {
1057 return PCI_BAR_UNMAPPED;
1060 /* Now pcibus_t is 64bit.
1061 * Check if 32 bit BAR wraps around explicitly.
1062 * Without this, PC ide doesn't work well.
1063 * TODO: remove this work around.
1065 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1066 return PCI_BAR_UNMAPPED;
1070 * OS is allowed to set BAR beyond its addressable
1071 * bits. For example, 32 bit OS can set 64bit bar
1072 * to >4G. Check it. TODO: we might need to support
1073 * it in the future for e.g. PAE.
1075 if (last_addr >= HWADDR_MAX) {
1076 return PCI_BAR_UNMAPPED;
1082 static void pci_update_mappings(PCIDevice *d)
1088 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1089 r = &d->io_regions[i];
1091 /* this region isn't registered */
1095 new_addr = pci_bar_address(d, i, r->type, r->size);
1097 /* This bar isn't changed */
1098 if (new_addr == r->addr)
1101 /* now do the real mapping */
1102 if (r->addr != PCI_BAR_UNMAPPED) {
1103 memory_region_del_subregion(r->address_space, r->memory);
1106 if (r->addr != PCI_BAR_UNMAPPED) {
1107 memory_region_add_subregion_overlap(r->address_space,
1108 r->addr, r->memory, 1);
1115 static inline int pci_irq_disabled(PCIDevice *d)
1117 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1120 /* Called after interrupt disabled field update in config space,
1121 * assert/deassert interrupts if necessary.
1122 * Gets original interrupt disable bit value (before update). */
1123 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1125 int i, disabled = pci_irq_disabled(d);
1126 if (disabled == was_irq_disabled)
1128 for (i = 0; i < PCI_NUM_PINS; ++i) {
1129 int state = pci_irq_state(d, i);
1130 pci_change_irq_level(d, i, disabled ? -state : state);
1134 uint32_t pci_default_read_config(PCIDevice *d,
1135 uint32_t address, int len)
1139 memcpy(&val, d->config + address, len);
1140 return le32_to_cpu(val);
1143 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1145 int i, was_irq_disabled = pci_irq_disabled(d);
1147 for (i = 0; i < l; val >>= 8, ++i) {
1148 uint8_t wmask = d->wmask[addr + i];
1149 uint8_t w1cmask = d->w1cmask[addr + i];
1150 assert(!(wmask & w1cmask));
1151 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1152 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1154 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1155 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1156 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1157 range_covers_byte(addr, l, PCI_COMMAND))
1158 pci_update_mappings(d);
1160 if (range_covers_byte(addr, l, PCI_COMMAND)) {
1161 pci_update_irq_disabled(d, was_irq_disabled);
1162 memory_region_set_enabled(&d->bus_master_enable_region,
1163 pci_get_word(d->config + PCI_COMMAND)
1164 & PCI_COMMAND_MASTER);
1167 msi_write_config(d, addr, val, l);
1168 msix_write_config(d, addr, val, l);
1171 /***********************************************************/
1172 /* generic PCI irq support */
1174 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1175 static void pci_set_irq(void *opaque, int irq_num, int level)
1177 PCIDevice *pci_dev = opaque;
1180 change = level - pci_irq_state(pci_dev, irq_num);
1184 pci_set_irq_state(pci_dev, irq_num, level);
1185 pci_update_irq_status(pci_dev);
1186 if (pci_irq_disabled(pci_dev))
1188 pci_change_irq_level(pci_dev, irq_num, change);
1191 /* Special hooks used by device assignment */
1192 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1194 assert(pci_bus_is_root(bus));
1195 bus->route_intx_to_irq = route_intx_to_irq;
1198 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1204 pin = bus->map_irq(dev, pin);
1205 dev = bus->parent_dev;
1208 if (!bus->route_intx_to_irq) {
1209 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1210 object_get_typename(OBJECT(bus->qbus.parent)));
1211 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1214 return bus->route_intx_to_irq(bus->irq_opaque, pin);
1217 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1219 return old->mode != new->mode || old->irq != new->irq;
1222 void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1228 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1229 dev = bus->devices[i];
1230 if (dev && dev->intx_routing_notifier) {
1231 dev->intx_routing_notifier(dev);
1235 QLIST_FOREACH(sec, &bus->child, sibling) {
1236 pci_bus_fire_intx_routing_notifier(sec);
1240 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1241 PCIINTxRoutingNotifier notifier)
1243 dev->intx_routing_notifier = notifier;
1247 * PCI-to-PCI bridge specification
1248 * 9.1: Interrupt routing. Table 9-1
1250 * the PCI Express Base Specification, Revision 2.1
1251 * 2.2.8.1: INTx interrutp signaling - Rules
1252 * the Implementation Note
1256 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1257 * 0-origin unlike PCI interrupt pin register.
1259 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1261 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1264 /***********************************************************/
1265 /* monitor info on PCI */
1270 const char *fw_name;
1271 uint16_t fw_ign_bits;
1274 static const pci_class_desc pci_class_descriptions[] =
1276 { 0x0001, "VGA controller", "display"},
1277 { 0x0100, "SCSI controller", "scsi"},
1278 { 0x0101, "IDE controller", "ide"},
1279 { 0x0102, "Floppy controller", "fdc"},
1280 { 0x0103, "IPI controller", "ipi"},
1281 { 0x0104, "RAID controller", "raid"},
1282 { 0x0106, "SATA controller"},
1283 { 0x0107, "SAS controller"},
1284 { 0x0180, "Storage controller"},
1285 { 0x0200, "Ethernet controller", "ethernet"},
1286 { 0x0201, "Token Ring controller", "token-ring"},
1287 { 0x0202, "FDDI controller", "fddi"},
1288 { 0x0203, "ATM controller", "atm"},
1289 { 0x0280, "Network controller"},
1290 { 0x0300, "VGA controller", "display", 0x00ff},
1291 { 0x0301, "XGA controller"},
1292 { 0x0302, "3D controller"},
1293 { 0x0380, "Display controller"},
1294 { 0x0400, "Video controller", "video"},
1295 { 0x0401, "Audio controller", "sound"},
1297 { 0x0403, "Audio controller", "sound"},
1298 { 0x0480, "Multimedia controller"},
1299 { 0x0500, "RAM controller", "memory"},
1300 { 0x0501, "Flash controller", "flash"},
1301 { 0x0580, "Memory controller"},
1302 { 0x0600, "Host bridge", "host"},
1303 { 0x0601, "ISA bridge", "isa"},
1304 { 0x0602, "EISA bridge", "eisa"},
1305 { 0x0603, "MC bridge", "mca"},
1306 { 0x0604, "PCI bridge", "pci"},
1307 { 0x0605, "PCMCIA bridge", "pcmcia"},
1308 { 0x0606, "NUBUS bridge", "nubus"},
1309 { 0x0607, "CARDBUS bridge", "cardbus"},
1310 { 0x0608, "RACEWAY bridge"},
1311 { 0x0680, "Bridge"},
1312 { 0x0700, "Serial port", "serial"},
1313 { 0x0701, "Parallel port", "parallel"},
1314 { 0x0800, "Interrupt controller", "interrupt-controller"},
1315 { 0x0801, "DMA controller", "dma-controller"},
1316 { 0x0802, "Timer", "timer"},
1317 { 0x0803, "RTC", "rtc"},
1318 { 0x0900, "Keyboard", "keyboard"},
1319 { 0x0901, "Pen", "pen"},
1320 { 0x0902, "Mouse", "mouse"},
1321 { 0x0A00, "Dock station", "dock", 0x00ff},
1322 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1323 { 0x0c00, "Fireware contorller", "fireware"},
1324 { 0x0c01, "Access bus controller", "access-bus"},
1325 { 0x0c02, "SSA controller", "ssa"},
1326 { 0x0c03, "USB controller", "usb"},
1327 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1332 static void pci_for_each_device_under_bus(PCIBus *bus,
1333 void (*fn)(PCIBus *b, PCIDevice *d,
1340 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1341 d = bus->devices[devfn];
1348 void pci_for_each_device(PCIBus *bus, int bus_num,
1349 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1352 bus = pci_find_bus_nr(bus, bus_num);
1355 pci_for_each_device_under_bus(bus, fn, opaque);
1359 static const pci_class_desc *get_class_desc(int class)
1361 const pci_class_desc *desc;
1363 desc = pci_class_descriptions;
1364 while (desc->desc && class != desc->class) {
1371 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1373 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1375 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1378 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1379 const PCIIORegion *r = &dev->io_regions[i];
1380 PciMemoryRegionList *region;
1386 region = g_malloc0(sizeof(*region));
1387 region->value = g_malloc0(sizeof(*region->value));
1389 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1390 region->value->type = g_strdup("io");
1392 region->value->type = g_strdup("memory");
1393 region->value->has_prefetch = true;
1394 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1395 region->value->has_mem_type_64 = true;
1396 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1399 region->value->bar = i;
1400 region->value->address = r->addr;
1401 region->value->size = r->size;
1403 /* XXX: waiting for the qapi to support GSList */
1405 head = cur_item = region;
1407 cur_item->next = region;
1415 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1418 PciBridgeInfo *info;
1420 info = g_malloc0(sizeof(*info));
1422 info->bus.number = dev->config[PCI_PRIMARY_BUS];
1423 info->bus.secondary = dev->config[PCI_SECONDARY_BUS];
1424 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS];
1426 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
1427 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1428 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1430 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
1431 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1432 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1434 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
1435 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1436 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1438 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1439 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1441 info->has_devices = true;
1442 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1449 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1452 const pci_class_desc *desc;
1453 PciDeviceInfo *info;
1457 info = g_malloc0(sizeof(*info));
1458 info->bus = bus_num;
1459 info->slot = PCI_SLOT(dev->devfn);
1460 info->function = PCI_FUNC(dev->devfn);
1462 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1463 info->class_info.class = class;
1464 desc = get_class_desc(class);
1466 info->class_info.has_desc = true;
1467 info->class_info.desc = g_strdup(desc->desc);
1470 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1471 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID);
1472 info->regions = qmp_query_pci_regions(dev);
1473 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1475 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1476 info->has_irq = true;
1477 info->irq = dev->config[PCI_INTERRUPT_LINE];
1480 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1481 if (type == PCI_HEADER_TYPE_BRIDGE) {
1482 info->has_pci_bridge = true;
1483 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1489 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1491 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1495 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1496 dev = bus->devices[devfn];
1498 info = g_malloc0(sizeof(*info));
1499 info->value = qmp_query_pci_device(dev, bus, bus_num);
1501 /* XXX: waiting for the qapi to support GSList */
1503 head = cur_item = info;
1505 cur_item->next = info;
1514 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1516 PciInfo *info = NULL;
1518 bus = pci_find_bus_nr(bus, bus_num);
1520 info = g_malloc0(sizeof(*info));
1521 info->bus = bus_num;
1522 info->devices = qmp_query_pci_devices(bus, bus_num);
1528 PciInfoList *qmp_query_pci(Error **errp)
1530 PciInfoList *info, *head = NULL, *cur_item = NULL;
1531 struct PCIHostBus *host;
1533 QLIST_FOREACH(host, &host_buses, next) {
1534 info = g_malloc0(sizeof(*info));
1535 info->value = qmp_query_pci_bus(host->bus, 0);
1537 /* XXX: waiting for the qapi to support GSList */
1539 head = cur_item = info;
1541 cur_item->next = info;
1549 static const char * const pci_nic_models[] = {
1561 static const char * const pci_nic_names[] = {
1573 /* Initialize a PCI NIC. */
1574 /* FIXME callers should check for failure, but don't */
1575 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1576 const char *default_devaddr)
1578 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1585 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1589 bus = pci_get_bus_devfn(&devfn, devaddr);
1591 error_report("Invalid PCI device address %s for device %s",
1592 devaddr, pci_nic_names[i]);
1596 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1597 dev = &pci_dev->qdev;
1598 qdev_set_nic_properties(dev, nd);
1599 if (qdev_init(dev) < 0)
1604 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1605 const char *default_devaddr)
1609 if (qemu_show_nic_models(nd->model, pci_nic_models))
1612 res = pci_nic_init(nd, default_model, default_devaddr);
1618 PCIDevice *pci_vga_init(PCIBus *bus)
1620 switch (vga_interface_type) {
1622 return pci_create_simple(bus, -1, "cirrus-vga");
1624 return pci_create_simple(bus, -1, "qxl-vga");
1626 return pci_create_simple(bus, -1, "VGA");
1628 return pci_create_simple(bus, -1, "vmware-svga");
1631 return pci_create_simple(bus, -1, "MARU_VGA");
1634 default: /* Other non-PCI types. Checking for unsupported types is already
1640 /* Whether a given bus number is in range of the secondary
1641 * bus of the given bridge device. */
1642 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1644 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1645 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1646 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1647 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1650 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1658 if (pci_bus_num(bus) == bus_num) {
1662 /* Consider all bus numbers in range for the host pci bridge. */
1663 if (!pci_bus_is_root(bus) &&
1664 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1669 for (; bus; bus = sec) {
1670 QLIST_FOREACH(sec, &bus->child, sibling) {
1671 assert(!pci_bus_is_root(sec));
1672 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1675 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1684 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1686 bus = pci_find_bus_nr(bus, bus_num);
1691 return bus->devices[devfn];
1694 static int pci_qdev_init(DeviceState *qdev)
1696 PCIDevice *pci_dev = (PCIDevice *)qdev;
1697 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1700 bool is_default_rom;
1702 /* initialize cap_present for pci_is_express() and pci_config_size() */
1703 if (pc->is_express) {
1704 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1707 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1708 pci_dev = do_pci_register_device(pci_dev, bus,
1709 object_get_typename(OBJECT(qdev)),
1711 if (pci_dev == NULL)
1713 if (qdev->hotplugged && pc->no_hotplug) {
1714 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev)));
1715 do_pci_unregister_device(pci_dev);
1719 rc = pc->init(pci_dev);
1721 do_pci_unregister_device(pci_dev);
1727 is_default_rom = false;
1728 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
1729 pci_dev->romfile = g_strdup(pc->romfile);
1730 is_default_rom = true;
1732 pci_add_option_rom(pci_dev, is_default_rom);
1735 /* Let buses differentiate between hotplug and when device is
1736 * enabled during qemu machine creation. */
1737 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1738 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1739 PCI_COLDPLUG_ENABLED);
1741 int r = pci_unregister_device(&pci_dev->qdev);
1749 static int pci_unplug_device(DeviceState *qdev)
1751 PCIDevice *dev = PCI_DEVICE(qdev);
1752 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1754 if (pc->no_hotplug) {
1755 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev)));
1758 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1759 PCI_HOTPLUG_DISABLED);
1762 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1767 dev = qdev_create(&bus->qbus, name);
1768 qdev_prop_set_int32(dev, "addr", devfn);
1769 qdev_prop_set_bit(dev, "multifunction", multifunction);
1770 return PCI_DEVICE(dev);
1773 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1777 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1778 qdev_init_nofail(&dev->qdev);
1782 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1784 return pci_create_multifunction(bus, devfn, false, name);
1787 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1789 return pci_create_simple_multifunction(bus, devfn, false, name);
1792 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
1794 int offset = PCI_CONFIG_HEADER_SIZE;
1796 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
1799 else if (i - offset + 1 == size)
1805 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1810 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1813 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1814 prev = next + PCI_CAP_LIST_NEXT)
1815 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1823 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1825 uint8_t next, prev, found = 0;
1827 if (!(pdev->used[offset])) {
1831 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1833 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1834 prev = next + PCI_CAP_LIST_NEXT) {
1835 if (next <= offset && next > found) {
1842 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1843 This is needed for an option rom which is used for more than one device. */
1844 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1848 uint16_t rom_vendor_id;
1849 uint16_t rom_device_id;
1851 uint16_t pcir_offset;
1854 /* Words in rom data are little endian (like in PCI configuration),
1855 so they can be read / written with pci_get_word / pci_set_word. */
1857 /* Only a valid rom will be patched. */
1858 rom_magic = pci_get_word(ptr);
1859 if (rom_magic != 0xaa55) {
1860 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1863 pcir_offset = pci_get_word(ptr + 0x18);
1864 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1865 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1869 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1870 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1871 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1872 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1874 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1875 vendor_id, device_id, rom_vendor_id, rom_device_id);
1879 if (vendor_id != rom_vendor_id) {
1880 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1881 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1882 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1883 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1885 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1888 if (device_id != rom_device_id) {
1889 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1890 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1891 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1892 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1894 pci_set_word(ptr + pcir_offset + 6, device_id);
1898 /* Add an option rom for the device */
1899 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1905 const VMStateDescription *vmsd;
1909 if (strlen(pdev->romfile) == 0)
1912 if (!pdev->rom_bar) {
1914 * Load rom via fw_cfg instead of creating a rom bar,
1915 * for 0.11 compatibility.
1917 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1918 if (class == 0x0300) {
1919 rom_add_vga(pdev->romfile);
1921 rom_add_option(pdev->romfile, -1);
1926 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1928 path = g_strdup(pdev->romfile);
1931 size = get_image_size(path);
1933 error_report("%s: failed to find romfile \"%s\"",
1934 __func__, pdev->romfile);
1937 } else if (size == 0) {
1938 error_report("%s: ignoring empty romfile \"%s\"",
1939 __func__, pdev->romfile);
1943 if (size & (size - 1)) {
1944 size = 1 << qemu_fls(size);
1947 vmsd = qdev_get_vmsd(DEVICE(pdev));
1950 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
1952 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
1954 pdev->has_rom = true;
1955 memory_region_init_ram(&pdev->rom, name, size);
1956 vmstate_register_ram(&pdev->rom, &pdev->qdev);
1957 ptr = memory_region_get_ram_ptr(&pdev->rom);
1958 load_image(path, ptr);
1961 if (is_default_rom) {
1962 /* Only the default rom images will be patched (if needed). */
1963 pci_patch_ids(pdev, ptr, size);
1966 qemu_put_ram_ptr(ptr);
1968 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1973 static void pci_del_option_rom(PCIDevice *pdev)
1978 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
1979 memory_region_destroy(&pdev->rom);
1980 pdev->has_rom = false;
1985 * Reserve space and add capability to the linked list in pci config space
1988 * Find and reserve space and add capability to the linked list
1989 * in pci config space */
1990 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1991 uint8_t offset, uint8_t size)
1994 int i, overlapping_cap;
1997 offset = pci_find_space(pdev, size);
2002 /* Verify that capabilities don't overlap. Note: device assignment
2003 * depends on this check to verify that the device is not broken.
2004 * Should never trigger for emulated devices, but it's helpful
2005 * for debugging these. */
2006 for (i = offset; i < offset + size; i++) {
2007 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2008 if (overlapping_cap) {
2009 fprintf(stderr, "ERROR: %04x:%02x:%02x.%x "
2010 "Attempt to add PCI capability %x at offset "
2011 "%x overlaps existing capability %x at offset %x\n",
2012 pci_find_domain(pdev->bus), pci_bus_num(pdev->bus),
2013 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2014 cap_id, offset, overlapping_cap, i);
2020 config = pdev->config + offset;
2021 config[PCI_CAP_LIST_ID] = cap_id;
2022 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2023 pdev->config[PCI_CAPABILITY_LIST] = offset;
2024 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2025 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2026 /* Make capability read-only by default */
2027 memset(pdev->wmask + offset, 0, size);
2028 /* Check capability by default */
2029 memset(pdev->cmask + offset, 0xFF, size);
2033 /* Unlink capability from the pci config space. */
2034 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2036 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2039 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2040 /* Make capability writable again */
2041 memset(pdev->wmask + offset, 0xff, size);
2042 memset(pdev->w1cmask + offset, 0, size);
2043 /* Clear cmask as device-specific registers can't be checked */
2044 memset(pdev->cmask + offset, 0, size);
2045 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2047 if (!pdev->config[PCI_CAPABILITY_LIST])
2048 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2051 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2053 return pci_find_capability_list(pdev, cap_id, NULL);
2056 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2058 PCIDevice *d = (PCIDevice *)dev;
2059 const pci_class_desc *desc;
2064 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2065 desc = pci_class_descriptions;
2066 while (desc->desc && class != desc->class)
2069 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2071 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2074 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2075 "pci id %04x:%04x (sub %04x:%04x)\n",
2076 indent, "", ctxt, pci_bus_num(d->bus),
2077 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2078 pci_get_word(d->config + PCI_VENDOR_ID),
2079 pci_get_word(d->config + PCI_DEVICE_ID),
2080 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2081 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2082 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2083 r = &d->io_regions[i];
2086 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2087 " [0x%"FMT_PCIBUS"]\n",
2089 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2090 r->addr, r->addr + r->size - 1);
2094 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2096 PCIDevice *d = (PCIDevice *)dev;
2097 const char *name = NULL;
2098 const pci_class_desc *desc = pci_class_descriptions;
2099 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2101 while (desc->desc &&
2102 (class & ~desc->fw_ign_bits) !=
2103 (desc->class & ~desc->fw_ign_bits)) {
2108 name = desc->fw_name;
2112 pstrcpy(buf, len, name);
2114 snprintf(buf, len, "pci%04x,%04x",
2115 pci_get_word(d->config + PCI_VENDOR_ID),
2116 pci_get_word(d->config + PCI_DEVICE_ID));
2122 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2124 PCIDevice *d = (PCIDevice *)dev;
2125 char path[50], name[33];
2128 off = snprintf(path, sizeof(path), "%s@%x",
2129 pci_dev_fw_name(dev, name, sizeof name),
2130 PCI_SLOT(d->devfn));
2131 if (PCI_FUNC(d->devfn))
2132 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2133 return g_strdup(path);
2136 static char *pcibus_get_dev_path(DeviceState *dev)
2138 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2141 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2142 * 00 is added here to make this format compatible with
2143 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2144 * Slot.Function list specifies the slot and function numbers for all
2145 * devices on the path from root to the specific device. */
2146 char domain[] = "DDDD:00";
2147 char slot[] = ":SS.F";
2148 int domain_len = sizeof domain - 1 /* For '\0' */;
2149 int slot_len = sizeof slot - 1 /* For '\0' */;
2154 /* Calculate # of slots on path between device and root. */;
2156 for (t = d; t; t = t->bus->parent_dev) {
2160 path_len = domain_len + slot_len * slot_depth;
2162 /* Allocate memory, fill in the terminating null byte. */
2163 path = g_malloc(path_len + 1 /* For '\0' */);
2164 path[path_len] = '\0';
2166 /* First field is the domain. */
2167 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
2168 assert(s == domain_len);
2169 memcpy(path, domain, domain_len);
2171 /* Fill in slot numbers. We walk up from device to root, so need to print
2172 * them in the reverse order, last to first. */
2173 p = path + path_len;
2174 for (t = d; t; t = t->bus->parent_dev) {
2176 s = snprintf(slot, sizeof slot, ":%02x.%x",
2177 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2178 assert(s == slot_len);
2179 memcpy(p, slot, slot_len);
2185 static int pci_qdev_find_recursive(PCIBus *bus,
2186 const char *id, PCIDevice **pdev)
2188 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2193 /* roughly check if given qdev is pci device */
2194 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2195 *pdev = PCI_DEVICE(qdev);
2201 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2203 struct PCIHostBus *host;
2206 QLIST_FOREACH(host, &host_buses, next) {
2207 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
2212 if (tmp != -ENODEV) {
2220 MemoryRegion *pci_address_space(PCIDevice *dev)
2222 return dev->bus->address_space_mem;
2225 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2227 return dev->bus->address_space_io;
2230 static void pci_device_class_init(ObjectClass *klass, void *data)
2232 DeviceClass *k = DEVICE_CLASS(klass);
2233 k->init = pci_qdev_init;
2234 k->unplug = pci_unplug_device;
2235 k->exit = pci_unregister_device;
2236 k->bus_type = TYPE_PCI_BUS;
2237 k->props = pci_props;
2240 void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque)
2242 bus->dma_context_fn = fn;
2243 bus->dma_context_opaque = opaque;
2246 static const TypeInfo pci_device_type_info = {
2247 .name = TYPE_PCI_DEVICE,
2248 .parent = TYPE_DEVICE,
2249 .instance_size = sizeof(PCIDevice),
2251 .class_size = sizeof(PCIDeviceClass),
2252 .class_init = pci_device_class_init,
2255 static void pci_register_types(void)
2257 type_register_static(&pci_bus_info);
2258 type_register_static(&pcie_bus_info);
2259 type_register_static(&pci_device_type_info);
2262 type_init(pci_register_types)