4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 struct omap_lcd_panel_s {
30 ram_addr_t emiff_base;
43 struct omap_dma_lcd_channel_s *dma;
44 uint16_t palette[256];
51 static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
53 if (s->frame_done && (s->interrupts & 1)) {
54 qemu_irq_raise(s->irq);
58 if (s->palette_done && (s->interrupts & 2)) {
59 qemu_irq_raise(s->irq);
64 qemu_irq_raise(s->irq);
68 qemu_irq_lower(s->irq);
71 #include "pixel_ops.h"
73 typedef void draw_line_func(
74 uint8_t *d, const uint8_t *s, int width, const uint16_t *pal);
77 #include "omap_lcd_template.h"
79 #include "omap_lcd_template.h"
81 #include "omap_lcd_template.h"
83 #include "omap_lcd_template.h"
85 static draw_line_func *draw_line_table2[33] = {
91 }, *draw_line_table4[33] = {
97 }, *draw_line_table8[33] = {
100 [15] = draw_line8_15,
101 [16] = draw_line8_16,
102 [32] = draw_line8_32,
103 }, *draw_line_table12[33] = {
106 [15] = draw_line12_15,
107 [16] = draw_line12_16,
108 [32] = draw_line12_32,
109 }, *draw_line_table16[33] = {
112 [15] = draw_line16_15,
113 [16] = draw_line16_16,
114 [32] = draw_line16_32,
117 static void omap_update_display(void *opaque)
119 struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
120 draw_line_func *draw_line;
121 int size, dirty[2], minline, maxline, height;
122 int line, width, linesize, step, bpp, frame_offset;
123 ram_addr_t frame_base, scanline, newline, x;
126 if (!omap_lcd || omap_lcd->plm == 1 ||
127 !omap_lcd->enable || !ds_get_bits_per_pixel(omap_lcd->state))
131 if (omap_lcd->plm != 2) {
132 memcpy(omap_lcd->palette, phys_ram_base +
133 omap_lcd->dma->phys_framebuffer[
134 omap_lcd->dma->current_frame], 0x200);
135 switch (omap_lcd->palette[0] >> 12 & 7) {
137 frame_offset += 0x200;
140 frame_offset += 0x20;
145 switch ((omap_lcd->palette[0] >> 12) & 7) {
147 draw_line = draw_line_table2[ds_get_bits_per_pixel(omap_lcd->state)];
152 draw_line = draw_line_table4[ds_get_bits_per_pixel(omap_lcd->state)];
157 draw_line = draw_line_table8[ds_get_bits_per_pixel(omap_lcd->state)];
163 draw_line = draw_line_table12[ds_get_bits_per_pixel(omap_lcd->state)];
165 draw_line = draw_line_table16[ds_get_bits_per_pixel(omap_lcd->state)];
170 /* Unsupported at the moment. */
175 width = omap_lcd->width;
176 if (width != ds_get_width(omap_lcd->state) ||
177 omap_lcd->height != ds_get_height(omap_lcd->state)) {
178 qemu_console_resize(omap_lcd->console,
179 omap_lcd->width, omap_lcd->height);
180 omap_lcd->invalidate = 1;
183 if (omap_lcd->dma->current_frame == 0)
184 size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top;
186 size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top;
188 if (frame_offset + ((width * omap_lcd->height * bpp) >> 3) > size + 2) {
189 omap_lcd->sync_error = 1;
190 omap_lcd_interrupts(omap_lcd);
191 omap_lcd->enable = 0;
196 frame_base = omap_lcd->dma->phys_framebuffer[
197 omap_lcd->dma->current_frame] + frame_offset;
198 omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame;
199 if (omap_lcd->dma->interrupts & 1)
200 qemu_irq_raise(omap_lcd->dma->irq);
201 if (omap_lcd->dma->dual)
202 omap_lcd->dma->current_frame ^= 1;
204 if (!ds_get_bits_per_pixel(omap_lcd->state))
208 height = omap_lcd->height;
209 if (omap_lcd->subpanel & (1 << 31)) {
210 if (omap_lcd->subpanel & (1 << 29))
211 line = (omap_lcd->subpanel >> 16) & 0x3ff;
213 height = (omap_lcd->subpanel >> 16) & 0x3ff;
214 /* TODO: fill the rest of the panel with DPD */
216 step = width * bpp >> 3;
217 scanline = frame_base + step * line;
218 s = (uint8_t *) (phys_ram_base + scanline);
219 d = ds_get_data(omap_lcd->state);
220 linesize = ds_get_linesize(omap_lcd->state);
222 dirty[0] = dirty[1] =
223 cpu_physical_memory_get_dirty(scanline, VGA_DIRTY_FLAG);
226 for (; line < height; line ++) {
227 newline = scanline + step;
228 for (x = scanline + TARGET_PAGE_SIZE; x < newline;
229 x += TARGET_PAGE_SIZE) {
230 dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
231 dirty[0] |= dirty[1];
233 if (dirty[0] || omap_lcd->invalidate) {
234 draw_line(d, s, width, omap_lcd->palette);
245 if (maxline >= minline) {
246 dpy_update(omap_lcd->state, 0, minline, width, maxline);
247 cpu_physical_memory_reset_dirty(frame_base + step * minline,
248 frame_base + step * maxline, VGA_DIRTY_FLAG);
252 static int ppm_save(const char *filename, uint8_t *data,
253 int w, int h, int linesize)
260 f = fopen(filename, "wb");
263 fprintf(f, "P6\n%d %d\n%d\n", w, h, 255);
266 for (y = 0; y < h; y ++) {
268 for (x = 0; x < w; x ++) {
272 fputc((v >> 8) & 0xf8, f);
273 fputc((v >> 3) & 0xfc, f);
274 fputc((v << 3) & 0xf8, f);
279 fputc((v >> 16) & 0xff, f);
280 fputc((v >> 8) & 0xff, f);
281 fputc((v) & 0xff, f);
292 static void omap_screen_dump(void *opaque, const char *filename) {
293 struct omap_lcd_panel_s *omap_lcd = opaque;
294 omap_update_display(opaque);
295 if (omap_lcd && ds_get_data(omap_lcd->state))
296 ppm_save(filename, ds_get_data(omap_lcd->state),
297 omap_lcd->width, omap_lcd->height,
298 ds_get_linesize(omap_lcd->state));
301 static void omap_invalidate_display(void *opaque) {
302 struct omap_lcd_panel_s *omap_lcd = opaque;
303 omap_lcd->invalidate = 1;
306 static void omap_lcd_update(struct omap_lcd_panel_s *s) {
308 s->dma->current_frame = -1;
312 omap_lcd_interrupts(s);
316 if (s->dma->current_frame == -1) {
319 s->dma->current_frame = 0;
322 if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu,
323 s->dma->src_f1_top) ||
325 s->dma->src].addr_valid(s->dma->mpu,
326 s->dma->src_f1_bottom) ||
329 s->dma->src].addr_valid(s->dma->mpu,
330 s->dma->src_f2_top) ||
332 s->dma->src].addr_valid(s->dma->mpu,
333 s->dma->src_f2_bottom)))) {
334 s->dma->condition |= 1 << 2;
335 if (s->dma->interrupts & (1 << 1))
336 qemu_irq_raise(s->dma->irq);
341 if (s->dma->src == imif) {
342 /* Framebuffers are in SRAM */
343 s->dma->phys_framebuffer[0] = s->imif_base +
344 s->dma->src_f1_top - OMAP_IMIF_BASE;
346 s->dma->phys_framebuffer[1] = s->imif_base +
347 s->dma->src_f2_top - OMAP_IMIF_BASE;
349 /* Framebuffers are in RAM */
350 s->dma->phys_framebuffer[0] = s->emiff_base +
351 s->dma->src_f1_top - OMAP_EMIFF_BASE;
353 s->dma->phys_framebuffer[1] = s->emiff_base +
354 s->dma->src_f2_top - OMAP_EMIFF_BASE;
357 if (s->plm != 2 && !s->palette_done) {
358 memcpy(s->palette, phys_ram_base +
359 s->dma->phys_framebuffer[s->dma->current_frame], 0x200);
361 omap_lcd_interrupts(s);
365 static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
367 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
370 case 0x00: /* LCD_CONTROL */
371 return (s->tft << 23) | (s->plm << 20) |
372 (s->tft << 7) | (s->interrupts << 3) |
373 (s->mono << 1) | s->enable | s->ctrl | 0xfe000c34;
375 case 0x04: /* LCD_TIMING0 */
376 return (s->timing[0] << 10) | (s->width - 1) | 0x0000000f;
378 case 0x08: /* LCD_TIMING1 */
379 return (s->timing[1] << 10) | (s->height - 1);
381 case 0x0c: /* LCD_TIMING2 */
382 return s->timing[2] | 0xfc000000;
384 case 0x10: /* LCD_STATUS */
385 return (s->palette_done << 6) | (s->sync_error << 2) | s->frame_done;
387 case 0x14: /* LCD_SUBPANEL */
397 static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
400 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
403 case 0x00: /* LCD_CONTROL */
404 s->plm = (value >> 20) & 3;
405 s->tft = (value >> 7) & 1;
406 s->interrupts = (value >> 3) & 3;
407 s->mono = (value >> 1) & 1;
408 s->ctrl = value & 0x01cff300;
409 if (s->enable != (value & 1)) {
410 s->enable = value & 1;
415 case 0x04: /* LCD_TIMING0 */
416 s->timing[0] = value >> 10;
417 s->width = (value & 0x3ff) + 1;
420 case 0x08: /* LCD_TIMING1 */
421 s->timing[1] = value >> 10;
422 s->height = (value & 0x3ff) + 1;
425 case 0x0c: /* LCD_TIMING2 */
426 s->timing[2] = value;
429 case 0x10: /* LCD_STATUS */
432 case 0x14: /* LCD_SUBPANEL */
433 s->subpanel = value & 0xa1ffffff;
441 static CPUReadMemoryFunc *omap_lcdc_readfn[] = {
447 static CPUWriteMemoryFunc *omap_lcdc_writefn[] = {
453 void omap_lcdc_reset(struct omap_lcd_panel_s *s)
455 s->dma->current_frame = -1;
475 struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
476 struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
477 ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk)
480 struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
481 qemu_mallocz(sizeof(struct omap_lcd_panel_s));
486 s->imif_base = imif_base;
487 s->emiff_base = emiff_base;
490 iomemtype = cpu_register_io_memory(0, omap_lcdc_readfn,
491 omap_lcdc_writefn, s);
492 cpu_register_physical_memory(base, 0x100, iomemtype);
494 s->console = graphic_console_init(ds, omap_update_display,
495 omap_invalidate_display,
496 omap_screen_dump, NULL, s);