4 * This module includes support for MSI-X in pci devices.
6 * Author: Michael S. Tsirkin <mst@redhat.com>
8 * Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
10 * This work is licensed under the terms of the GNU GPL, version 2. See
11 * the COPYING file in the top-level directory.
18 /* MSI-X capability structure */
19 #define MSIX_TABLE_OFFSET 4
20 #define MSIX_PBA_OFFSET 8
21 #define MSIX_CAP_LENGTH 12
23 /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
24 #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
25 #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
26 #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
28 /* MSI-X table format */
29 #define MSIX_MSG_ADDR 0
30 #define MSIX_MSG_UPPER_ADDR 4
31 #define MSIX_MSG_DATA 8
32 #define MSIX_VECTOR_CTRL 12
33 #define MSIX_ENTRY_SIZE 16
34 #define MSIX_VECTOR_MASK 0x1
36 /* How much space does an MSIX table need. */
37 /* The spec requires giving the table structure
38 * a 4K aligned region all by itself. */
39 #define MSIX_PAGE_SIZE 0x1000
40 /* Reserve second half of the page for pending bits */
41 #define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
42 #define MSIX_MAX_ENTRIES 32
45 /* Flag for interrupt controller to declare MSI-X support */
48 /* Add MSI-X capability to the config space for the device. */
49 /* Given a bar and its size, add MSI-X table on top of it
50 * and fill MSI-X capability in the config space.
51 * Original bar size must be a power of 2 or 0.
52 * New bar size is returned. */
53 static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
54 unsigned bar_nr, unsigned bar_size)
60 if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
62 if (bar_size > 0x80000000)
65 /* Add space for MSI-X structures */
67 new_size = MSIX_PAGE_SIZE;
68 } else if (bar_size < MSIX_PAGE_SIZE) {
69 bar_size = MSIX_PAGE_SIZE;
70 new_size = MSIX_PAGE_SIZE * 2;
72 new_size = bar_size * 2;
75 pdev->msix_bar_size = new_size;
76 config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
78 if (config_offset < 0)
80 config = pdev->config + config_offset;
82 pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
83 /* Table on top of BAR */
84 pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr);
85 /* Pending bits on top of that */
86 pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) |
88 pdev->msix_cap = config_offset;
89 /* Make flags bit writeable. */
90 pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
95 static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
97 PCIDevice *dev = opaque;
98 unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
99 void *page = dev->msix_table_page;
101 return pci_get_long(page + offset);
104 static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
106 fprintf(stderr, "MSI-X: only dword read is allowed!\n");
110 static uint8_t msix_pending_mask(int vector)
112 return 1 << (vector % 8);
115 static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
117 return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
120 static int msix_is_pending(PCIDevice *dev, int vector)
122 return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
125 static void msix_set_pending(PCIDevice *dev, int vector)
127 *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
130 static void msix_clr_pending(PCIDevice *dev, int vector)
132 *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
135 static int msix_function_masked(PCIDevice *dev)
137 return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
140 static int msix_is_masked(PCIDevice *dev, int vector)
142 unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
143 return msix_function_masked(dev) ||
144 dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
147 static void msix_handle_mask_update(PCIDevice *dev, int vector)
149 if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
150 msix_clr_pending(dev, vector);
151 msix_notify(dev, vector);
155 /* Handle MSI-X capability config write. */
156 void msix_write_config(PCIDevice *dev, uint32_t addr,
157 uint32_t val, int len)
159 unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
162 if (!range_covers_byte(addr, len, enable_pos)) {
166 if (!msix_enabled(dev)) {
170 qemu_set_irq(dev->irq[0], 0);
172 if (msix_function_masked(dev)) {
176 for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
177 msix_handle_mask_update(dev, vector);
181 static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
184 PCIDevice *dev = opaque;
185 unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
186 int vector = offset / MSIX_ENTRY_SIZE;
187 pci_set_long(dev->msix_table_page + offset, val);
188 msix_handle_mask_update(dev, vector);
191 static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
194 fprintf(stderr, "MSI-X: only dword write is allowed!\n");
197 static CPUWriteMemoryFunc * const msix_mmio_write[] = {
198 msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
201 static CPUReadMemoryFunc * const msix_mmio_read[] = {
202 msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
205 /* Should be called from device's map method. */
206 void msix_mmio_map(PCIDevice *d, int region_num,
207 pcibus_t addr, pcibus_t size, int type)
209 uint8_t *config = d->config + d->msix_cap;
210 uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
211 uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
212 /* TODO: for assigned devices, we'll want to make it possible to map
213 * pending bits separately in case they are in a separate bar. */
214 int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
216 if (table_bir != region_num)
220 cpu_register_physical_memory(addr + offset, size - offset,
224 static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
227 for (vector = 0; vector < nentries; ++vector) {
228 unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
229 dev->msix_table_page[offset] |= MSIX_VECTOR_MASK;
233 /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
234 * modified, it should be retrieved with msix_bar_size. */
235 int msix_init(struct PCIDevice *dev, unsigned short nentries,
236 unsigned bar_nr, unsigned bar_size)
239 /* Nothing to do if MSI is not supported by interrupt controller */
243 if (nentries > MSIX_MAX_ENTRIES)
246 dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
247 sizeof *dev->msix_entry_used);
249 dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
250 msix_mask_all(dev, nentries);
252 dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
253 msix_mmio_write, dev);
254 if (dev->msix_mmio_index == -1) {
259 dev->msix_entries_nr = nentries;
260 ret = msix_add_config(dev, nentries, bar_nr, bar_size);
264 dev->cap_present |= QEMU_PCI_CAP_MSIX;
268 dev->msix_entries_nr = 0;
269 cpu_unregister_io_memory(dev->msix_mmio_index);
271 qemu_free(dev->msix_table_page);
272 dev->msix_table_page = NULL;
273 qemu_free(dev->msix_entry_used);
274 dev->msix_entry_used = NULL;
278 static void msix_free_irq_entries(PCIDevice *dev)
282 for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
283 dev->msix_entry_used[vector] = 0;
284 msix_clr_pending(dev, vector);
288 /* Clean up resources for the device. */
289 int msix_uninit(PCIDevice *dev)
291 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
293 pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
295 msix_free_irq_entries(dev);
296 dev->msix_entries_nr = 0;
297 cpu_unregister_io_memory(dev->msix_mmio_index);
298 qemu_free(dev->msix_table_page);
299 dev->msix_table_page = NULL;
300 qemu_free(dev->msix_entry_used);
301 dev->msix_entry_used = NULL;
302 dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
306 void msix_save(PCIDevice *dev, QEMUFile *f)
308 unsigned n = dev->msix_entries_nr;
310 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
314 qemu_put_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
315 qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
318 /* Should be called after restoring the config space. */
319 void msix_load(PCIDevice *dev, QEMUFile *f)
321 unsigned n = dev->msix_entries_nr;
323 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
327 msix_free_irq_entries(dev);
328 qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
329 qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
332 /* Does device support MSI-X? */
333 int msix_present(PCIDevice *dev)
335 return dev->cap_present & QEMU_PCI_CAP_MSIX;
338 /* Is MSI-X enabled? */
339 int msix_enabled(PCIDevice *dev)
341 return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
342 (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
346 /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
347 uint32_t msix_bar_size(PCIDevice *dev)
349 return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
350 dev->msix_bar_size : 0;
353 /* Send an MSI-X message */
354 void msix_notify(PCIDevice *dev, unsigned vector)
356 uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE;
360 if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
362 if (msix_is_masked(dev, vector)) {
363 msix_set_pending(dev, vector);
367 address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
368 address = (address << 32) | pci_get_long(table_entry + MSIX_MSG_ADDR);
369 data = pci_get_long(table_entry + MSIX_MSG_DATA);
370 stl_phys(address, data);
373 void msix_reset(PCIDevice *dev)
375 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
377 msix_free_irq_entries(dev);
378 dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
379 ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
380 memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
381 msix_mask_all(dev, dev->msix_entries_nr);
384 /* PCI spec suggests that devices make it possible for software to configure
385 * less vectors than supported by the device, but does not specify a standard
386 * mechanism for devices to do so.
388 * We support this by asking devices to declare vectors software is going to
389 * actually use, and checking this on the notification path. Devices that
390 * don't want to follow the spec suggestion can declare all vectors as used. */
392 /* Mark vector as used. */
393 int msix_vector_use(PCIDevice *dev, unsigned vector)
395 if (vector >= dev->msix_entries_nr)
397 dev->msix_entry_used[vector]++;
401 /* Mark vector as unused. */
402 void msix_vector_unuse(PCIDevice *dev, unsigned vector)
404 if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
407 if (--dev->msix_entry_used[vector]) {
410 msix_clr_pending(dev, vector);
413 void msix_unuse_all_vectors(PCIDevice *dev)
415 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
417 msix_free_irq_entries(dev);