4 * This module includes support for MSI-X in pci devices.
6 * Author: Michael S. Tsirkin <mst@redhat.com>
8 * Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
10 * This work is licensed under the terms of the GNU GPL, version 2. See
11 * the COPYING file in the top-level directory.
19 #define MSIX_CAP_LENGTH 12
21 /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
22 #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
23 #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
24 #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
26 /* How much space does an MSIX table need. */
27 /* The spec requires giving the table structure
28 * a 4K aligned region all by itself. */
29 #define MSIX_PAGE_SIZE 0x1000
30 /* Reserve second half of the page for pending bits */
31 #define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
32 #define MSIX_MAX_ENTRIES 32
35 /* Flag for interrupt controller to declare MSI-X support */
38 /* Add MSI-X capability to the config space for the device. */
39 /* Given a bar and its size, add MSI-X table on top of it
40 * and fill MSI-X capability in the config space.
41 * Original bar size must be a power of 2 or 0.
42 * New bar size is returned. */
43 static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
44 unsigned bar_nr, unsigned bar_size)
50 if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
52 if (bar_size > 0x80000000)
55 /* Add space for MSI-X structures */
57 new_size = MSIX_PAGE_SIZE;
58 } else if (bar_size < MSIX_PAGE_SIZE) {
59 bar_size = MSIX_PAGE_SIZE;
60 new_size = MSIX_PAGE_SIZE * 2;
62 new_size = bar_size * 2;
65 pdev->msix_bar_size = new_size;
66 config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
68 if (config_offset < 0)
70 config = pdev->config + config_offset;
72 pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
73 /* Table on top of BAR */
74 pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr);
75 /* Pending bits on top of that */
76 pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) |
78 pdev->msix_cap = config_offset;
79 /* Make flags bit writeable. */
80 pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
85 static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
87 PCIDevice *dev = opaque;
88 unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
89 void *page = dev->msix_table_page;
91 return pci_get_long(page + offset);
94 static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
96 fprintf(stderr, "MSI-X: only dword read is allowed!\n");
100 static uint8_t msix_pending_mask(int vector)
102 return 1 << (vector % 8);
105 static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
107 return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
110 static int msix_is_pending(PCIDevice *dev, int vector)
112 return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
115 static void msix_set_pending(PCIDevice *dev, int vector)
117 *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
120 static void msix_clr_pending(PCIDevice *dev, int vector)
122 *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
125 static int msix_function_masked(PCIDevice *dev)
127 return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK;
130 static int msix_is_masked(PCIDevice *dev, int vector)
133 vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
134 return msix_function_masked(dev) ||
135 dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
138 static void msix_handle_mask_update(PCIDevice *dev, int vector)
140 if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
141 msix_clr_pending(dev, vector);
142 msix_notify(dev, vector);
146 /* Handle MSI-X capability config write. */
147 void msix_write_config(PCIDevice *dev, uint32_t addr,
148 uint32_t val, int len)
150 unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
153 if (!range_covers_byte(addr, len, enable_pos)) {
157 if (!msix_enabled(dev)) {
161 pci_device_deassert_intx(dev);
163 if (msix_function_masked(dev)) {
167 for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
168 msix_handle_mask_update(dev, vector);
172 static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
175 PCIDevice *dev = opaque;
176 unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
177 int vector = offset / PCI_MSIX_ENTRY_SIZE;
178 pci_set_long(dev->msix_table_page + offset, val);
179 msix_handle_mask_update(dev, vector);
182 static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
185 fprintf(stderr, "MSI-X: only dword write is allowed!\n");
188 static CPUWriteMemoryFunc * const msix_mmio_write[] = {
189 msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
192 static CPUReadMemoryFunc * const msix_mmio_read[] = {
193 msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
196 /* Should be called from device's map method. */
197 void msix_mmio_map(PCIDevice *d, int region_num,
198 pcibus_t addr, pcibus_t size, int type)
200 uint8_t *config = d->config + d->msix_cap;
201 uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
202 uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
203 /* TODO: for assigned devices, we'll want to make it possible to map
204 * pending bits separately in case they are in a separate bar. */
205 int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
207 if (table_bir != region_num)
211 cpu_register_physical_memory(addr + offset, size - offset,
215 static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
218 for (vector = 0; vector < nentries; ++vector) {
220 vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
221 dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
225 /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
226 * modified, it should be retrieved with msix_bar_size. */
227 int msix_init(struct PCIDevice *dev, unsigned short nentries,
228 unsigned bar_nr, unsigned bar_size)
231 /* Nothing to do if MSI is not supported by interrupt controller */
235 if (nentries > MSIX_MAX_ENTRIES)
238 dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
239 sizeof *dev->msix_entry_used);
241 dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
242 msix_mask_all(dev, nentries);
244 dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
245 msix_mmio_write, dev,
246 DEVICE_NATIVE_ENDIAN);
247 if (dev->msix_mmio_index == -1) {
252 dev->msix_entries_nr = nentries;
253 ret = msix_add_config(dev, nentries, bar_nr, bar_size);
257 dev->cap_present |= QEMU_PCI_CAP_MSIX;
261 dev->msix_entries_nr = 0;
262 cpu_unregister_io_memory(dev->msix_mmio_index);
264 qemu_free(dev->msix_table_page);
265 dev->msix_table_page = NULL;
266 qemu_free(dev->msix_entry_used);
267 dev->msix_entry_used = NULL;
271 static void msix_free_irq_entries(PCIDevice *dev)
275 for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
276 dev->msix_entry_used[vector] = 0;
277 msix_clr_pending(dev, vector);
281 /* Clean up resources for the device. */
282 int msix_uninit(PCIDevice *dev)
284 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
286 pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
288 msix_free_irq_entries(dev);
289 dev->msix_entries_nr = 0;
290 cpu_unregister_io_memory(dev->msix_mmio_index);
291 qemu_free(dev->msix_table_page);
292 dev->msix_table_page = NULL;
293 qemu_free(dev->msix_entry_used);
294 dev->msix_entry_used = NULL;
295 dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
299 void msix_save(PCIDevice *dev, QEMUFile *f)
301 unsigned n = dev->msix_entries_nr;
303 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
307 qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
308 qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
311 /* Should be called after restoring the config space. */
312 void msix_load(PCIDevice *dev, QEMUFile *f)
314 unsigned n = dev->msix_entries_nr;
316 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
320 msix_free_irq_entries(dev);
321 qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
322 qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
325 /* Does device support MSI-X? */
326 int msix_present(PCIDevice *dev)
328 return dev->cap_present & QEMU_PCI_CAP_MSIX;
331 /* Is MSI-X enabled? */
332 int msix_enabled(PCIDevice *dev)
334 return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
335 (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
339 /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
340 uint32_t msix_bar_size(PCIDevice *dev)
342 return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
343 dev->msix_bar_size : 0;
346 /* Send an MSI-X message */
347 void msix_notify(PCIDevice *dev, unsigned vector)
349 uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
353 if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
355 if (msix_is_masked(dev, vector)) {
356 msix_set_pending(dev, vector);
360 address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
361 data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
362 stl_phys(address, data);
365 void msix_reset(PCIDevice *dev)
367 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
369 msix_free_irq_entries(dev);
370 dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
371 ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
372 memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
373 msix_mask_all(dev, dev->msix_entries_nr);
376 /* PCI spec suggests that devices make it possible for software to configure
377 * less vectors than supported by the device, but does not specify a standard
378 * mechanism for devices to do so.
380 * We support this by asking devices to declare vectors software is going to
381 * actually use, and checking this on the notification path. Devices that
382 * don't want to follow the spec suggestion can declare all vectors as used. */
384 /* Mark vector as used. */
385 int msix_vector_use(PCIDevice *dev, unsigned vector)
387 if (vector >= dev->msix_entries_nr)
389 dev->msix_entry_used[vector]++;
393 /* Mark vector as unused. */
394 void msix_vector_unuse(PCIDevice *dev, unsigned vector)
396 if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
399 if (--dev->msix_entry_used[vector]) {
402 msix_clr_pending(dev, vector);
405 void msix_unuse_all_vectors(PCIDevice *dev)
407 if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
409 msix_free_irq_entries(dev);