exec: move include files to include/exec/
[sdk/emulator/qemu.git] / hw / lm32_boards.c
1 /*
2  *  QEMU models for LatticeMico32 uclinux and evr32 boards.
3  *
4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19
20 #include "sysbus.h"
21 #include "hw.h"
22 #include "flash.h"
23 #include "devices.h"
24 #include "boards.h"
25 #include "loader.h"
26 #include "blockdev.h"
27 #include "elf.h"
28 #include "lm32_hwsetup.h"
29 #include "lm32.h"
30 #include "exec/address-spaces.h"
31
32 typedef struct {
33     LM32CPU *cpu;
34     hwaddr bootstrap_pc;
35     hwaddr flash_base;
36     hwaddr hwsetup_base;
37     hwaddr initrd_base;
38     size_t initrd_size;
39     hwaddr cmdline_base;
40 } ResetInfo;
41
42 static void cpu_irq_handler(void *opaque, int irq, int level)
43 {
44     CPULM32State *env = opaque;
45
46     if (level) {
47         cpu_interrupt(env, CPU_INTERRUPT_HARD);
48     } else {
49         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
50     }
51 }
52
53 static void main_cpu_reset(void *opaque)
54 {
55     ResetInfo *reset_info = opaque;
56     CPULM32State *env = &reset_info->cpu->env;
57
58     cpu_reset(CPU(reset_info->cpu));
59
60     /* init defaults */
61     env->pc = (uint32_t)reset_info->bootstrap_pc;
62     env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
63     env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
64     env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
65     env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
66         reset_info->initrd_size);
67     env->eba = reset_info->flash_base;
68     env->deba = reset_info->flash_base;
69 }
70
71 static void lm32_evr_init(QEMUMachineInitArgs *args)
72 {
73     const char *cpu_model = args->cpu_model;
74     const char *kernel_filename = args->kernel_filename;
75     LM32CPU *cpu;
76     CPULM32State *env;
77     DriveInfo *dinfo;
78     MemoryRegion *address_space_mem =  get_system_memory();
79     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
80     qemu_irq *cpu_irq, irq[32];
81     ResetInfo *reset_info;
82     int i;
83
84     /* memory map */
85     hwaddr flash_base  = 0x04000000;
86     size_t flash_sector_size       = 256 * 1024;
87     size_t flash_size              = 32 * 1024 * 1024;
88     hwaddr ram_base    = 0x08000000;
89     size_t ram_size                = 64 * 1024 * 1024;
90     hwaddr timer0_base = 0x80002000;
91     hwaddr uart0_base  = 0x80006000;
92     hwaddr timer1_base = 0x8000a000;
93     int uart0_irq                  = 0;
94     int timer0_irq                 = 1;
95     int timer1_irq                 = 3;
96
97     reset_info = g_malloc0(sizeof(ResetInfo));
98
99     if (cpu_model == NULL) {
100         cpu_model = "lm32-full";
101     }
102     cpu = cpu_lm32_init(cpu_model);
103     env = &cpu->env;
104     reset_info->cpu = cpu;
105
106     reset_info->flash_base = flash_base;
107
108     memory_region_init_ram(phys_ram, "lm32_evr.sdram", ram_size);
109     vmstate_register_ram_global(phys_ram);
110     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
111
112     dinfo = drive_get(IF_PFLASH, 0, 0);
113     /* Spansion S29NS128P */
114     pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
115                           dinfo ? dinfo->bdrv : NULL, flash_sector_size,
116                           flash_size / flash_sector_size, 1, 2,
117                           0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
118
119     /* create irq lines */
120     cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
121     env->pic_state = lm32_pic_init(*cpu_irq);
122     for (i = 0; i < 32; i++) {
123         irq[i] = qdev_get_gpio_in(env->pic_state, i);
124     }
125
126     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
127     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
128     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
129
130     /* make sure juart isn't the first chardev */
131     env->juart_state = lm32_juart_init();
132
133     reset_info->bootstrap_pc = flash_base;
134
135     if (kernel_filename) {
136         uint64_t entry;
137         int kernel_size;
138
139         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
140                                1, ELF_MACHINE, 0);
141         reset_info->bootstrap_pc = entry;
142
143         if (kernel_size < 0) {
144             kernel_size = load_image_targphys(kernel_filename, ram_base,
145                                               ram_size);
146             reset_info->bootstrap_pc = ram_base;
147         }
148
149         if (kernel_size < 0) {
150             fprintf(stderr, "qemu: could not load kernel '%s'\n",
151                     kernel_filename);
152             exit(1);
153         }
154     }
155
156     qemu_register_reset(main_cpu_reset, reset_info);
157 }
158
159 static void lm32_uclinux_init(QEMUMachineInitArgs *args)
160 {
161     const char *cpu_model = args->cpu_model;
162     const char *kernel_filename = args->kernel_filename;
163     const char *kernel_cmdline = args->kernel_cmdline;
164     const char *initrd_filename = args->initrd_filename;
165     LM32CPU *cpu;
166     CPULM32State *env;
167     DriveInfo *dinfo;
168     MemoryRegion *address_space_mem =  get_system_memory();
169     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
170     qemu_irq *cpu_irq, irq[32];
171     HWSetup *hw;
172     ResetInfo *reset_info;
173     int i;
174
175     /* memory map */
176     hwaddr flash_base   = 0x04000000;
177     size_t flash_sector_size        = 256 * 1024;
178     size_t flash_size               = 32 * 1024 * 1024;
179     hwaddr ram_base     = 0x08000000;
180     size_t ram_size                 = 64 * 1024 * 1024;
181     hwaddr uart0_base   = 0x80000000;
182     hwaddr timer0_base  = 0x80002000;
183     hwaddr timer1_base  = 0x80010000;
184     hwaddr timer2_base  = 0x80012000;
185     int uart0_irq                   = 0;
186     int timer0_irq                  = 1;
187     int timer1_irq                  = 20;
188     int timer2_irq                  = 21;
189     hwaddr hwsetup_base = 0x0bffe000;
190     hwaddr cmdline_base = 0x0bfff000;
191     hwaddr initrd_base  = 0x08400000;
192     size_t initrd_max               = 0x01000000;
193
194     reset_info = g_malloc0(sizeof(ResetInfo));
195
196     if (cpu_model == NULL) {
197         cpu_model = "lm32-full";
198     }
199     cpu = cpu_lm32_init(cpu_model);
200     env = &cpu->env;
201     reset_info->cpu = cpu;
202
203     reset_info->flash_base = flash_base;
204
205     memory_region_init_ram(phys_ram, "lm32_uclinux.sdram", ram_size);
206     vmstate_register_ram_global(phys_ram);
207     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
208
209     dinfo = drive_get(IF_PFLASH, 0, 0);
210     /* Spansion S29NS128P */
211     pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
212                           dinfo ? dinfo->bdrv : NULL, flash_sector_size,
213                           flash_size / flash_sector_size, 1, 2,
214                           0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
215
216     /* create irq lines */
217     cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
218     env->pic_state = lm32_pic_init(*cpu_irq);
219     for (i = 0; i < 32; i++) {
220         irq[i] = qdev_get_gpio_in(env->pic_state, i);
221     }
222
223     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
224     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
225     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
226     sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
227
228     /* make sure juart isn't the first chardev */
229     env->juart_state = lm32_juart_init();
230
231     reset_info->bootstrap_pc = flash_base;
232
233     if (kernel_filename) {
234         uint64_t entry;
235         int kernel_size;
236
237         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
238                                1, ELF_MACHINE, 0);
239         reset_info->bootstrap_pc = entry;
240
241         if (kernel_size < 0) {
242             kernel_size = load_image_targphys(kernel_filename, ram_base,
243                                               ram_size);
244             reset_info->bootstrap_pc = ram_base;
245         }
246
247         if (kernel_size < 0) {
248             fprintf(stderr, "qemu: could not load kernel '%s'\n",
249                     kernel_filename);
250             exit(1);
251         }
252     }
253
254     /* generate a rom with the hardware description */
255     hw = hwsetup_init();
256     hwsetup_add_cpu(hw, "LM32", 75000000);
257     hwsetup_add_flash(hw, "flash", flash_base, flash_size);
258     hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
259     hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
260     hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
261     hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
262     hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
263     hwsetup_add_trailer(hw);
264     hwsetup_create_rom(hw, hwsetup_base);
265     hwsetup_free(hw);
266
267     reset_info->hwsetup_base = hwsetup_base;
268
269     if (kernel_cmdline && strlen(kernel_cmdline)) {
270         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
271                 kernel_cmdline);
272         reset_info->cmdline_base = cmdline_base;
273     }
274
275     if (initrd_filename) {
276         size_t initrd_size;
277         initrd_size = load_image_targphys(initrd_filename, initrd_base,
278                 initrd_max);
279         reset_info->initrd_base = initrd_base;
280         reset_info->initrd_size = initrd_size;
281     }
282
283     qemu_register_reset(main_cpu_reset, reset_info);
284 }
285
286 static QEMUMachine lm32_evr_machine = {
287     .name = "lm32-evr",
288     .desc = "LatticeMico32 EVR32 eval system",
289     .init = lm32_evr_init,
290     .is_default = 1
291 };
292
293 static QEMUMachine lm32_uclinux_machine = {
294     .name = "lm32-uclinux",
295     .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
296     .init = lm32_uclinux_init,
297     .is_default = 0
298 };
299
300 static void lm32_machine_init(void)
301 {
302     qemu_register_machine(&lm32_uclinux_machine);
303     qemu_register_machine(&lm32_evr_machine);
304 }
305
306 machine_init(lm32_machine_init);