2 * ARM Integrator CP System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL
11 #include "primecell.h"
21 uint32_t flash_offset;
35 static uint8_t integrator_spd[128] = {
36 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
37 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
40 static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
42 integratorcm_state *s = (integratorcm_state *)opaque;
43 if (offset >= 0x100 && offset < 0x200) {
47 return integrator_spd[offset >> 2];
49 switch (offset >> 2) {
61 if (s->cm_lock == 0xa05f) {
66 case 6: /* CM_LMBUSCNT */
67 /* ??? High frequency timer. */
68 hw_error("integratorcm_read: CM_LMBUSCNT");
69 case 7: /* CM_AUXOSC */
71 case 8: /* CM_SDRAM */
75 case 10: /* CM_REFCT */
76 /* ??? High frequency timer. */
77 hw_error("integratorcm_read: CM_REFCT");
78 case 12: /* CM_FLAGS */
80 case 14: /* CM_NVFLAGS */
82 case 16: /* CM_IRQ_STAT */
83 return s->int_level & s->irq_enabled;
84 case 17: /* CM_IRQ_RSTAT */
86 case 18: /* CM_IRQ_ENSET */
87 return s->irq_enabled;
88 case 20: /* CM_SOFT_INTSET */
89 return s->int_level & 1;
90 case 24: /* CM_FIQ_STAT */
91 return s->int_level & s->fiq_enabled;
92 case 25: /* CM_FIQ_RSTAT */
94 case 26: /* CM_FIQ_ENSET */
95 return s->fiq_enabled;
96 case 32: /* CM_VOLTAGE_CTL0 */
97 case 33: /* CM_VOLTAGE_CTL1 */
98 case 34: /* CM_VOLTAGE_CTL2 */
99 case 35: /* CM_VOLTAGE_CTL3 */
100 /* ??? Voltage control unimplemented. */
103 hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
109 static void integratorcm_do_remap(integratorcm_state *s, int flash)
112 cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM);
114 cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM);
116 //??? tlb_flush (cpu_single_env, 1);
119 static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
122 hw_error("Board reset\n");
124 if ((s->cm_init ^ value) & 4) {
125 integratorcm_do_remap(s, (value & 4) == 0);
127 if ((s->cm_init ^ value) & 1) {
128 printf("Green LED %s\n", (value & 1) ? "on" : "off");
130 s->cm_init = (s->cm_init & ~ 5) | (value ^ 5);
133 static void integratorcm_update(integratorcm_state *s)
135 /* ??? The CPU irq/fiq is raised when either the core module or base PIC
137 if (s->int_level & (s->irq_enabled | s->fiq_enabled))
138 hw_error("Core module interrupt\n");
141 static void integratorcm_write(void *opaque, target_phys_addr_t offset,
144 integratorcm_state *s = (integratorcm_state *)opaque;
145 switch (offset >> 2) {
147 if (s->cm_lock == 0xa05f)
150 case 3: /* CM_CTRL */
151 integratorcm_set_ctrl(s, value);
153 case 5: /* CM_LOCK */
154 s->cm_lock = value & 0xffff;
156 case 7: /* CM_AUXOSC */
157 if (s->cm_lock == 0xa05f)
158 s->cm_auxosc = value;
160 case 8: /* CM_SDRAM */
163 case 9: /* CM_INIT */
164 /* ??? This can change the memory bus frequency. */
167 case 12: /* CM_FLAGSS */
168 s->cm_flags |= value;
170 case 13: /* CM_FLAGSC */
171 s->cm_flags &= ~value;
173 case 14: /* CM_NVFLAGSS */
174 s->cm_nvflags |= value;
176 case 15: /* CM_NVFLAGSS */
177 s->cm_nvflags &= ~value;
179 case 18: /* CM_IRQ_ENSET */
180 s->irq_enabled |= value;
181 integratorcm_update(s);
183 case 19: /* CM_IRQ_ENCLR */
184 s->irq_enabled &= ~value;
185 integratorcm_update(s);
187 case 20: /* CM_SOFT_INTSET */
188 s->int_level |= (value & 1);
189 integratorcm_update(s);
191 case 21: /* CM_SOFT_INTCLR */
192 s->int_level &= ~(value & 1);
193 integratorcm_update(s);
195 case 26: /* CM_FIQ_ENSET */
196 s->fiq_enabled |= value;
197 integratorcm_update(s);
199 case 27: /* CM_FIQ_ENCLR */
200 s->fiq_enabled &= ~value;
201 integratorcm_update(s);
203 case 32: /* CM_VOLTAGE_CTL0 */
204 case 33: /* CM_VOLTAGE_CTL1 */
205 case 34: /* CM_VOLTAGE_CTL2 */
206 case 35: /* CM_VOLTAGE_CTL3 */
207 /* ??? Voltage control unimplemented. */
210 hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
216 /* Integrator/CM control registers. */
218 static CPUReadMemoryFunc * const integratorcm_readfn[] = {
224 static CPUWriteMemoryFunc * const integratorcm_writefn[] = {
230 static int integratorcm_init(SysBusDevice *dev)
233 integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev);
235 s->cm_osc = 0x01000048;
236 /* ??? What should the high bits of this value be? */
237 s->cm_auxosc = 0x0007feff;
238 s->cm_sdram = 0x00011122;
239 if (s->memsz >= 256) {
240 integrator_spd[31] = 64;
242 } else if (s->memsz >= 128) {
243 integrator_spd[31] = 32;
245 } else if (s->memsz >= 64) {
246 integrator_spd[31] = 16;
248 } else if (s->memsz >= 32) {
249 integrator_spd[31] = 4;
252 integrator_spd[31] = 2;
254 memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
255 s->cm_init = 0x00000112;
256 s->flash_offset = qemu_ram_alloc(NULL, "integrator.flash", 0x100000);
258 iomemtype = cpu_register_io_memory(integratorcm_readfn,
259 integratorcm_writefn, s,
260 DEVICE_NATIVE_ENDIAN);
261 sysbus_init_mmio(dev, 0x00800000, iomemtype);
262 integratorcm_do_remap(s, 1);
263 /* ??? Save/restore. */
267 /* Integrator/CP hardware emulation. */
268 /* Primary interrupt controller. */
270 typedef struct icp_pic_state
274 uint32_t irq_enabled;
275 uint32_t fiq_enabled;
280 static void icp_pic_update(icp_pic_state *s)
284 flags = (s->level & s->irq_enabled);
285 qemu_set_irq(s->parent_irq, flags != 0);
286 flags = (s->level & s->fiq_enabled);
287 qemu_set_irq(s->parent_fiq, flags != 0);
290 static void icp_pic_set_irq(void *opaque, int irq, int level)
292 icp_pic_state *s = (icp_pic_state *)opaque;
294 s->level |= 1 << irq;
296 s->level &= ~(1 << irq);
300 static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
302 icp_pic_state *s = (icp_pic_state *)opaque;
304 switch (offset >> 2) {
305 case 0: /* IRQ_STATUS */
306 return s->level & s->irq_enabled;
307 case 1: /* IRQ_RAWSTAT */
309 case 2: /* IRQ_ENABLESET */
310 return s->irq_enabled;
311 case 4: /* INT_SOFTSET */
313 case 8: /* FRQ_STATUS */
314 return s->level & s->fiq_enabled;
315 case 9: /* FRQ_RAWSTAT */
317 case 10: /* FRQ_ENABLESET */
318 return s->fiq_enabled;
319 case 3: /* IRQ_ENABLECLR */
320 case 5: /* INT_SOFTCLR */
321 case 11: /* FRQ_ENABLECLR */
323 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
328 static void icp_pic_write(void *opaque, target_phys_addr_t offset,
331 icp_pic_state *s = (icp_pic_state *)opaque;
333 switch (offset >> 2) {
334 case 2: /* IRQ_ENABLESET */
335 s->irq_enabled |= value;
337 case 3: /* IRQ_ENABLECLR */
338 s->irq_enabled &= ~value;
340 case 4: /* INT_SOFTSET */
342 icp_pic_set_irq(s, 0, 1);
344 case 5: /* INT_SOFTCLR */
346 icp_pic_set_irq(s, 0, 0);
348 case 10: /* FRQ_ENABLESET */
349 s->fiq_enabled |= value;
351 case 11: /* FRQ_ENABLECLR */
352 s->fiq_enabled &= ~value;
354 case 0: /* IRQ_STATUS */
355 case 1: /* IRQ_RAWSTAT */
356 case 8: /* FRQ_STATUS */
357 case 9: /* FRQ_RAWSTAT */
359 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
365 static CPUReadMemoryFunc * const icp_pic_readfn[] = {
371 static CPUWriteMemoryFunc * const icp_pic_writefn[] = {
377 static int icp_pic_init(SysBusDevice *dev)
379 icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);
382 qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
383 sysbus_init_irq(dev, &s->parent_irq);
384 sysbus_init_irq(dev, &s->parent_fiq);
385 iomemtype = cpu_register_io_memory(icp_pic_readfn,
387 DEVICE_NATIVE_ENDIAN);
388 sysbus_init_mmio(dev, 0x00800000, iomemtype);
392 /* CP control registers. */
393 static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
395 switch (offset >> 2) {
396 case 0: /* CP_IDFIELD */
398 case 1: /* CP_FLASHPROG */
400 case 2: /* CP_INTREG */
402 case 3: /* CP_DECODE */
405 hw_error("icp_control_read: Bad offset %x\n", (int)offset);
410 static void icp_control_write(void *opaque, target_phys_addr_t offset,
413 switch (offset >> 2) {
414 case 1: /* CP_FLASHPROG */
415 case 2: /* CP_INTREG */
416 case 3: /* CP_DECODE */
417 /* Nothing interesting implemented yet. */
420 hw_error("icp_control_write: Bad offset %x\n", (int)offset);
423 static CPUReadMemoryFunc * const icp_control_readfn[] = {
429 static CPUWriteMemoryFunc * const icp_control_writefn[] = {
435 static void icp_control_init(uint32_t base)
439 iomemtype = cpu_register_io_memory(icp_control_readfn,
440 icp_control_writefn, NULL,
441 DEVICE_NATIVE_ENDIAN);
442 cpu_register_physical_memory(base, 0x00800000, iomemtype);
443 /* ??? Save/restore. */
449 static struct arm_boot_info integrator_binfo = {
454 static void integratorcp_init(ram_addr_t ram_size,
455 const char *boot_device,
456 const char *kernel_filename, const char *kernel_cmdline,
457 const char *initrd_filename, const char *cpu_model)
460 ram_addr_t ram_offset;
467 cpu_model = "arm926";
468 env = cpu_init(cpu_model);
470 fprintf(stderr, "Unable to find CPU definition\n");
473 ram_offset = qemu_ram_alloc(NULL, "integrator.ram", ram_size);
474 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
475 /* ??? RAM should repeat to fill physical memory space. */
476 /* SDRAM at address zero*/
477 cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
478 /* And again at address 0x80000000 */
479 cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM);
481 dev = qdev_create(NULL, "integrator_core");
482 qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
483 qdev_init_nofail(dev);
484 sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
486 cpu_pic = arm_pic_init_cpu(env);
487 dev = sysbus_create_varargs("integrator_pic", 0x14000000,
488 cpu_pic[ARM_PIC_CPU_IRQ],
489 cpu_pic[ARM_PIC_CPU_FIQ], NULL);
490 for (i = 0; i < 32; i++) {
491 pic[i] = qdev_get_gpio_in(dev, i);
493 sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
494 sysbus_create_varargs("integrator_pit", 0x13000000,
495 pic[5], pic[6], pic[7], NULL);
496 sysbus_create_simple("pl031", 0x15000000, pic[8]);
497 sysbus_create_simple("pl011", 0x16000000, pic[1]);
498 sysbus_create_simple("pl011", 0x17000000, pic[2]);
499 icp_control_init(0xcb000000);
500 sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
501 sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
502 sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
503 if (nd_table[0].vlan)
504 smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
506 sysbus_create_simple("pl110", 0xc0000000, pic[22]);
508 integrator_binfo.ram_size = ram_size;
509 integrator_binfo.kernel_filename = kernel_filename;
510 integrator_binfo.kernel_cmdline = kernel_cmdline;
511 integrator_binfo.initrd_filename = initrd_filename;
512 arm_load_kernel(env, &integrator_binfo);
515 static QEMUMachine integratorcp_machine = {
516 .name = "integratorcp",
517 .desc = "ARM Integrator/CP (ARM926EJ-S)",
518 .init = integratorcp_init,
522 static void integratorcp_machine_init(void)
524 qemu_register_machine(&integratorcp_machine);
527 machine_init(integratorcp_machine_init);
529 static SysBusDeviceInfo core_info = {
530 .init = integratorcm_init,
531 .qdev.name = "integrator_core",
532 .qdev.size = sizeof(integratorcm_state),
533 .qdev.props = (Property[]) {
534 DEFINE_PROP_UINT32("memsz", integratorcm_state, memsz, 0),
535 DEFINE_PROP_END_OF_LIST(),
539 static void integratorcp_register_devices(void)
541 sysbus_register_dev("integrator_pic", sizeof(icp_pic_state), icp_pic_init);
542 sysbus_register_withprop(&core_info);
545 device_init(integratorcp_register_devices)