2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/i386/pc.h"
26 #include "hw/char/serial.h"
27 #include "hw/i386/apic.h"
28 #include "hw/block/fdc.h"
30 #include "hw/pci/pci.h"
31 #include "monitor/monitor.h"
32 #include "hw/nvram/fw_cfg.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/i386/smbios.h"
35 #include "hw/loader.h"
37 #include "multiboot.h"
38 #include "hw/timer/mc146818rtc.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/audio/pcspk.h"
41 #include "hw/pci/msi.h"
42 #include "hw/sysbus.h"
43 #include "sysemu/sysemu.h"
44 #include "sysemu/kvm.h"
46 #include "hw/xen/xen.h"
47 #include "sysemu/blockdev.h"
48 #include "hw/block/block.h"
49 #include "ui/qemu-spice.h"
50 #include "exec/memory.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/arch_init.h"
53 #include "qemu/bitmap.h"
54 #include "qemu/config-file.h"
55 #include "hw/acpi/acpi.h"
56 #include "hw/acpi/cpu_hotplug.h"
57 #include "hw/cpu/icc_bus.h"
58 #include "hw/boards.h"
59 #include "hw/pci/pci_host.h"
60 #include "acpi-build.h"
63 #include "tizen/src/util/maru_err_table.h"
65 /* debug PC/ISA interrupts */
69 #define DPRINTF(fmt, ...) \
70 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
72 #define DPRINTF(fmt, ...)
75 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
76 #define ACPI_DATA_SIZE 0x10000
77 #define BIOS_CFG_IOPORT 0x510
78 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
79 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
80 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
81 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
82 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
84 #define E820_NR_ENTRIES 16
90 } QEMU_PACKED __attribute((__aligned__(4)));
94 struct e820_entry entry[E820_NR_ENTRIES];
95 } QEMU_PACKED __attribute((__aligned__(4)));
97 static struct e820_table e820_reserve;
98 static struct e820_entry *e820_table;
99 static unsigned e820_entries;
100 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
102 void gsi_handler(void *opaque, int n, int level)
104 GSIState *s = opaque;
106 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
107 if (n < ISA_NUM_IRQS) {
108 qemu_set_irq(s->i8259_irq[n], level);
110 qemu_set_irq(s->ioapic_irq[n], level);
113 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
118 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
120 return 0xffffffffffffffffULL;
123 /* MSDOS compatibility mode FPU exception support */
124 static qemu_irq ferr_irq;
126 void pc_register_ferr_irq(qemu_irq irq)
131 /* XXX: add IGNNE support */
132 void cpu_set_ferr(CPUX86State *s)
134 qemu_irq_raise(ferr_irq);
137 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
140 qemu_irq_lower(ferr_irq);
143 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
145 return 0xffffffffffffffffULL;
149 uint64_t cpu_get_tsc(CPUX86State *env)
151 return cpu_get_ticks();
156 static cpu_set_smm_t smm_set;
157 static void *smm_arg;
159 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
161 assert(smm_set == NULL);
162 assert(smm_arg == NULL);
167 void cpu_smm_update(CPUX86State *env)
169 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) {
170 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
176 int cpu_get_pic_interrupt(CPUX86State *env)
178 X86CPU *cpu = x86_env_get_cpu(env);
181 intno = apic_get_interrupt(cpu->apic_state);
185 /* read the irq from the PIC */
186 if (!apic_accept_pic_intr(cpu->apic_state)) {
190 intno = pic_read_irq(isa_pic);
194 static void pic_irq_request(void *opaque, int irq, int level)
196 CPUState *cs = first_cpu;
197 X86CPU *cpu = X86_CPU(cs);
199 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
200 if (cpu->apic_state) {
203 if (apic_accept_pic_intr(cpu->apic_state)) {
204 apic_deliver_pic_intr(cpu->apic_state, level);
209 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
211 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
216 /* PC cmos mappings */
218 #define REG_EQUIPMENT_BYTE 0x14
220 static int cmos_get_fd_drive_type(FDriveType fd0)
226 /* 1.44 Mb 3"5 drive */
230 /* 2.88 Mb 3"5 drive */
234 /* 1.2 Mb 5"5 drive */
237 case FDRIVE_DRV_NONE:
245 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
246 int16_t cylinders, int8_t heads, int8_t sectors)
248 rtc_set_memory(s, type_ofs, 47);
249 rtc_set_memory(s, info_ofs, cylinders);
250 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
251 rtc_set_memory(s, info_ofs + 2, heads);
252 rtc_set_memory(s, info_ofs + 3, 0xff);
253 rtc_set_memory(s, info_ofs + 4, 0xff);
254 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
255 rtc_set_memory(s, info_ofs + 6, cylinders);
256 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
257 rtc_set_memory(s, info_ofs + 8, sectors);
260 /* convert boot_device letter to something recognizable by the bios */
261 static int boot_device2nibble(char boot_device)
263 switch(boot_device) {
266 return 0x01; /* floppy boot */
268 return 0x02; /* hard drive boot */
270 return 0x03; /* CD-ROM boot */
272 return 0x04; /* Network boot */
277 static int set_boot_dev(ISADevice *s, const char *boot_device)
279 #define PC_MAX_BOOT_DEVICES 3
280 int nbds, bds[3] = { 0, };
283 nbds = strlen(boot_device);
284 if (nbds > PC_MAX_BOOT_DEVICES) {
285 error_report("Too many boot devices for PC");
288 for (i = 0; i < nbds; i++) {
289 bds[i] = boot_device2nibble(boot_device[i]);
291 error_report("Invalid boot device for PC: '%c'",
296 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
297 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
301 static int pc_boot_set(void *opaque, const char *boot_device)
303 return set_boot_dev(opaque, boot_device);
306 typedef struct pc_cmos_init_late_arg {
307 ISADevice *rtc_state;
309 } pc_cmos_init_late_arg;
311 static void pc_cmos_init_late(void *opaque)
313 pc_cmos_init_late_arg *arg = opaque;
314 ISADevice *s = arg->rtc_state;
316 int8_t heads, sectors;
321 if (ide_get_geometry(arg->idebus[0], 0,
322 &cylinders, &heads, §ors) >= 0) {
323 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
326 if (ide_get_geometry(arg->idebus[0], 1,
327 &cylinders, &heads, §ors) >= 0) {
328 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
331 rtc_set_memory(s, 0x12, val);
334 for (i = 0; i < 4; i++) {
335 /* NOTE: ide_get_geometry() returns the physical
336 geometry. It is always such that: 1 <= sects <= 63, 1
337 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
338 geometry can be different if a translation is done. */
339 if (ide_get_geometry(arg->idebus[i / 2], i % 2,
340 &cylinders, &heads, §ors) >= 0) {
341 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
342 assert((trans & ~3) == 0);
343 val |= trans << (i * 2);
346 rtc_set_memory(s, 0x39, val);
348 qemu_unregister_reset(pc_cmos_init_late, opaque);
351 typedef struct RTCCPUHotplugArg {
352 Notifier cpu_added_notifier;
353 ISADevice *rtc_state;
356 static void rtc_notify_cpu_added(Notifier *notifier, void *data)
358 RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg,
360 ISADevice *s = arg->rtc_state;
362 /* increment the number of CPUs */
363 rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1);
366 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
367 const char *boot_device,
368 ISADevice *floppy, BusState *idebus0, BusState *idebus1,
372 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
373 static pc_cmos_init_late_arg arg;
374 static RTCCPUHotplugArg cpu_hotplug_cb;
376 /* various important CMOS locations needed by PC/Bochs bios */
379 /* base memory (first MiB) */
380 val = MIN(ram_size / 1024, 640);
381 rtc_set_memory(s, 0x15, val);
382 rtc_set_memory(s, 0x16, val >> 8);
383 /* extended memory (next 64MiB) */
384 if (ram_size > 1024 * 1024) {
385 val = (ram_size - 1024 * 1024) / 1024;
391 rtc_set_memory(s, 0x17, val);
392 rtc_set_memory(s, 0x18, val >> 8);
393 rtc_set_memory(s, 0x30, val);
394 rtc_set_memory(s, 0x31, val >> 8);
395 /* memory between 16MiB and 4GiB */
396 if (ram_size > 16 * 1024 * 1024) {
397 val = (ram_size - 16 * 1024 * 1024) / 65536;
403 rtc_set_memory(s, 0x34, val);
404 rtc_set_memory(s, 0x35, val >> 8);
405 /* memory above 4GiB */
406 val = above_4g_mem_size / 65536;
407 rtc_set_memory(s, 0x5b, val);
408 rtc_set_memory(s, 0x5c, val >> 8);
409 rtc_set_memory(s, 0x5d, val >> 16);
411 /* set the number of CPU */
412 rtc_set_memory(s, 0x5f, smp_cpus - 1);
413 /* init CPU hotplug notifier */
414 cpu_hotplug_cb.rtc_state = s;
415 cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added;
416 qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier);
418 if (set_boot_dev(s, boot_device)) {
424 for (i = 0; i < 2; i++) {
425 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
428 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
429 cmos_get_fd_drive_type(fd_type[1]);
430 rtc_set_memory(s, 0x10, val);
434 if (fd_type[0] < FDRIVE_DRV_NONE) {
437 if (fd_type[1] < FDRIVE_DRV_NONE) {
444 val |= 0x01; /* 1 drive, ready for boot */
447 val |= 0x41; /* 2 drives, ready for boot */
450 val |= 0x02; /* FPU is there */
451 val |= 0x04; /* PS/2 mouse installed */
452 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
456 arg.idebus[0] = idebus0;
457 arg.idebus[1] = idebus1;
458 qemu_register_reset(pc_cmos_init_late, &arg);
461 #define TYPE_PORT92 "port92"
462 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
464 /* port 92 stuff: could be split off */
465 typedef struct Port92State {
466 ISADevice parent_obj;
473 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
476 Port92State *s = opaque;
478 DPRINTF("port92: write 0x%02x\n", val);
480 qemu_set_irq(*s->a20_out, (val >> 1) & 1);
482 qemu_system_reset_request();
486 static uint64_t port92_read(void *opaque, hwaddr addr,
489 Port92State *s = opaque;
493 DPRINTF("port92: read 0x%02x\n", ret);
497 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
499 Port92State *s = PORT92(dev);
501 s->a20_out = a20_out;
504 static const VMStateDescription vmstate_port92_isa = {
507 .minimum_version_id = 1,
508 .minimum_version_id_old = 1,
509 .fields = (VMStateField []) {
510 VMSTATE_UINT8(outport, Port92State),
511 VMSTATE_END_OF_LIST()
515 static void port92_reset(DeviceState *d)
517 Port92State *s = PORT92(d);
522 static const MemoryRegionOps port92_ops = {
524 .write = port92_write,
526 .min_access_size = 1,
527 .max_access_size = 1,
529 .endianness = DEVICE_LITTLE_ENDIAN,
532 static void port92_initfn(Object *obj)
534 Port92State *s = PORT92(obj);
536 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
541 static void port92_realizefn(DeviceState *dev, Error **errp)
543 ISADevice *isadev = ISA_DEVICE(dev);
544 Port92State *s = PORT92(dev);
546 isa_register_ioport(isadev, &s->io, 0x92);
549 static void port92_class_initfn(ObjectClass *klass, void *data)
551 DeviceClass *dc = DEVICE_CLASS(klass);
553 dc->realize = port92_realizefn;
554 dc->reset = port92_reset;
555 dc->vmsd = &vmstate_port92_isa;
557 * Reason: unlike ordinary ISA devices, this one needs additional
558 * wiring: its A20 output line needs to be wired up by
561 dc->cannot_instantiate_with_device_add_yet = true;
564 static const TypeInfo port92_info = {
566 .parent = TYPE_ISA_DEVICE,
567 .instance_size = sizeof(Port92State),
568 .instance_init = port92_initfn,
569 .class_init = port92_class_initfn,
572 static void port92_register_types(void)
574 type_register_static(&port92_info);
577 type_init(port92_register_types)
579 static void handle_a20_line_change(void *opaque, int irq, int level)
581 X86CPU *cpu = opaque;
583 /* XXX: send to all CPUs ? */
584 /* XXX: add logic to handle multiple A20 line sources */
585 x86_cpu_set_a20(cpu, level);
588 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
590 int index = le32_to_cpu(e820_reserve.count);
591 struct e820_entry *entry;
593 if (type != E820_RAM) {
594 /* old FW_CFG_E820_TABLE entry -- reservations only */
595 if (index >= E820_NR_ENTRIES) {
598 entry = &e820_reserve.entry[index++];
600 entry->address = cpu_to_le64(address);
601 entry->length = cpu_to_le64(length);
602 entry->type = cpu_to_le32(type);
604 e820_reserve.count = cpu_to_le32(index);
607 /* new "etc/e820" file -- include ram too */
608 e820_table = g_realloc(e820_table,
609 sizeof(struct e820_entry) * (e820_entries+1));
610 e820_table[e820_entries].address = cpu_to_le64(address);
611 e820_table[e820_entries].length = cpu_to_le64(length);
612 e820_table[e820_entries].type = cpu_to_le32(type);
618 /* Calculates the limit to CPU APIC ID values
620 * This function returns the limit for the APIC ID value, so that all
621 * CPU APIC IDs are < pc_apic_id_limit().
623 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
625 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
627 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
630 static FWCfgState *bochs_bios_init(void)
633 uint8_t *smbios_table;
635 uint64_t *numa_fw_cfg;
637 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
639 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
640 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
642 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
643 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
644 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
645 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
648 * So, this means we must not use max_cpus, here, but the maximum possible
649 * APIC ID value, plus one.
651 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
652 * the APIC ID, not the "CPU index"
654 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
655 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
656 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
657 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
658 acpi_tables, acpi_tables_len);
659 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
661 smbios_table = smbios_get_table(&smbios_len);
663 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
664 smbios_table, smbios_len);
665 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
666 &e820_reserve, sizeof(e820_reserve));
667 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
668 sizeof(struct e820_entry) * e820_entries);
670 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
671 /* allocate memory for the NUMA channel: one (64bit) word for the number
672 * of nodes, one word for each VCPU->node and one word for each node to
673 * hold the amount of memory.
675 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
676 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
677 for (i = 0; i < max_cpus; i++) {
678 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
679 assert(apic_id < apic_id_limit);
680 for (j = 0; j < nb_numa_nodes; j++) {
681 if (test_bit(i, node_cpumask[j])) {
682 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
687 for (i = 0; i < nb_numa_nodes; i++) {
688 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]);
690 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
691 (1 + apic_id_limit + nb_numa_nodes) *
692 sizeof(*numa_fw_cfg));
697 static long get_file_size(FILE *f)
701 /* XXX: on Unix systems, using fstat() probably makes more sense */
704 fseek(f, 0, SEEK_END);
706 fseek(f, where, SEEK_SET);
711 static void load_linux(FWCfgState *fw_cfg,
712 const char *kernel_filename,
713 const char *initrd_filename,
714 const char *kernel_cmdline,
718 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
720 uint8_t header[8192], *setup, *kernel, *initrd_data;
721 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
725 /* Align to 16 bytes as a paranoia measure */
726 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
728 /* load the kernel header */
729 f = fopen(kernel_filename, "rb");
730 if (!f || !(kernel_size = get_file_size(f)) ||
731 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
732 MIN(ARRAY_SIZE(header), kernel_size)) {
733 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
734 kernel_filename, strerror(errno));
737 char *path = get_canonical_path(kernel_filename);
738 maru_register_exit_msg(MARU_EXIT_KERNEL_FILE_EXCEPTION, path);
745 /* kernel protocol version */
747 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
749 if (ldl_p(header+0x202) == 0x53726448) {
750 protocol = lduw_p(header+0x206);
752 /* This looks like a multiboot kernel. If it is, let's stop
753 treating it like a Linux kernel. */
754 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
755 kernel_cmdline, kernel_size, header)) {
761 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
764 cmdline_addr = 0x9a000 - cmdline_size;
766 } else if (protocol < 0x202) {
767 /* High but ancient kernel */
769 cmdline_addr = 0x9a000 - cmdline_size;
770 prot_addr = 0x100000;
772 /* High and recent kernel */
774 cmdline_addr = 0x20000;
775 prot_addr = 0x100000;
780 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
781 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
782 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
788 /* highest address for loading the initrd */
789 if (protocol >= 0x203) {
790 initrd_max = ldl_p(header+0x22c);
792 initrd_max = 0x37ffffff;
795 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
796 initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
798 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
799 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
800 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
802 if (protocol >= 0x202) {
803 stl_p(header+0x228, cmdline_addr);
805 stw_p(header+0x20, 0xA33F);
806 stw_p(header+0x22, cmdline_addr-real_addr);
809 /* handle vga= parameter */
810 vmode = strstr(kernel_cmdline, "vga=");
812 unsigned int video_mode;
815 if (!strncmp(vmode, "normal", 6)) {
817 } else if (!strncmp(vmode, "ext", 3)) {
819 } else if (!strncmp(vmode, "ask", 3)) {
822 video_mode = strtol(vmode, NULL, 0);
824 stw_p(header+0x1fa, video_mode);
828 /* High nybble = B reserved for QEMU; low nybble is revision number.
829 If this code is substantially changed, you may want to consider
830 incrementing the revision. */
831 if (protocol >= 0x200) {
832 header[0x210] = 0xB0;
835 if (protocol >= 0x201) {
836 header[0x211] |= 0x80; /* CAN_USE_HEAP */
837 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
841 if (initrd_filename) {
842 if (protocol < 0x200) {
843 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
847 initrd_size = get_image_size(initrd_filename);
848 if (initrd_size < 0) {
849 fprintf(stderr, "qemu: error reading initrd %s: %s\n",
850 initrd_filename, strerror(errno));
854 initrd_addr = (initrd_max-initrd_size) & ~4095;
856 initrd_data = g_malloc(initrd_size);
857 load_image(initrd_filename, initrd_data);
859 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
860 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
861 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
863 stl_p(header+0x218, initrd_addr);
864 stl_p(header+0x21c, initrd_size);
867 /* load kernel and setup */
868 setup_size = header[0x1f1];
869 if (setup_size == 0) {
872 setup_size = (setup_size+1)*512;
873 kernel_size -= setup_size;
875 setup = g_malloc(setup_size);
876 kernel = g_malloc(kernel_size);
877 fseek(f, 0, SEEK_SET);
878 if (fread(setup, 1, setup_size, f) != setup_size) {
879 fprintf(stderr, "fread() failed\n");
882 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
883 fprintf(stderr, "fread() failed\n");
887 memcpy(setup, header, MIN(sizeof(header), setup_size));
889 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
890 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
891 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
893 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
894 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
895 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
897 option_rom[nb_option_roms].name = "linuxboot.bin";
898 option_rom[nb_option_roms].bootindex = 0;
902 #define NE2000_NB_MAX 6
904 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
906 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
908 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
910 static int nb_ne2k = 0;
912 if (nb_ne2k == NE2000_NB_MAX)
914 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
915 ne2000_irq[nb_ne2k], nd);
919 DeviceState *cpu_get_current_apic(void)
922 X86CPU *cpu = X86_CPU(current_cpu);
923 return cpu->apic_state;
929 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
931 X86CPU *cpu = opaque;
934 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
938 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id,
939 DeviceState *icc_bridge, Error **errp)
942 Error *local_err = NULL;
944 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err);
945 if (local_err != NULL) {
946 error_propagate(errp, local_err);
950 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
951 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
954 error_propagate(errp, local_err);
955 object_unref(OBJECT(cpu));
961 static const char *current_cpu_model;
963 void pc_hot_add_cpu(const int64_t id, Error **errp)
965 DeviceState *icc_bridge;
966 int64_t apic_id = x86_cpu_apic_id_from_index(id);
969 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
973 if (cpu_exists(apic_id)) {
974 error_setg(errp, "Unable to add CPU: %" PRIi64
975 ", it already exists", id);
979 if (id >= max_cpus) {
980 error_setg(errp, "Unable to add CPU: %" PRIi64
981 ", max allowed: %d", id, max_cpus - 1);
985 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
986 error_setg(errp, "Unable to add CPU: %" PRIi64
987 ", resulting APIC ID (%" PRIi64 ") is too large",
992 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge",
993 TYPE_ICC_BRIDGE, NULL));
994 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp);
997 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
1001 Error *error = NULL;
1002 unsigned long apic_id_limit;
1005 if (cpu_model == NULL) {
1006 #ifdef TARGET_X86_64
1007 cpu_model = "qemu64";
1009 cpu_model = "qemu32";
1012 current_cpu_model = cpu_model;
1014 apic_id_limit = pc_apic_id_limit(max_cpus);
1015 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) {
1016 error_report("max_cpus is too large. APIC ID of last CPU is %lu",
1021 for (i = 0; i < smp_cpus; i++) {
1022 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i),
1023 icc_bridge, &error);
1025 error_report("%s", error_get_pretty(error));
1031 /* map APIC MMIO area if CPU has APIC */
1032 if (cpu && cpu->apic_state) {
1033 /* XXX: what if the base changes? */
1034 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0,
1035 APIC_DEFAULT_ADDRESS, 0x1000);
1039 /* pci-info ROM file. Little endian format */
1040 typedef struct PcRomPciInfo {
1047 static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
1051 bool ambiguous = false;
1053 if (!guest_info->has_pci_info || !guest_info->fw_cfg) {
1056 pci_info = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1057 g_assert(!ambiguous);
1062 info = g_malloc(sizeof *info);
1063 info->w32_min = cpu_to_le64(object_property_get_int(pci_info,
1064 PCI_HOST_PROP_PCI_HOLE_START, NULL));
1065 info->w32_max = cpu_to_le64(object_property_get_int(pci_info,
1066 PCI_HOST_PROP_PCI_HOLE_END, NULL));
1067 info->w64_min = cpu_to_le64(object_property_get_int(pci_info,
1068 PCI_HOST_PROP_PCI_HOLE64_START, NULL));
1069 info->w64_max = cpu_to_le64(object_property_get_int(pci_info,
1070 PCI_HOST_PROP_PCI_HOLE64_END, NULL));
1071 /* Pass PCI hole info to guest via a side channel.
1072 * Required so guest PCI enumeration does the right thing. */
1073 fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info);
1076 typedef struct PcGuestInfoState {
1078 Notifier machine_done;
1082 void pc_guest_info_machine_done(Notifier *notifier, void *data)
1084 PcGuestInfoState *guest_info_state = container_of(notifier,
1087 pc_fw_cfg_guest_info(&guest_info_state->info);
1088 acpi_setup(&guest_info_state->info);
1091 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
1092 ram_addr_t above_4g_mem_size)
1094 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
1095 PcGuestInfo *guest_info = &guest_info_state->info;
1098 guest_info->ram_size_below_4g = below_4g_mem_size;
1099 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size;
1100 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus);
1101 guest_info->apic_xrupt_override = kvm_allows_irq0_override();
1102 guest_info->numa_nodes = nb_numa_nodes;
1103 guest_info->node_mem = g_memdup(node_mem, guest_info->numa_nodes *
1104 sizeof *guest_info->node_mem);
1105 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit *
1106 sizeof *guest_info->node_cpu);
1108 for (i = 0; i < max_cpus; i++) {
1109 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
1110 assert(apic_id < guest_info->apic_id_limit);
1111 for (j = 0; j < nb_numa_nodes; j++) {
1112 if (test_bit(i, node_cpumask[j])) {
1113 guest_info->node_cpu[apic_id] = j;
1119 guest_info_state->machine_done.notify = pc_guest_info_machine_done;
1120 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
1124 /* setup pci memory address space mapping into system address space */
1125 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
1126 MemoryRegion *pci_address_space)
1128 /* Set to lower priority than RAM */
1129 memory_region_add_subregion_overlap(system_memory, 0x0,
1130 pci_address_space, -1);
1133 void pc_acpi_init(const char *default_dsdt)
1137 if (acpi_tables != NULL) {
1138 /* manually set via -acpitable, leave it alone */
1142 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1143 if (filename == NULL) {
1144 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
1150 arg = g_strdup_printf("file=%s", filename);
1152 /* creates a deep copy of "arg" */
1153 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0);
1154 g_assert(opts != NULL);
1156 acpi_table_add_builtin(opts, &err);
1158 error_report("WARNING: failed to load %s: %s", filename,
1159 error_get_pretty(err));
1167 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
1168 const char *kernel_filename,
1169 const char *kernel_cmdline,
1170 const char *initrd_filename,
1171 ram_addr_t below_4g_mem_size,
1172 ram_addr_t above_4g_mem_size,
1173 MemoryRegion *rom_memory,
1174 MemoryRegion **ram_memory,
1175 PcGuestInfo *guest_info)
1178 MemoryRegion *ram, *option_rom_mr;
1179 MemoryRegion *ram_below_4g, *ram_above_4g;
1182 linux_boot = (kernel_filename != NULL);
1184 /* Allocate RAM. We allocate it as a single memory region and use
1185 * aliases to address portions of it, mostly for backwards compatibility
1186 * with older qemus that used qemu_ram_alloc().
1188 ram = g_malloc(sizeof(*ram));
1189 memory_region_init_ram(ram, NULL, "pc.ram",
1190 below_4g_mem_size + above_4g_mem_size);
1191 vmstate_register_ram_global(ram);
1193 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1194 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1195 0, below_4g_mem_size);
1196 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1197 e820_add_entry(0, below_4g_mem_size, E820_RAM);
1198 if (above_4g_mem_size > 0) {
1199 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1200 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1201 below_4g_mem_size, above_4g_mem_size);
1202 memory_region_add_subregion(system_memory, 0x100000000ULL,
1204 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM);
1208 /* Initialize PC system firmware */
1209 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw);
1211 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1212 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
1213 vmstate_register_ram_global(option_rom_mr);
1214 memory_region_add_subregion_overlap(rom_memory,
1219 fw_cfg = bochs_bios_init();
1223 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1226 for (i = 0; i < nb_option_roms; i++) {
1227 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1229 guest_info->fw_cfg = fw_cfg;
1233 qemu_irq *pc_allocate_cpu_irq(void)
1235 return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1238 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1240 DeviceState *dev = NULL;
1243 PCIDevice *pcidev = pci_vga_init(pci_bus);
1244 dev = pcidev ? &pcidev->qdev : NULL;
1245 } else if (isa_bus) {
1246 ISADevice *isadev = isa_vga_init(isa_bus);
1247 dev = isadev ? DEVICE(isadev) : NULL;
1252 static void cpu_request_exit(void *opaque, int irq, int level)
1254 CPUState *cpu = current_cpu;
1261 static const MemoryRegionOps ioport80_io_ops = {
1262 .write = ioport80_write,
1263 .read = ioport80_read,
1264 .endianness = DEVICE_NATIVE_ENDIAN,
1266 .min_access_size = 1,
1267 .max_access_size = 1,
1271 static const MemoryRegionOps ioportF0_io_ops = {
1272 .write = ioportF0_write,
1273 .read = ioportF0_read,
1274 .endianness = DEVICE_NATIVE_ENDIAN,
1276 .min_access_size = 1,
1277 .max_access_size = 1,
1281 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1282 ISADevice **rtc_state,
1288 DriveInfo *fd[MAX_FD];
1289 DeviceState *hpet = NULL;
1290 int pit_isa_irq = 0;
1291 qemu_irq pit_alt_irq = NULL;
1292 qemu_irq rtc_irq = NULL;
1294 ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1295 qemu_irq *cpu_exit_irq;
1296 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1297 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1299 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1300 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1302 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1303 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1306 * Check if an HPET shall be created.
1308 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1309 * when the HPET wants to take over. Thus we have to disable the latter.
1311 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1312 /* In order to set property, here not using sysbus_try_create_simple */
1313 hpet = qdev_try_create(NULL, TYPE_HPET);
1315 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1316 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1319 uint8_t compat = object_property_get_int(OBJECT(hpet),
1322 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1324 qdev_init_nofail(hpet);
1325 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1327 for (i = 0; i < GSI_NUM_PINS; i++) {
1328 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1331 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1332 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1335 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1337 qemu_register_boot_set(pc_boot_set, *rtc_state);
1339 if (!xen_enabled()) {
1340 if (kvm_irqchip_in_kernel()) {
1341 pit = kvm_pit_init(isa_bus, 0x40);
1343 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1346 /* connect PIT to output control line of the HPET */
1347 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1349 pcspk_init(isa_bus, pit);
1352 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1353 if (serial_hds[i]) {
1354 serial_isa_init(isa_bus, i, serial_hds[i]);
1358 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1359 if (parallel_hds[i]) {
1360 parallel_init(isa_bus, i, parallel_hds[i]);
1364 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1365 i8042 = isa_create_simple(isa_bus, "i8042");
1366 i8042_setup_a20_line(i8042, &a20_line[0]);
1368 vmport_init(isa_bus);
1369 vmmouse = isa_try_create(isa_bus, "vmmouse");
1374 DeviceState *dev = DEVICE(vmmouse);
1375 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1376 qdev_init_nofail(dev);
1378 port92 = isa_create_simple(isa_bus, "port92");
1379 port92_init(port92, &a20_line[1]);
1381 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1382 DMA_init(0, cpu_exit_irq);
1384 for(i = 0; i < MAX_FD; i++) {
1385 fd[i] = drive_get(IF_FLOPPY, 0, i);
1387 *floppy = fdctrl_init_isa(isa_bus, fd);
1390 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1394 for (i = 0; i < nb_nics; i++) {
1395 NICInfo *nd = &nd_table[i];
1397 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1398 pc_init_ne2k_isa(isa_bus, nd);
1400 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL);
1405 void pc_pci_device_init(PCIBus *pci_bus)
1410 max_bus = drive_get_max_bus(IF_SCSI);
1411 for (bus = 0; bus <= max_bus; bus++) {
1412 pci_create_simple(pci_bus, -1, "lsi53c895a");
1416 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1422 if (kvm_irqchip_in_kernel()) {
1423 dev = qdev_create(NULL, "kvm-ioapic");
1425 dev = qdev_create(NULL, "ioapic");
1428 object_property_add_child(object_resolve_path(parent_name, NULL),
1429 "ioapic", OBJECT(dev), NULL);
1431 qdev_init_nofail(dev);
1432 d = SYS_BUS_DEVICE(dev);
1433 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1435 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1436 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);