2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/i386/pc.h"
26 #include "hw/char/serial.h"
27 #include "hw/i386/apic.h"
28 #include "hw/block/fdc.h"
30 #include "hw/pci/pci.h"
31 #include "monitor/monitor.h"
32 #include "hw/nvram/fw_cfg.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/i386/smbios.h"
35 #include "hw/loader.h"
37 #include "multiboot.h"
38 #include "hw/timer/mc146818rtc.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/audio/pcspk.h"
41 #include "hw/pci/msi.h"
42 #include "hw/sysbus.h"
43 #include "sysemu/sysemu.h"
44 #include "sysemu/kvm.h"
46 #include "hw/xen/xen.h"
47 #include "sysemu/blockdev.h"
48 #include "hw/block/block.h"
49 #include "ui/qemu-spice.h"
50 #include "exec/memory.h"
51 #include "exec/address-spaces.h"
52 #include "sysemu/arch_init.h"
53 #include "qemu/bitmap.h"
54 #include "qemu/config-file.h"
55 #include "hw/acpi/acpi.h"
56 #include "hw/cpu/icc_bus.h"
57 #include "hw/boards.h"
58 #include "hw/pci/pci_host.h"
61 #include "../../tizen/src/maru_err_table.h"
63 /* debug PC/ISA interrupts */
67 #define DPRINTF(fmt, ...) \
68 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
70 #define DPRINTF(fmt, ...)
73 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
74 #define ACPI_DATA_SIZE 0x10000
75 #define BIOS_CFG_IOPORT 0x510
76 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
77 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
78 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
79 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
80 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
82 #define E820_NR_ENTRIES 16
88 } QEMU_PACKED __attribute((__aligned__(4)));
92 struct e820_entry entry[E820_NR_ENTRIES];
93 } QEMU_PACKED __attribute((__aligned__(4)));
95 static struct e820_table e820_table;
96 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
98 void gsi_handler(void *opaque, int n, int level)
100 GSIState *s = opaque;
102 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
103 if (n < ISA_NUM_IRQS) {
104 qemu_set_irq(s->i8259_irq[n], level);
106 qemu_set_irq(s->ioapic_irq[n], level);
109 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
114 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
116 return 0xffffffffffffffffULL;
119 /* MSDOS compatibility mode FPU exception support */
120 static qemu_irq ferr_irq;
122 void pc_register_ferr_irq(qemu_irq irq)
127 /* XXX: add IGNNE support */
128 void cpu_set_ferr(CPUX86State *s)
130 qemu_irq_raise(ferr_irq);
133 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
136 qemu_irq_lower(ferr_irq);
139 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
141 return 0xffffffffffffffffULL;
145 uint64_t cpu_get_tsc(CPUX86State *env)
147 return cpu_get_ticks();
152 static cpu_set_smm_t smm_set;
153 static void *smm_arg;
155 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
157 assert(smm_set == NULL);
158 assert(smm_arg == NULL);
163 void cpu_smm_update(CPUX86State *env)
165 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) {
166 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
172 int cpu_get_pic_interrupt(CPUX86State *env)
176 intno = apic_get_interrupt(env->apic_state);
180 /* read the irq from the PIC */
181 if (!apic_accept_pic_intr(env->apic_state)) {
185 intno = pic_read_irq(isa_pic);
189 static void pic_irq_request(void *opaque, int irq, int level)
191 CPUState *cs = first_cpu;
192 X86CPU *cpu = X86_CPU(cs);
193 CPUX86State *env = &cpu->env;
195 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
196 if (env->apic_state) {
200 if (apic_accept_pic_intr(env->apic_state)) {
201 apic_deliver_pic_intr(env->apic_state, level);
207 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
209 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
214 /* PC cmos mappings */
216 #define REG_EQUIPMENT_BYTE 0x14
218 static int cmos_get_fd_drive_type(FDriveType fd0)
224 /* 1.44 Mb 3"5 drive */
228 /* 2.88 Mb 3"5 drive */
232 /* 1.2 Mb 5"5 drive */
235 case FDRIVE_DRV_NONE:
243 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
244 int16_t cylinders, int8_t heads, int8_t sectors)
246 rtc_set_memory(s, type_ofs, 47);
247 rtc_set_memory(s, info_ofs, cylinders);
248 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
249 rtc_set_memory(s, info_ofs + 2, heads);
250 rtc_set_memory(s, info_ofs + 3, 0xff);
251 rtc_set_memory(s, info_ofs + 4, 0xff);
252 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
253 rtc_set_memory(s, info_ofs + 6, cylinders);
254 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
255 rtc_set_memory(s, info_ofs + 8, sectors);
258 /* convert boot_device letter to something recognizable by the bios */
259 static int boot_device2nibble(char boot_device)
261 switch(boot_device) {
264 return 0x01; /* floppy boot */
266 return 0x02; /* hard drive boot */
268 return 0x03; /* CD-ROM boot */
270 return 0x04; /* Network boot */
275 static int set_boot_dev(ISADevice *s, const char *boot_device)
277 #define PC_MAX_BOOT_DEVICES 3
278 int nbds, bds[3] = { 0, };
281 nbds = strlen(boot_device);
282 if (nbds > PC_MAX_BOOT_DEVICES) {
283 error_report("Too many boot devices for PC");
286 for (i = 0; i < nbds; i++) {
287 bds[i] = boot_device2nibble(boot_device[i]);
289 error_report("Invalid boot device for PC: '%c'",
294 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
295 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
299 static int pc_boot_set(void *opaque, const char *boot_device)
301 return set_boot_dev(opaque, boot_device);
304 typedef struct pc_cmos_init_late_arg {
305 ISADevice *rtc_state;
307 } pc_cmos_init_late_arg;
309 static void pc_cmos_init_late(void *opaque)
311 pc_cmos_init_late_arg *arg = opaque;
312 ISADevice *s = arg->rtc_state;
314 int8_t heads, sectors;
319 if (ide_get_geometry(arg->idebus[0], 0,
320 &cylinders, &heads, §ors) >= 0) {
321 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
324 if (ide_get_geometry(arg->idebus[0], 1,
325 &cylinders, &heads, §ors) >= 0) {
326 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
329 rtc_set_memory(s, 0x12, val);
332 for (i = 0; i < 4; i++) {
333 /* NOTE: ide_get_geometry() returns the physical
334 geometry. It is always such that: 1 <= sects <= 63, 1
335 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
336 geometry can be different if a translation is done. */
337 if (ide_get_geometry(arg->idebus[i / 2], i % 2,
338 &cylinders, &heads, §ors) >= 0) {
339 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
340 assert((trans & ~3) == 0);
341 val |= trans << (i * 2);
344 rtc_set_memory(s, 0x39, val);
346 qemu_unregister_reset(pc_cmos_init_late, opaque);
349 typedef struct RTCCPUHotplugArg {
350 Notifier cpu_added_notifier;
351 ISADevice *rtc_state;
354 static void rtc_notify_cpu_added(Notifier *notifier, void *data)
356 RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg,
358 ISADevice *s = arg->rtc_state;
360 /* increment the number of CPUs */
361 rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1);
364 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
365 const char *boot_device,
366 ISADevice *floppy, BusState *idebus0, BusState *idebus1,
370 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
371 static pc_cmos_init_late_arg arg;
372 static RTCCPUHotplugArg cpu_hotplug_cb;
374 /* various important CMOS locations needed by PC/Bochs bios */
377 /* base memory (first MiB) */
378 val = MIN(ram_size / 1024, 640);
379 rtc_set_memory(s, 0x15, val);
380 rtc_set_memory(s, 0x16, val >> 8);
381 /* extended memory (next 64MiB) */
382 if (ram_size > 1024 * 1024) {
383 val = (ram_size - 1024 * 1024) / 1024;
389 rtc_set_memory(s, 0x17, val);
390 rtc_set_memory(s, 0x18, val >> 8);
391 rtc_set_memory(s, 0x30, val);
392 rtc_set_memory(s, 0x31, val >> 8);
393 /* memory between 16MiB and 4GiB */
394 if (ram_size > 16 * 1024 * 1024) {
395 val = (ram_size - 16 * 1024 * 1024) / 65536;
401 rtc_set_memory(s, 0x34, val);
402 rtc_set_memory(s, 0x35, val >> 8);
403 /* memory above 4GiB */
404 val = above_4g_mem_size / 65536;
405 rtc_set_memory(s, 0x5b, val);
406 rtc_set_memory(s, 0x5c, val >> 8);
407 rtc_set_memory(s, 0x5d, val >> 16);
409 /* set the number of CPU */
410 rtc_set_memory(s, 0x5f, smp_cpus - 1);
411 /* init CPU hotplug notifier */
412 cpu_hotplug_cb.rtc_state = s;
413 cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added;
414 qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier);
416 if (set_boot_dev(s, boot_device)) {
422 for (i = 0; i < 2; i++) {
423 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
426 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
427 cmos_get_fd_drive_type(fd_type[1]);
428 rtc_set_memory(s, 0x10, val);
432 if (fd_type[0] < FDRIVE_DRV_NONE) {
435 if (fd_type[1] < FDRIVE_DRV_NONE) {
442 val |= 0x01; /* 1 drive, ready for boot */
445 val |= 0x41; /* 2 drives, ready for boot */
448 val |= 0x02; /* FPU is there */
449 val |= 0x04; /* PS/2 mouse installed */
450 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
454 arg.idebus[0] = idebus0;
455 arg.idebus[1] = idebus1;
456 qemu_register_reset(pc_cmos_init_late, &arg);
459 #define TYPE_PORT92 "port92"
460 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
462 /* port 92 stuff: could be split off */
463 typedef struct Port92State {
464 ISADevice parent_obj;
471 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
474 Port92State *s = opaque;
476 DPRINTF("port92: write 0x%02x\n", val);
478 qemu_set_irq(*s->a20_out, (val >> 1) & 1);
480 qemu_system_reset_request();
484 static uint64_t port92_read(void *opaque, hwaddr addr,
487 Port92State *s = opaque;
491 DPRINTF("port92: read 0x%02x\n", ret);
495 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
497 Port92State *s = PORT92(dev);
499 s->a20_out = a20_out;
502 static const VMStateDescription vmstate_port92_isa = {
505 .minimum_version_id = 1,
506 .minimum_version_id_old = 1,
507 .fields = (VMStateField []) {
508 VMSTATE_UINT8(outport, Port92State),
509 VMSTATE_END_OF_LIST()
513 static void port92_reset(DeviceState *d)
515 Port92State *s = PORT92(d);
520 static const MemoryRegionOps port92_ops = {
522 .write = port92_write,
524 .min_access_size = 1,
525 .max_access_size = 1,
527 .endianness = DEVICE_LITTLE_ENDIAN,
530 static void port92_initfn(Object *obj)
532 Port92State *s = PORT92(obj);
534 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
539 static void port92_realizefn(DeviceState *dev, Error **errp)
541 ISADevice *isadev = ISA_DEVICE(dev);
542 Port92State *s = PORT92(dev);
544 isa_register_ioport(isadev, &s->io, 0x92);
547 static void port92_class_initfn(ObjectClass *klass, void *data)
549 DeviceClass *dc = DEVICE_CLASS(klass);
552 dc->realize = port92_realizefn;
553 dc->reset = port92_reset;
554 dc->vmsd = &vmstate_port92_isa;
557 static const TypeInfo port92_info = {
559 .parent = TYPE_ISA_DEVICE,
560 .instance_size = sizeof(Port92State),
561 .instance_init = port92_initfn,
562 .class_init = port92_class_initfn,
565 static void port92_register_types(void)
567 type_register_static(&port92_info);
570 type_init(port92_register_types)
572 static void handle_a20_line_change(void *opaque, int irq, int level)
574 X86CPU *cpu = opaque;
576 /* XXX: send to all CPUs ? */
577 /* XXX: add logic to handle multiple A20 line sources */
578 x86_cpu_set_a20(cpu, level);
581 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
583 int index = le32_to_cpu(e820_table.count);
584 struct e820_entry *entry;
586 if (index >= E820_NR_ENTRIES)
588 entry = &e820_table.entry[index++];
590 entry->address = cpu_to_le64(address);
591 entry->length = cpu_to_le64(length);
592 entry->type = cpu_to_le32(type);
594 e820_table.count = cpu_to_le32(index);
598 /* Calculates the limit to CPU APIC ID values
600 * This function returns the limit for the APIC ID value, so that all
601 * CPU APIC IDs are < pc_apic_id_limit().
603 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init().
605 static unsigned int pc_apic_id_limit(unsigned int max_cpus)
607 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1;
610 static FWCfgState *bochs_bios_init(void)
613 uint8_t *smbios_table;
615 uint64_t *numa_fw_cfg;
617 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
619 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
620 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
622 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
623 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC
624 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the
625 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS
628 * So, this means we must not use max_cpus, here, but the maximum possible
629 * APIC ID value, plus one.
631 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is
632 * the APIC ID, not the "CPU index"
634 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit);
635 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
636 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
637 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
638 acpi_tables, acpi_tables_len);
639 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
641 smbios_table = smbios_get_table(&smbios_len);
643 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
644 smbios_table, smbios_len);
645 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
646 &e820_table, sizeof(e820_table));
648 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
649 /* allocate memory for the NUMA channel: one (64bit) word for the number
650 * of nodes, one word for each VCPU->node and one word for each node to
651 * hold the amount of memory.
653 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
654 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
655 for (i = 0; i < max_cpus; i++) {
656 unsigned int apic_id = x86_cpu_apic_id_from_index(i);
657 assert(apic_id < apic_id_limit);
658 for (j = 0; j < nb_numa_nodes; j++) {
659 if (test_bit(i, node_cpumask[j])) {
660 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j);
665 for (i = 0; i < nb_numa_nodes; i++) {
666 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]);
668 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
669 (1 + apic_id_limit + nb_numa_nodes) *
670 sizeof(*numa_fw_cfg));
675 static long get_file_size(FILE *f)
679 /* XXX: on Unix systems, using fstat() probably makes more sense */
682 fseek(f, 0, SEEK_END);
684 fseek(f, where, SEEK_SET);
689 static void load_linux(FWCfgState *fw_cfg,
690 const char *kernel_filename,
691 const char *initrd_filename,
692 const char *kernel_cmdline,
696 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
698 uint8_t header[8192], *setup, *kernel, *initrd_data;
699 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
703 /* Align to 16 bytes as a paranoia measure */
704 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
706 /* load the kernel header */
707 f = fopen(kernel_filename, "rb");
708 if (!f || !(kernel_size = get_file_size(f)) ||
709 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
710 MIN(ARRAY_SIZE(header), kernel_size)) {
711 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
712 kernel_filename, strerror(errno));
715 char *error_msg = NULL;
717 error_msg = maru_convert_path(error_msg, kernel_filename);
718 maru_register_exit_msg(MARU_EXIT_KERNEL_FILE_EXCEPTION, error_msg);
726 /* kernel protocol version */
728 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
730 if (ldl_p(header+0x202) == 0x53726448) {
731 protocol = lduw_p(header+0x206);
733 /* This looks like a multiboot kernel. If it is, let's stop
734 treating it like a Linux kernel. */
735 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
736 kernel_cmdline, kernel_size, header)) {
742 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
745 cmdline_addr = 0x9a000 - cmdline_size;
747 } else if (protocol < 0x202) {
748 /* High but ancient kernel */
750 cmdline_addr = 0x9a000 - cmdline_size;
751 prot_addr = 0x100000;
753 /* High and recent kernel */
755 cmdline_addr = 0x20000;
756 prot_addr = 0x100000;
761 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
762 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
763 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
769 /* highest address for loading the initrd */
770 if (protocol >= 0x203) {
771 initrd_max = ldl_p(header+0x22c);
773 initrd_max = 0x37ffffff;
776 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
777 initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
779 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
780 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
781 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
783 if (protocol >= 0x202) {
784 stl_p(header+0x228, cmdline_addr);
786 stw_p(header+0x20, 0xA33F);
787 stw_p(header+0x22, cmdline_addr-real_addr);
790 /* handle vga= parameter */
791 vmode = strstr(kernel_cmdline, "vga=");
793 unsigned int video_mode;
796 if (!strncmp(vmode, "normal", 6)) {
798 } else if (!strncmp(vmode, "ext", 3)) {
800 } else if (!strncmp(vmode, "ask", 3)) {
803 video_mode = strtol(vmode, NULL, 0);
805 stw_p(header+0x1fa, video_mode);
809 /* High nybble = B reserved for QEMU; low nybble is revision number.
810 If this code is substantially changed, you may want to consider
811 incrementing the revision. */
812 if (protocol >= 0x200) {
813 header[0x210] = 0xB0;
816 if (protocol >= 0x201) {
817 header[0x211] |= 0x80; /* CAN_USE_HEAP */
818 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
822 if (initrd_filename) {
823 if (protocol < 0x200) {
824 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
828 initrd_size = get_image_size(initrd_filename);
829 if (initrd_size < 0) {
830 fprintf(stderr, "qemu: error reading initrd %s\n",
835 initrd_addr = (initrd_max-initrd_size) & ~4095;
837 initrd_data = g_malloc(initrd_size);
838 load_image(initrd_filename, initrd_data);
840 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
841 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
842 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
844 stl_p(header+0x218, initrd_addr);
845 stl_p(header+0x21c, initrd_size);
848 /* load kernel and setup */
849 setup_size = header[0x1f1];
850 if (setup_size == 0) {
853 setup_size = (setup_size+1)*512;
854 kernel_size -= setup_size;
856 setup = g_malloc(setup_size);
857 kernel = g_malloc(kernel_size);
858 fseek(f, 0, SEEK_SET);
859 if (fread(setup, 1, setup_size, f) != setup_size) {
860 fprintf(stderr, "fread() failed\n");
863 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
864 fprintf(stderr, "fread() failed\n");
868 memcpy(setup, header, MIN(sizeof(header), setup_size));
870 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
871 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
872 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
874 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
875 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
876 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
878 option_rom[nb_option_roms].name = "linuxboot.bin";
879 option_rom[nb_option_roms].bootindex = 0;
883 #define NE2000_NB_MAX 6
885 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
887 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
889 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
890 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
892 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
894 static int nb_ne2k = 0;
896 if (nb_ne2k == NE2000_NB_MAX)
898 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
899 ne2000_irq[nb_ne2k], nd);
903 DeviceState *cpu_get_current_apic(void)
906 X86CPU *cpu = X86_CPU(current_cpu);
907 return cpu->env.apic_state;
913 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
915 X86CPU *cpu = opaque;
918 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
922 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id,
923 DeviceState *icc_bridge, Error **errp)
926 Error *local_err = NULL;
928 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err);
929 if (local_err != NULL) {
930 error_propagate(errp, local_err);
934 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err);
935 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
938 error_propagate(errp, local_err);
939 object_unref(OBJECT(cpu));
945 static const char *current_cpu_model;
947 void pc_hot_add_cpu(const int64_t id, Error **errp)
949 DeviceState *icc_bridge;
950 int64_t apic_id = x86_cpu_apic_id_from_index(id);
953 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
957 if (cpu_exists(apic_id)) {
958 error_setg(errp, "Unable to add CPU: %" PRIi64
959 ", it already exists", id);
963 if (id >= max_cpus) {
964 error_setg(errp, "Unable to add CPU: %" PRIi64
965 ", max allowed: %d", id, max_cpus - 1);
969 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge",
970 TYPE_ICC_BRIDGE, NULL));
971 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp);
974 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
981 if (cpu_model == NULL) {
983 cpu_model = "qemu64";
985 cpu_model = "qemu32";
988 current_cpu_model = cpu_model;
990 for (i = 0; i < smp_cpus; i++) {
991 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i),
994 fprintf(stderr, "%s\n", error_get_pretty(error));
1000 /* map APIC MMIO area if CPU has APIC */
1001 if (cpu && cpu->env.apic_state) {
1002 /* XXX: what if the base changes? */
1003 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0,
1004 APIC_DEFAULT_ADDRESS, 0x1000);
1008 /* pci-info ROM file. Little endian format */
1009 typedef struct PcRomPciInfo {
1016 static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
1020 bool ambiguous = false;
1022 if (!guest_info->has_pci_info || !guest_info->fw_cfg) {
1025 pci_info = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1026 g_assert(!ambiguous);
1031 info = g_malloc(sizeof *info);
1032 info->w32_min = cpu_to_le64(object_property_get_int(pci_info,
1033 PCI_HOST_PROP_PCI_HOLE_START, NULL));
1034 info->w32_max = cpu_to_le64(object_property_get_int(pci_info,
1035 PCI_HOST_PROP_PCI_HOLE_END, NULL));
1036 info->w64_min = cpu_to_le64(object_property_get_int(pci_info,
1037 PCI_HOST_PROP_PCI_HOLE64_START, NULL));
1038 info->w64_max = cpu_to_le64(object_property_get_int(pci_info,
1039 PCI_HOST_PROP_PCI_HOLE64_END, NULL));
1040 /* Pass PCI hole info to guest via a side channel.
1041 * Required so guest PCI enumeration does the right thing. */
1042 fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info);
1045 typedef struct PcGuestInfoState {
1047 Notifier machine_done;
1051 void pc_guest_info_machine_done(Notifier *notifier, void *data)
1053 PcGuestInfoState *guest_info_state = container_of(notifier,
1056 pc_fw_cfg_guest_info(&guest_info_state->info);
1059 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
1060 ram_addr_t above_4g_mem_size)
1062 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
1063 PcGuestInfo *guest_info = &guest_info_state->info;
1065 guest_info_state->machine_done.notify = pc_guest_info_machine_done;
1066 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
1070 void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
1071 uint64_t pci_hole64_size)
1073 if ((sizeof(hwaddr) == 4) || (!pci_hole64_size)) {
1077 * BIOS does not set MTRR entries for the 64 bit window, so no need to
1078 * align address to power of two. Align address at 1G, this makes sure
1079 * it can be exactly covered with a PAT entry even when using huge
1082 pci_info->w64.begin = ROUND_UP(pci_hole64_start, 0x1ULL << 30);
1083 pci_info->w64.end = pci_info->w64.begin + pci_hole64_size;
1084 assert(pci_info->w64.begin <= pci_info->w64.end);
1087 void pc_acpi_init(const char *default_dsdt)
1091 if (acpi_tables != NULL) {
1092 /* manually set via -acpitable, leave it alone */
1096 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt);
1097 if (filename == NULL) {
1098 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt);
1104 arg = g_strdup_printf("file=%s", filename);
1106 /* creates a deep copy of "arg" */
1107 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0);
1108 g_assert(opts != NULL);
1110 acpi_table_add(opts, &err);
1112 fprintf(stderr, "WARNING: failed to load %s: %s\n", filename,
1113 error_get_pretty(err));
1121 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
1122 const char *kernel_filename,
1123 const char *kernel_cmdline,
1124 const char *initrd_filename,
1125 ram_addr_t below_4g_mem_size,
1126 ram_addr_t above_4g_mem_size,
1127 MemoryRegion *rom_memory,
1128 MemoryRegion **ram_memory,
1129 PcGuestInfo *guest_info)
1132 MemoryRegion *ram, *option_rom_mr;
1133 MemoryRegion *ram_below_4g, *ram_above_4g;
1136 linux_boot = (kernel_filename != NULL);
1138 /* Allocate RAM. We allocate it as a single memory region and use
1139 * aliases to address portions of it, mostly for backwards compatibility
1140 * with older qemus that used qemu_ram_alloc().
1142 ram = g_malloc(sizeof(*ram));
1143 memory_region_init_ram(ram, NULL, "pc.ram",
1144 below_4g_mem_size + above_4g_mem_size);
1145 vmstate_register_ram_global(ram);
1147 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1148 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram,
1149 0, below_4g_mem_size);
1150 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1151 if (above_4g_mem_size > 0) {
1152 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1153 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram,
1154 below_4g_mem_size, above_4g_mem_size);
1155 memory_region_add_subregion(system_memory, 0x100000000ULL,
1160 /* Initialize PC system firmware */
1161 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw);
1163 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1164 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
1165 vmstate_register_ram_global(option_rom_mr);
1166 memory_region_add_subregion_overlap(rom_memory,
1171 fw_cfg = bochs_bios_init();
1175 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1178 for (i = 0; i < nb_option_roms; i++) {
1179 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1181 guest_info->fw_cfg = fw_cfg;
1185 qemu_irq *pc_allocate_cpu_irq(void)
1187 return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1190 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1192 DeviceState *dev = NULL;
1195 PCIDevice *pcidev = pci_vga_init(pci_bus);
1196 dev = pcidev ? &pcidev->qdev : NULL;
1197 } else if (isa_bus) {
1198 ISADevice *isadev = isa_vga_init(isa_bus);
1199 dev = isadev ? DEVICE(isadev) : NULL;
1204 static void cpu_request_exit(void *opaque, int irq, int level)
1206 CPUState *cpu = current_cpu;
1213 static const MemoryRegionOps ioport80_io_ops = {
1214 .write = ioport80_write,
1215 .read = ioport80_read,
1216 .endianness = DEVICE_NATIVE_ENDIAN,
1218 .min_access_size = 1,
1219 .max_access_size = 1,
1223 static const MemoryRegionOps ioportF0_io_ops = {
1224 .write = ioportF0_write,
1225 .read = ioportF0_read,
1226 .endianness = DEVICE_NATIVE_ENDIAN,
1228 .min_access_size = 1,
1229 .max_access_size = 1,
1233 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1234 ISADevice **rtc_state,
1239 DriveInfo *fd[MAX_FD];
1240 DeviceState *hpet = NULL;
1241 int pit_isa_irq = 0;
1242 qemu_irq pit_alt_irq = NULL;
1243 qemu_irq rtc_irq = NULL;
1245 ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1246 qemu_irq *cpu_exit_irq;
1247 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1248 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1250 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1251 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1253 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1254 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1257 * Check if an HPET shall be created.
1259 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1260 * when the HPET wants to take over. Thus we have to disable the latter.
1262 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1263 hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1266 for (i = 0; i < GSI_NUM_PINS; i++) {
1267 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1270 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1271 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1274 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1276 qemu_register_boot_set(pc_boot_set, *rtc_state);
1278 if (!xen_enabled()) {
1279 if (kvm_irqchip_in_kernel()) {
1280 pit = kvm_pit_init(isa_bus, 0x40);
1282 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1285 /* connect PIT to output control line of the HPET */
1286 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1288 pcspk_init(isa_bus, pit);
1291 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1292 if (serial_hds[i]) {
1293 serial_isa_init(isa_bus, i, serial_hds[i]);
1297 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1298 if (parallel_hds[i]) {
1299 parallel_init(isa_bus, i, parallel_hds[i]);
1303 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1304 i8042 = isa_create_simple(isa_bus, "i8042");
1305 i8042_setup_a20_line(i8042, &a20_line[0]);
1307 vmport_init(isa_bus);
1308 vmmouse = isa_try_create(isa_bus, "vmmouse");
1313 DeviceState *dev = DEVICE(vmmouse);
1314 qdev_prop_set_ptr(dev, "ps2_mouse", i8042);
1315 qdev_init_nofail(dev);
1317 port92 = isa_create_simple(isa_bus, "port92");
1318 port92_init(port92, &a20_line[1]);
1320 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1321 DMA_init(0, cpu_exit_irq);
1323 for(i = 0; i < MAX_FD; i++) {
1324 fd[i] = drive_get(IF_FLOPPY, 0, i);
1326 *floppy = fdctrl_init_isa(isa_bus, fd);
1329 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
1333 for (i = 0; i < nb_nics; i++) {
1334 NICInfo *nd = &nd_table[i];
1336 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
1337 pc_init_ne2k_isa(isa_bus, nd);
1339 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL);
1344 void pc_pci_device_init(PCIBus *pci_bus)
1349 max_bus = drive_get_max_bus(IF_SCSI);
1350 for (bus = 0; bus <= max_bus; bus++) {
1351 pci_create_simple(pci_bus, -1, "lsi53c895a");
1355 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
1361 if (kvm_irqchip_in_kernel()) {
1362 dev = qdev_create(NULL, "kvm-ioapic");
1364 dev = qdev_create(NULL, "ioapic");
1367 object_property_add_child(object_resolve_path(parent_name, NULL),
1368 "ioapic", OBJECT(dev), NULL);
1370 qdev_init_nofail(dev);
1371 d = SYS_BUS_DEVICE(dev);
1372 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS);
1374 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1375 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);