2 * QEMU GT64120 PCI host
4 * Copyright (c) 2006,2007 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
34 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
36 #define DPRINTF(fmt, ...)
39 #define GT_REGS (0x1000 >> 2)
41 /* CPU Configuration */
42 #define GT_CPU (0x000 >> 2)
43 #define GT_MULTI (0x120 >> 2)
45 /* CPU Address Decode */
46 #define GT_SCS10LD (0x008 >> 2)
47 #define GT_SCS10HD (0x010 >> 2)
48 #define GT_SCS32LD (0x018 >> 2)
49 #define GT_SCS32HD (0x020 >> 2)
50 #define GT_CS20LD (0x028 >> 2)
51 #define GT_CS20HD (0x030 >> 2)
52 #define GT_CS3BOOTLD (0x038 >> 2)
53 #define GT_CS3BOOTHD (0x040 >> 2)
54 #define GT_PCI0IOLD (0x048 >> 2)
55 #define GT_PCI0IOHD (0x050 >> 2)
56 #define GT_PCI0M0LD (0x058 >> 2)
57 #define GT_PCI0M0HD (0x060 >> 2)
58 #define GT_PCI0M1LD (0x080 >> 2)
59 #define GT_PCI0M1HD (0x088 >> 2)
60 #define GT_PCI1IOLD (0x090 >> 2)
61 #define GT_PCI1IOHD (0x098 >> 2)
62 #define GT_PCI1M0LD (0x0a0 >> 2)
63 #define GT_PCI1M0HD (0x0a8 >> 2)
64 #define GT_PCI1M1LD (0x0b0 >> 2)
65 #define GT_PCI1M1HD (0x0b8 >> 2)
66 #define GT_ISD (0x068 >> 2)
68 #define GT_SCS10AR (0x0d0 >> 2)
69 #define GT_SCS32AR (0x0d8 >> 2)
70 #define GT_CS20R (0x0e0 >> 2)
71 #define GT_CS3BOOTR (0x0e8 >> 2)
73 #define GT_PCI0IOREMAP (0x0f0 >> 2)
74 #define GT_PCI0M0REMAP (0x0f8 >> 2)
75 #define GT_PCI0M1REMAP (0x100 >> 2)
76 #define GT_PCI1IOREMAP (0x108 >> 2)
77 #define GT_PCI1M0REMAP (0x110 >> 2)
78 #define GT_PCI1M1REMAP (0x118 >> 2)
80 /* CPU Error Report */
81 #define GT_CPUERR_ADDRLO (0x070 >> 2)
82 #define GT_CPUERR_ADDRHI (0x078 >> 2)
83 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
84 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
85 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
87 /* CPU Sync Barrier */
88 #define GT_PCI0SYNC (0x0c0 >> 2)
89 #define GT_PCI1SYNC (0x0c8 >> 2)
91 /* SDRAM and Device Address Decode */
92 #define GT_SCS0LD (0x400 >> 2)
93 #define GT_SCS0HD (0x404 >> 2)
94 #define GT_SCS1LD (0x408 >> 2)
95 #define GT_SCS1HD (0x40c >> 2)
96 #define GT_SCS2LD (0x410 >> 2)
97 #define GT_SCS2HD (0x414 >> 2)
98 #define GT_SCS3LD (0x418 >> 2)
99 #define GT_SCS3HD (0x41c >> 2)
100 #define GT_CS0LD (0x420 >> 2)
101 #define GT_CS0HD (0x424 >> 2)
102 #define GT_CS1LD (0x428 >> 2)
103 #define GT_CS1HD (0x42c >> 2)
104 #define GT_CS2LD (0x430 >> 2)
105 #define GT_CS2HD (0x434 >> 2)
106 #define GT_CS3LD (0x438 >> 2)
107 #define GT_CS3HD (0x43c >> 2)
108 #define GT_BOOTLD (0x440 >> 2)
109 #define GT_BOOTHD (0x444 >> 2)
110 #define GT_ADERR (0x470 >> 2)
112 /* SDRAM Configuration */
113 #define GT_SDRAM_CFG (0x448 >> 2)
114 #define GT_SDRAM_OPMODE (0x474 >> 2)
115 #define GT_SDRAM_BM (0x478 >> 2)
116 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
118 /* SDRAM Parameters */
119 #define GT_SDRAM_B0 (0x44c >> 2)
120 #define GT_SDRAM_B1 (0x450 >> 2)
121 #define GT_SDRAM_B2 (0x454 >> 2)
122 #define GT_SDRAM_B3 (0x458 >> 2)
124 /* Device Parameters */
125 #define GT_DEV_B0 (0x45c >> 2)
126 #define GT_DEV_B1 (0x460 >> 2)
127 #define GT_DEV_B2 (0x464 >> 2)
128 #define GT_DEV_B3 (0x468 >> 2)
129 #define GT_DEV_BOOT (0x46c >> 2)
132 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
133 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
134 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
135 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
136 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
139 #define GT_DMA0_CNT (0x800 >> 2)
140 #define GT_DMA1_CNT (0x804 >> 2)
141 #define GT_DMA2_CNT (0x808 >> 2)
142 #define GT_DMA3_CNT (0x80c >> 2)
143 #define GT_DMA0_SA (0x810 >> 2)
144 #define GT_DMA1_SA (0x814 >> 2)
145 #define GT_DMA2_SA (0x818 >> 2)
146 #define GT_DMA3_SA (0x81c >> 2)
147 #define GT_DMA0_DA (0x820 >> 2)
148 #define GT_DMA1_DA (0x824 >> 2)
149 #define GT_DMA2_DA (0x828 >> 2)
150 #define GT_DMA3_DA (0x82c >> 2)
151 #define GT_DMA0_NEXT (0x830 >> 2)
152 #define GT_DMA1_NEXT (0x834 >> 2)
153 #define GT_DMA2_NEXT (0x838 >> 2)
154 #define GT_DMA3_NEXT (0x83c >> 2)
155 #define GT_DMA0_CUR (0x870 >> 2)
156 #define GT_DMA1_CUR (0x874 >> 2)
157 #define GT_DMA2_CUR (0x878 >> 2)
158 #define GT_DMA3_CUR (0x87c >> 2)
160 /* DMA Channel Control */
161 #define GT_DMA0_CTRL (0x840 >> 2)
162 #define GT_DMA1_CTRL (0x844 >> 2)
163 #define GT_DMA2_CTRL (0x848 >> 2)
164 #define GT_DMA3_CTRL (0x84c >> 2)
167 #define GT_DMA_ARB (0x860 >> 2)
170 #define GT_TC0 (0x850 >> 2)
171 #define GT_TC1 (0x854 >> 2)
172 #define GT_TC2 (0x858 >> 2)
173 #define GT_TC3 (0x85c >> 2)
174 #define GT_TC_CONTROL (0x864 >> 2)
177 #define GT_PCI0_CMD (0xc00 >> 2)
178 #define GT_PCI0_TOR (0xc04 >> 2)
179 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
180 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
181 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
182 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
183 #define GT_PCI1_IACK (0xc30 >> 2)
184 #define GT_PCI0_IACK (0xc34 >> 2)
185 #define GT_PCI0_BARE (0xc3c >> 2)
186 #define GT_PCI0_PREFMBR (0xc40 >> 2)
187 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
188 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
189 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
190 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
191 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
192 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
193 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
194 #define GT_PCI1_CMD (0xc80 >> 2)
195 #define GT_PCI1_TOR (0xc84 >> 2)
196 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
197 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
198 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
199 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
200 #define GT_PCI1_BARE (0xcbc >> 2)
201 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
202 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
203 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
204 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
205 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
206 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
207 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
208 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
209 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
210 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
211 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
212 #define GT_PCI0_CFGDATA (0xcfc >> 2)
215 #define GT_INTRCAUSE (0xc18 >> 2)
216 #define GT_INTRMASK (0xc1c >> 2)
217 #define GT_PCI0_ICMASK (0xc24 >> 2)
218 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
219 #define GT_CPU_INTSEL (0xc70 >> 2)
220 #define GT_PCI0_INTSEL (0xc74 >> 2)
221 #define GT_HINTRCAUSE (0xc98 >> 2)
222 #define GT_HINTRMASK (0xc9c >> 2)
223 #define GT_PCI0_HICMASK (0xca4 >> 2)
224 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
226 #define PCI_MAPPING_ENTRY(regname) \
227 target_phys_addr_t regname ##_start; \
228 target_phys_addr_t regname ##_length; \
229 int regname ##_handle
231 typedef struct GT64120State {
234 uint32_t regs[GT_REGS];
235 PCI_MAPPING_ENTRY(PCI0IO);
236 PCI_MAPPING_ENTRY(ISD);
239 /* Adjust range to avoid touching space which isn't mappable via PCI */
240 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
241 0x1fc00000 - 0x1fd00000 */
242 static void check_reserved_space (target_phys_addr_t *start,
243 target_phys_addr_t *length)
245 target_phys_addr_t begin = *start;
246 target_phys_addr_t end = *start + *length;
248 if (end >= 0x1e000000LL && end < 0x1f100000LL)
250 if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
251 begin = 0x1f100000LL;
252 if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
254 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
255 begin = 0x1fd00000LL;
256 /* XXX: This is broken when a reserved range splits the requested range */
257 if (end >= 0x1f100000LL && begin < 0x1e000000LL)
259 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
263 *length = end - begin;
266 static void gt64120_isd_mapping(GT64120State *s)
268 target_phys_addr_t start = s->regs[GT_ISD] << 21;
269 target_phys_addr_t length = 0x1000;
272 cpu_register_physical_memory(s->ISD_start, s->ISD_length,
274 check_reserved_space(&start, &length);
276 /* Map new address */
277 DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx" -> "TARGET_FMT_plx"@"TARGET_FMT_plx", %x\n", s->ISD_length, s->ISD_start,
278 length, start, s->ISD_handle);
279 s->ISD_start = start;
280 s->ISD_length = length;
281 cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle);
284 static void gt64120_pci_mapping(GT64120State *s)
286 /* Update IO mapping */
287 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
289 /* Unmap old IO address */
290 if (s->PCI0IO_length)
292 cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);
294 /* Map new IO address */
295 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
296 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
297 isa_mem_base = s->PCI0IO_start;
298 isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
302 static void gt64120_writel (void *opaque, target_phys_addr_t addr,
305 GT64120State *s = opaque;
308 if (!(s->regs[GT_CPU] & 0x00001000))
311 saddr = (addr & 0xfff) >> 2;
314 /* CPU Configuration */
316 s->regs[GT_CPU] = val;
319 /* Read-only register as only one GT64xxx is present on the CPU bus */
322 /* CPU Address Decode */
324 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
325 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
326 gt64120_pci_mapping(s);
329 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
330 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
333 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
334 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
337 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
338 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
341 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
342 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
345 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
346 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
349 s->regs[saddr] = val & 0x0000007f;
350 gt64120_pci_mapping(s);
357 s->regs[saddr] = val & 0x0000007f;
360 s->regs[saddr] = val & 0x00007fff;
361 gt64120_isd_mapping(s);
370 s->regs[saddr] = val & 0x000007ff;
373 /* CPU Error Report */
374 case GT_CPUERR_ADDRLO:
375 case GT_CPUERR_ADDRHI:
376 case GT_CPUERR_DATALO:
377 case GT_CPUERR_DATAHI:
378 case GT_CPUERR_PARITY:
379 /* Read-only registers, do nothing */
382 /* CPU Sync Barrier */
385 /* Read-only registers, do nothing */
388 /* SDRAM and Device Address Decode */
408 /* SDRAM Configuration */
410 case GT_SDRAM_OPMODE:
412 case GT_SDRAM_ADDRDECODE:
413 /* Accept and ignore SDRAM interleave configuration */
414 s->regs[saddr] = val;
417 /* Device Parameters */
423 /* Not implemented */
424 DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
428 case GT_ECC_ERRDATALO:
429 case GT_ECC_ERRDATAHI:
433 /* Read-only registers, do nothing */
457 /* Not implemented */
458 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
461 /* DMA Channel Control */
466 /* Not implemented */
467 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
472 /* Not implemented */
473 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
482 /* Not implemented */
483 DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
489 s->regs[saddr] = val & 0x0401fc0f;
492 case GT_PCI0_BS_SCS10:
493 case GT_PCI0_BS_SCS32:
494 case GT_PCI0_BS_CS20:
495 case GT_PCI0_BS_CS3BT:
499 case GT_PCI0_PREFMBR:
500 case GT_PCI0_SCS10_BAR:
501 case GT_PCI0_SCS32_BAR:
502 case GT_PCI0_CS20_BAR:
503 case GT_PCI0_CS3BT_BAR:
504 case GT_PCI0_SSCS10_BAR:
505 case GT_PCI0_SSCS32_BAR:
506 case GT_PCI0_SCS3BT_BAR:
508 case GT_PCI1_BS_SCS10:
509 case GT_PCI1_BS_SCS32:
510 case GT_PCI1_BS_CS20:
511 case GT_PCI1_BS_CS3BT:
513 case GT_PCI1_PREFMBR:
514 case GT_PCI1_SCS10_BAR:
515 case GT_PCI1_SCS32_BAR:
516 case GT_PCI1_CS20_BAR:
517 case GT_PCI1_CS3BT_BAR:
518 case GT_PCI1_SSCS10_BAR:
519 case GT_PCI1_SSCS32_BAR:
520 case GT_PCI1_SCS3BT_BAR:
521 case GT_PCI1_CFGADDR:
522 case GT_PCI1_CFGDATA:
523 /* not implemented */
525 case GT_PCI0_CFGADDR:
526 s->pci.config_reg = val & 0x80fffffc;
528 case GT_PCI0_CFGDATA:
529 if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800))
531 if (s->pci.config_reg & (1u << 31))
532 pci_data_write(s->pci.bus, s->pci.config_reg, val, 4);
537 /* not really implemented */
538 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
539 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
540 DPRINTF("INTRCAUSE %x\n", val);
543 s->regs[saddr] = val & 0x3c3ffffe;
544 DPRINTF("INTRMASK %x\n", val);
547 s->regs[saddr] = val & 0x03fffffe;
548 DPRINTF("ICMASK %x\n", val);
550 case GT_PCI0_SERR0MASK:
551 s->regs[saddr] = val & 0x0000003f;
552 DPRINTF("SERR0MASK %x\n", val);
555 /* Reserved when only PCI_0 is configured. */
560 case GT_PCI0_HICMASK:
561 case GT_PCI1_SERR1MASK:
562 /* not implemented */
565 /* SDRAM Parameters */
570 /* We don't simulate electrical parameters of the SDRAM.
571 Accept, but ignore the values. */
572 s->regs[saddr] = val;
576 DPRINTF ("Bad register offset 0x%x\n", (int)addr);
581 static uint32_t gt64120_readl (void *opaque,
582 target_phys_addr_t addr)
584 GT64120State *s = opaque;
588 saddr = (addr & 0xfff) >> 2;
591 /* CPU Configuration */
593 /* Only one GT64xxx is present on the CPU bus, return
595 val = s->regs[saddr];
598 /* CPU Error Report */
599 case GT_CPUERR_ADDRLO:
600 case GT_CPUERR_ADDRHI:
601 case GT_CPUERR_DATALO:
602 case GT_CPUERR_DATAHI:
603 case GT_CPUERR_PARITY:
604 /* Emulated memory has no error, always return the initial
606 val = s->regs[saddr];
609 /* CPU Sync Barrier */
612 /* Reading those register should empty all FIFO on the PCI
613 bus, which are not emulated. The return value should be
614 a random value that should be ignored. */
619 case GT_ECC_ERRDATALO:
620 case GT_ECC_ERRDATAHI:
624 /* Emulated memory has no error, always return the initial
626 val = s->regs[saddr];
661 val = s->regs[saddr];
664 /* Read the IRQ number */
665 val = pic_read_irq(isa_pic);
668 /* SDRAM and Device Address Decode */
688 val = s->regs[saddr];
691 /* SDRAM Configuration */
693 case GT_SDRAM_OPMODE:
695 case GT_SDRAM_ADDRDECODE:
696 val = s->regs[saddr];
699 /* SDRAM Parameters */
704 /* We don't simulate electrical parameters of the SDRAM.
705 Just return the last written value. */
706 val = s->regs[saddr];
709 /* Device Parameters */
715 val = s->regs[saddr];
739 val = s->regs[saddr];
742 /* DMA Channel Control */
747 val = s->regs[saddr];
752 val = s->regs[saddr];
761 val = s->regs[saddr];
765 case GT_PCI0_CFGADDR:
766 val = s->pci.config_reg;
768 case GT_PCI0_CFGDATA:
769 if (!(s->pci.config_reg & (1 << 31)))
772 val = pci_data_read(s->pci.bus, s->pci.config_reg, 4);
773 if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci.config_reg & 0x00fff800))
779 case GT_PCI0_BS_SCS10:
780 case GT_PCI0_BS_SCS32:
781 case GT_PCI0_BS_CS20:
782 case GT_PCI0_BS_CS3BT:
785 case GT_PCI0_PREFMBR:
786 case GT_PCI0_SCS10_BAR:
787 case GT_PCI0_SCS32_BAR:
788 case GT_PCI0_CS20_BAR:
789 case GT_PCI0_CS3BT_BAR:
790 case GT_PCI0_SSCS10_BAR:
791 case GT_PCI0_SSCS32_BAR:
792 case GT_PCI0_SCS3BT_BAR:
795 case GT_PCI1_BS_SCS10:
796 case GT_PCI1_BS_SCS32:
797 case GT_PCI1_BS_CS20:
798 case GT_PCI1_BS_CS3BT:
800 case GT_PCI1_PREFMBR:
801 case GT_PCI1_SCS10_BAR:
802 case GT_PCI1_SCS32_BAR:
803 case GT_PCI1_CS20_BAR:
804 case GT_PCI1_CS3BT_BAR:
805 case GT_PCI1_SSCS10_BAR:
806 case GT_PCI1_SSCS32_BAR:
807 case GT_PCI1_SCS3BT_BAR:
808 case GT_PCI1_CFGADDR:
809 case GT_PCI1_CFGDATA:
810 val = s->regs[saddr];
815 val = s->regs[saddr];
816 DPRINTF("INTRCAUSE %x\n", val);
819 val = s->regs[saddr];
820 DPRINTF("INTRMASK %x\n", val);
823 val = s->regs[saddr];
824 DPRINTF("ICMASK %x\n", val);
826 case GT_PCI0_SERR0MASK:
827 val = s->regs[saddr];
828 DPRINTF("SERR0MASK %x\n", val);
831 /* Reserved when only PCI_0 is configured. */
836 case GT_PCI0_HICMASK:
837 case GT_PCI1_SERR1MASK:
838 val = s->regs[saddr];
842 val = s->regs[saddr];
843 DPRINTF ("Bad register offset 0x%x\n", (int)addr);
847 if (!(s->regs[GT_CPU] & 0x00001000))
853 static CPUWriteMemoryFunc * const gt64120_write[] = {
859 static CPUReadMemoryFunc * const gt64120_read[] = {
865 static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
869 slot = (pci_dev->devfn >> 3);
875 /* AMD 79C973 Ethernet */
878 /* Crystal 4281 Sound */
881 /* PCI slot 1 to 4 */
883 return ((slot - 18) + irq_num) & 0x03;
884 /* Unknown device, don't do any translation */
890 static int pci_irq_levels[4];
892 static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
894 int i, pic_irq, pic_level;
895 qemu_irq *pic = opaque;
897 pci_irq_levels[irq_num] = level;
899 /* now we change the pic irq level according to the piix irq mappings */
901 pic_irq = piix4_dev->config[0x60 + irq_num];
903 /* The pic level is the logical OR of all the PCI irqs mapped
906 for (i = 0; i < 4; i++) {
907 if (pic_irq == piix4_dev->config[0x60 + i])
908 pic_level |= pci_irq_levels[i];
910 qemu_set_irq(pic[pic_irq], pic_level);
915 static void gt64120_reset(void *opaque)
917 GT64120State *s = opaque;
919 /* FIXME: Malta specific hw assumptions ahead */
921 /* CPU Configuration */
922 #ifdef TARGET_WORDS_BIGENDIAN
923 s->regs[GT_CPU] = 0x00000000;
925 s->regs[GT_CPU] = 0x00001000;
927 s->regs[GT_MULTI] = 0x00000003;
929 /* CPU Address decode */
930 s->regs[GT_SCS10LD] = 0x00000000;
931 s->regs[GT_SCS10HD] = 0x00000007;
932 s->regs[GT_SCS32LD] = 0x00000008;
933 s->regs[GT_SCS32HD] = 0x0000000f;
934 s->regs[GT_CS20LD] = 0x000000e0;
935 s->regs[GT_CS20HD] = 0x00000070;
936 s->regs[GT_CS3BOOTLD] = 0x000000f8;
937 s->regs[GT_CS3BOOTHD] = 0x0000007f;
939 s->regs[GT_PCI0IOLD] = 0x00000080;
940 s->regs[GT_PCI0IOHD] = 0x0000000f;
941 s->regs[GT_PCI0M0LD] = 0x00000090;
942 s->regs[GT_PCI0M0HD] = 0x0000001f;
943 s->regs[GT_ISD] = 0x000000a0;
944 s->regs[GT_PCI0M1LD] = 0x00000790;
945 s->regs[GT_PCI0M1HD] = 0x0000001f;
946 s->regs[GT_PCI1IOLD] = 0x00000100;
947 s->regs[GT_PCI1IOHD] = 0x0000000f;
948 s->regs[GT_PCI1M0LD] = 0x00000110;
949 s->regs[GT_PCI1M0HD] = 0x0000001f;
950 s->regs[GT_PCI1M1LD] = 0x00000120;
951 s->regs[GT_PCI1M1HD] = 0x0000002f;
953 s->regs[GT_SCS10AR] = 0x00000000;
954 s->regs[GT_SCS32AR] = 0x00000008;
955 s->regs[GT_CS20R] = 0x000000e0;
956 s->regs[GT_CS3BOOTR] = 0x000000f8;
958 s->regs[GT_PCI0IOREMAP] = 0x00000080;
959 s->regs[GT_PCI0M0REMAP] = 0x00000090;
960 s->regs[GT_PCI0M1REMAP] = 0x00000790;
961 s->regs[GT_PCI1IOREMAP] = 0x00000100;
962 s->regs[GT_PCI1M0REMAP] = 0x00000110;
963 s->regs[GT_PCI1M1REMAP] = 0x00000120;
965 /* CPU Error Report */
966 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
967 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
968 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
969 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
970 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
972 /* CPU Sync Barrier */
973 s->regs[GT_PCI0SYNC] = 0x00000000;
974 s->regs[GT_PCI1SYNC] = 0x00000000;
976 /* SDRAM and Device Address Decode */
977 s->regs[GT_SCS0LD] = 0x00000000;
978 s->regs[GT_SCS0HD] = 0x00000007;
979 s->regs[GT_SCS1LD] = 0x00000008;
980 s->regs[GT_SCS1HD] = 0x0000000f;
981 s->regs[GT_SCS2LD] = 0x00000010;
982 s->regs[GT_SCS2HD] = 0x00000017;
983 s->regs[GT_SCS3LD] = 0x00000018;
984 s->regs[GT_SCS3HD] = 0x0000001f;
985 s->regs[GT_CS0LD] = 0x000000c0;
986 s->regs[GT_CS0HD] = 0x000000c7;
987 s->regs[GT_CS1LD] = 0x000000c8;
988 s->regs[GT_CS1HD] = 0x000000cf;
989 s->regs[GT_CS2LD] = 0x000000d0;
990 s->regs[GT_CS2HD] = 0x000000df;
991 s->regs[GT_CS3LD] = 0x000000f0;
992 s->regs[GT_CS3HD] = 0x000000fb;
993 s->regs[GT_BOOTLD] = 0x000000fc;
994 s->regs[GT_BOOTHD] = 0x000000ff;
995 s->regs[GT_ADERR] = 0xffffffff;
997 /* SDRAM Configuration */
998 s->regs[GT_SDRAM_CFG] = 0x00000200;
999 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1000 s->regs[GT_SDRAM_BM] = 0x00000007;
1001 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1003 /* SDRAM Parameters */
1004 s->regs[GT_SDRAM_B0] = 0x00000005;
1005 s->regs[GT_SDRAM_B1] = 0x00000005;
1006 s->regs[GT_SDRAM_B2] = 0x00000005;
1007 s->regs[GT_SDRAM_B3] = 0x00000005;
1010 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1011 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1012 s->regs[GT_ECC_MEM] = 0x00000000;
1013 s->regs[GT_ECC_CALC] = 0x00000000;
1014 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1016 /* Device Parameters */
1017 s->regs[GT_DEV_B0] = 0x386fffff;
1018 s->regs[GT_DEV_B1] = 0x386fffff;
1019 s->regs[GT_DEV_B2] = 0x386fffff;
1020 s->regs[GT_DEV_B3] = 0x386fffff;
1021 s->regs[GT_DEV_BOOT] = 0x146fffff;
1023 /* DMA registers are all zeroed at reset */
1026 s->regs[GT_TC0] = 0xffffffff;
1027 s->regs[GT_TC1] = 0x00ffffff;
1028 s->regs[GT_TC2] = 0x00ffffff;
1029 s->regs[GT_TC3] = 0x00ffffff;
1030 s->regs[GT_TC_CONTROL] = 0x00000000;
1033 #ifdef TARGET_WORDS_BIGENDIAN
1034 s->regs[GT_PCI0_CMD] = 0x00000000;
1036 s->regs[GT_PCI0_CMD] = 0x00010001;
1038 s->regs[GT_PCI0_TOR] = 0x0000070f;
1039 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1040 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1041 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1042 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1043 s->regs[GT_PCI1_IACK] = 0x00000000;
1044 s->regs[GT_PCI0_IACK] = 0x00000000;
1045 s->regs[GT_PCI0_BARE] = 0x0000000f;
1046 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1047 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1048 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1049 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1050 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1051 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1052 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1053 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1054 #ifdef TARGET_WORDS_BIGENDIAN
1055 s->regs[GT_PCI1_CMD] = 0x00000000;
1057 s->regs[GT_PCI1_CMD] = 0x00010001;
1059 s->regs[GT_PCI1_TOR] = 0x0000070f;
1060 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1061 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1062 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1063 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1064 s->regs[GT_PCI1_BARE] = 0x0000000f;
1065 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1066 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1067 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1068 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1069 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1070 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1071 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1072 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1073 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1074 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1075 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1077 /* Interrupt registers are all zeroed at reset */
1079 gt64120_isd_mapping(s);
1080 gt64120_pci_mapping(s);
1083 PCIBus *gt64120_register(qemu_irq *pic)
1089 dev = qdev_create(NULL, "gt64120");
1090 qdev_init_nofail(dev);
1091 s = sysbus_from_qdev(dev);
1092 d = FROM_SYSBUS(GT64120State, s);
1093 d->pci.bus = pci_register_bus(&d->busdev.qdev, "pci",
1094 gt64120_pci_set_irq, gt64120_pci_map_irq,
1095 pic, PCI_DEVFN(18, 0), 4);
1096 d->ISD_handle = cpu_register_io_memory(gt64120_read, gt64120_write, d,
1097 DEVICE_NATIVE_ENDIAN);
1099 pci_create_simple(d->pci.bus, PCI_DEVFN(0, 0), "gt64120_pci");
1103 static int gt64120_init(SysBusDevice *dev)
1107 s = FROM_SYSBUS(GT64120State, dev);
1109 /* FIXME: This value is computed from registers during reset, but some
1110 devices (e.g. VGA card) need to know it when they are registered.
1111 This also mean that changing the register to change the mapping
1112 does not fully work. */
1113 isa_mem_base = 0x10000000;
1114 qemu_register_reset(gt64120_reset, s);
1118 static int gt64120_pci_init(PCIDevice *d)
1120 /* FIXME: Malta specific hw assumptions ahead */
1121 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MARVELL);
1122 pci_config_set_device_id(d->config, PCI_DEVICE_ID_MARVELL_GT6412X);
1123 pci_set_word(d->config + PCI_COMMAND, 0);
1124 pci_set_word(d->config + PCI_STATUS,
1125 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1126 pci_set_byte(d->config + PCI_CLASS_REVISION, 0x10);
1127 pci_config_set_prog_interface(d->config, 0);
1128 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
1129 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1130 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1131 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1132 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1133 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1134 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1135 pci_set_byte(d->config + 0x3d, 0x01);
1140 static PCIDeviceInfo gt64120_pci_info = {
1141 .qdev.name = "gt64120_pci",
1142 .qdev.size = sizeof(PCIDevice),
1143 .init = gt64120_pci_init,
1146 static void gt64120_pci_register_devices(void)
1148 sysbus_register_dev("gt64120", sizeof(GT64120State),
1150 pci_qdev_register(>64120_pci_info);
1153 device_init(gt64120_pci_register_devices)