2 * QEMU i8255x (PRO100) emulation
4 * Copyright (C) 2006-2010 Stefan Weil
6 * Portions of the code are copies from grub / etherboot eepro100.c
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 * Tested features (i82559):
24 * Linux networking (i386) ok
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
36 * * PHY emulation should be separated from nic emulation.
37 * Most nic emulations could share the same phy code.
38 * * i82550 is untested. It is programmed like the i82559.
39 * * i82562 is untested. It is programmed like the i82559.
40 * * Power management (i82558 and later) is not implemented.
41 * * Wake-on-LAN is not implemented.
44 #include <stddef.h> /* offsetof */
48 #include "eeprom93xx.h"
52 /* Debug EEPRO100 card. */
54 # define DEBUG_EEPRO100
58 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
60 #define logout(fmt, ...) ((void)0)
63 /* Set flags to 0 to disable debug output. */
64 #define INT 1 /* interrupt related actions */
65 #define MDI 1 /* mdi related actions */
68 #define EEPROM 1 /* eeprom related actions */
70 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
72 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
74 #define MAX_ETH_FRAME_SIZE 1514
76 /* This driver supports several different devices which are declared here. */
77 #define i82550 0x82550
78 #define i82551 0x82551
79 #define i82557A 0x82557a
80 #define i82557B 0x82557b
81 #define i82557C 0x82557c
82 #define i82558A 0x82558a
83 #define i82558B 0x82558b
84 #define i82559A 0x82559a
85 #define i82559B 0x82559b
86 #define i82559C 0x82559c
87 #define i82559ER 0x82559e
88 #define i82562 0x82562
89 #define i82801 0x82801
91 /* Use 64 word EEPROM. TODO: could be a runtime option. */
92 #define EEPROM_SIZE 64
94 #define PCI_MEM_SIZE (4 * KiB)
95 #define PCI_IO_SIZE 64
96 #define PCI_FLASH_SIZE (128 * KiB)
98 #define BIT(n) (1 << (n))
99 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
101 /* The SCB accepts the following controls for the Tx and Rx units: */
102 #define CU_NOP 0x0000 /* No operation. */
103 #define CU_START 0x0010 /* CU start. */
104 #define CU_RESUME 0x0020 /* CU resume. */
105 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
106 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
107 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
108 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
109 #define CU_SRESUME 0x00a0 /* CU static resume. */
111 #define RU_NOP 0x0000
112 #define RX_START 0x0001
113 #define RX_RESUME 0x0002
114 #define RU_ABORT 0x0004
115 #define RX_ADDR_LOAD 0x0006
116 #define RX_RESUMENR 0x0007
117 #define INT_MASK 0x0100
118 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
126 bool has_extended_tcb_support;
127 bool power_management;
130 /* Offsets to the various registers.
131 All accesses need not be longword aligned. */
132 enum speedo_offsets {
133 SCBStatus = 0, /* Status Word. */
135 SCBCmd = 2, /* Rx/Command Unit command and status. */
137 SCBPointer = 4, /* General purpose pointer. */
138 SCBPort = 8, /* Misc. commands and operands. */
139 SCBflash = 12, /* Flash memory control. */
140 SCBeeprom = 14, /* EEPROM control. */
141 SCBCtrlMDI = 16, /* MDI interface control. */
142 SCBEarlyRx = 20, /* Early receive byte count. */
143 SCBFlow = 24, /* Flow Control. */
144 SCBpmdr = 27, /* Power Management Driver. */
145 SCBgctrl = 28, /* General Control. */
146 SCBgstat = 29, /* General Status. */
149 /* A speedo3 transmit buffer descriptor with two buffers... */
153 uint32_t link; /* void * */
154 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
155 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
156 uint8_t tx_threshold; /* transmit threshold */
157 uint8_t tbd_count; /* TBD number */
159 /* This constitutes two "TBD" entries: hdr and data */
160 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
161 int32_t tx_buf_size0; /* Length of Tx hdr. */
162 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
163 int32_t tx_buf_size1; /* Length of Tx data. */
167 /* Receive frame descriptor. */
171 uint32_t link; /* struct RxFD * */
172 uint32_t rx_buf_addr; /* void * */
175 char packet[MAX_ETH_FRAME_SIZE + 4];
179 COMMAND_EL = BIT(15),
184 COMMAND_CMD = BITS(2, 0),
193 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
194 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
195 tx_multiple_collisions, tx_total_collisions;
196 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
197 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
198 rx_short_frame_errors;
199 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
200 uint16_t xmt_tco_frames, rcv_tco_frames;
201 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
202 uint32_t reserved[4];
222 /* Hash register (multicast mask array, multiple individual addresses). */
227 uint8_t scb_stat; /* SCB stat/ack byte */
228 uint8_t int_stat; /* PCI interrupt status */
229 /* region must not be saved by nic_save. */
230 uint32_t region[3]; /* PCI region addresses */
233 uint32_t device; /* device variant */
235 /* (cu_base + cu_offset) address the next command block in the command block list. */
236 uint32_t cu_base; /* CU base address */
237 uint32_t cu_offset; /* CU address offset */
238 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
239 uint32_t ru_base; /* RU base address */
240 uint32_t ru_offset; /* RU address offset */
241 uint32_t statsaddr; /* pointer to eepro100_stats_t */
243 /* Temporary status information (no need to save these values),
244 * used while processing CU commands. */
245 eepro100_tx_t tx; /* transmit buffer descriptor */
246 uint32_t cb_address; /* = cu_base + cu_offset */
248 /* Statistical counters. Also used for wake-up packet (i82559). */
249 eepro100_stats_t statistics;
251 /* Configuration bytes. */
252 uint8_t configuration[22];
254 /* Data in mem is always in the byte order of the controller (le). */
255 uint8_t mem[PCI_MEM_SIZE];
256 /* vmstate for each particular nic */
257 VMStateDescription *vmstate;
259 /* Quasi static device properties (no need to save them). */
261 bool has_extended_tcb_support;
264 /* Word indices in EEPROM. */
266 EEPROM_CNFG_MDIX = 0x03,
268 EEPROM_PHY_ID = 0x06,
269 EEPROM_VENDOR_ID = 0x0c,
270 EEPROM_CONFIG_ASF = 0x0d,
271 EEPROM_DEVICE_ID = 0x23,
272 EEPROM_SMBUS_ADDR = 0x90,
275 /* Bit values for EEPROM ID word. */
277 EEPROM_ID_MDM = BIT(0), /* Modem */
278 EEPROM_ID_STB = BIT(1), /* Standby Enable */
279 EEPROM_ID_WMR = BIT(2), /* ??? */
280 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
281 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
282 EEPROM_ID_ALT = BIT(7), /* */
283 /* BITS(10, 8) device revision */
284 EEPROM_ID_BD = BIT(11), /* boot disable */
285 EEPROM_ID_ID = BIT(13), /* id bit */
286 /* BITS(15, 14) signature */
287 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
290 /* Default values for MDI (PHY) registers */
291 static const uint16_t eepro100_mdi_default[] = {
292 /* MDI Registers 0 - 6, 7 */
293 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
294 /* MDI Registers 8 - 15 */
295 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
296 /* MDI Registers 16 - 31 */
297 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
298 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
301 /* Readonly mask for MDI (PHY) registers */
302 static const uint16_t eepro100_mdi_mask[] = {
303 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
304 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
305 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
306 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
310 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
312 val = cpu_to_le32(val);
313 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
316 #define POLYNOMIAL 0x04c11db6
320 static unsigned compute_mcast_idx(const uint8_t * ep)
327 for (i = 0; i < 6; i++) {
329 for (j = 0; j < 8; j++) {
330 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
334 crc = ((crc ^ POLYNOMIAL) | carry);
338 return (crc & BITS(7, 2)) >> 2;
341 #if defined(DEBUG_EEPRO100)
342 static const char *nic_dump(const uint8_t * buf, unsigned size)
344 static char dump[3 * 16 + 1];
350 p += sprintf(p, " %02x", *buf++);
354 #endif /* DEBUG_EEPRO100 */
357 stat_ack_not_ours = 0x00,
358 stat_ack_sw_gen = 0x04,
360 stat_ack_cu_idle = 0x20,
361 stat_ack_frame_rx = 0x40,
362 stat_ack_cu_cmd_done = 0x80,
363 stat_ack_not_present = 0xFF,
364 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
365 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
368 static void disable_interrupt(EEPRO100State * s)
371 TRACE(INT, logout("interrupt disabled\n"));
372 qemu_irq_lower(s->dev.irq[0]);
377 static void enable_interrupt(EEPRO100State * s)
380 TRACE(INT, logout("interrupt enabled\n"));
381 qemu_irq_raise(s->dev.irq[0]);
386 static void eepro100_acknowledge(EEPRO100State * s)
388 s->scb_stat &= ~s->mem[SCBAck];
389 s->mem[SCBAck] = s->scb_stat;
390 if (s->scb_stat == 0) {
391 disable_interrupt(s);
395 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
397 uint8_t mask = ~s->mem[SCBIntmask];
398 s->mem[SCBAck] |= status;
399 status = s->scb_stat = s->mem[SCBAck];
400 status &= (mask | 0x0f);
402 status &= (~s->mem[SCBIntmask] | 0x0xf);
404 if (status && (mask & 0x01)) {
405 /* SCB mask and SCB Bit M do not disable interrupt. */
407 } else if (s->int_stat) {
408 disable_interrupt(s);
412 static void eepro100_cx_interrupt(EEPRO100State * s)
414 /* CU completed action command. */
415 /* Transmit not ok (82557 only, not in emulation). */
416 eepro100_interrupt(s, 0x80);
419 static void eepro100_cna_interrupt(EEPRO100State * s)
421 /* CU left the active state. */
422 eepro100_interrupt(s, 0x20);
425 static void eepro100_fr_interrupt(EEPRO100State * s)
427 /* RU received a complete frame. */
428 eepro100_interrupt(s, 0x40);
431 static void eepro100_rnr_interrupt(EEPRO100State * s)
433 /* RU is not ready. */
434 eepro100_interrupt(s, 0x10);
437 static void eepro100_mdi_interrupt(EEPRO100State * s)
439 /* MDI completed read or write cycle. */
440 eepro100_interrupt(s, 0x08);
443 static void eepro100_swi_interrupt(EEPRO100State * s)
445 /* Software has requested an interrupt. */
446 eepro100_interrupt(s, 0x04);
450 static void eepro100_fcp_interrupt(EEPRO100State * s)
452 /* Flow control pause interrupt (82558 and later). */
453 eepro100_interrupt(s, 0x01);
457 static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
459 uint32_t device = s->device;
460 uint8_t *pci_conf = s->dev.config;
462 TRACE(OTHER, logout("%p\n", s));
465 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
467 pci_config_set_device_id(pci_conf, e100_device->device_id);
469 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
470 PCI_STATUS_FAST_BACK);
471 /* PCI Revision ID */
472 pci_config_set_revision(pci_conf, e100_device->revision);
473 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
474 /* PCI Latency Timer */
475 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
476 /* Capability Pointer is set by PCI framework. */
479 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
481 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
482 /* Maximum Latency */
483 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
485 s->stats_size = e100_device->stats_size;
486 s->has_extended_tcb_support = e100_device->has_extended_tcb_support;
504 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL);
505 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
509 logout("Device %X is undefined!\n", device);
513 s->configuration[6] |= BIT(4);
515 /* Standard statistical counters. */
516 s->configuration[6] |= BIT(5);
518 if (s->stats_size == 80) {
519 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
520 if (s->configuration[6] & BIT(2)) {
521 /* TCO statistical counters. */
522 assert(s->configuration[6] & BIT(5));
524 if (s->configuration[6] & BIT(5)) {
525 /* No extended statistical counters, i82557 compatible. */
528 /* i82558 compatible. */
533 if (s->configuration[6] & BIT(5)) {
534 /* No extended statistical counters. */
538 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
540 if (e100_device->power_management) {
541 /* Power Management Capabilities */
542 int cfg_offset = 0xdc;
543 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
544 cfg_offset, PCI_PM_SIZEOF);
546 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
547 #if 0 /* TODO: replace dummy code for power management emulation. */
548 /* TODO: Power Management Control / Status. */
549 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
550 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
551 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
556 if (device == i82557C || device == i82558B || device == i82559C) {
558 TODO: get vendor id from EEPROM for i82557C or later.
559 TODO: get device id from EEPROM for i82557C or later.
560 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
561 TODO: header type is determined by EEPROM for i82559.
562 TODO: get subsystem id from EEPROM for i82557C or later.
563 TODO: get subsystem vendor id from EEPROM for i82557C or later.
564 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
565 TODO: capability pointer depends on EEPROM for i82558.
567 logout("Get device id and revision from EEPROM!!!\n");
569 #endif /* EEPROM_SIZE > 0 */
572 static void nic_selective_reset(EEPRO100State * s)
575 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
577 eeprom93xx_reset(s->eeprom);
579 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
580 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
581 if (s->device == i82557B || s->device == i82557C)
582 eeprom_contents[5] = 0x0100;
583 eeprom_contents[EEPROM_PHY_ID] = 1;
585 for (i = 0; i < EEPROM_SIZE - 1; i++) {
586 sum += eeprom_contents[i];
588 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
589 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
591 memset(s->mem, 0, sizeof(s->mem));
592 uint32_t val = BIT(21);
593 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
595 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
596 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
599 static void nic_reset(void *opaque)
601 EEPRO100State *s = opaque;
602 TRACE(OTHER, logout("%p\n", s));
603 /* TODO: Clearing of hash register for selective reset, too? */
604 memset(&s->mult[0], 0, sizeof(s->mult));
605 nic_selective_reset(s);
608 #if defined(DEBUG_EEPRO100)
609 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
613 "EEPROM/Flash Control",
615 "Receive DMA Byte Count",
617 "General Status/Control"
620 static char *regname(uint32_t addr)
623 if (addr < PCI_IO_SIZE) {
624 const char *r = e100_reg[addr / 4];
626 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
628 snprintf(buf, sizeof(buf), "0x%02x", addr);
631 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
635 #endif /* DEBUG_EEPRO100 */
637 /*****************************************************************************
641 ****************************************************************************/
644 static uint16_t eepro100_read_command(EEPRO100State * s)
646 uint16_t val = 0xffff;
647 TRACE(OTHER, logout("val=0x%04x\n", val));
652 /* Commands that can be put in a command list entry. */
657 CmdMulticastList = 3,
659 CmdTDR = 5, /* load microcode */
663 /* And some extra flags: */
664 CmdSuspend = 0x4000, /* Suspend after completion. */
665 CmdIntr = 0x2000, /* Interrupt after completion. */
666 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
669 static cu_state_t get_cu_state(EEPRO100State * s)
671 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
674 static void set_cu_state(EEPRO100State * s, cu_state_t state)
676 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
679 static ru_state_t get_ru_state(EEPRO100State * s)
681 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
684 static void set_ru_state(EEPRO100State * s, ru_state_t state)
686 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
689 static void dump_statistics(EEPRO100State * s)
691 /* Dump statistical data. Most data is never changed by the emulation
692 * and always 0, so we first just copy the whole block and then those
693 * values which really matter.
694 * Number of data should check configuration!!!
696 cpu_physical_memory_write(s->statsaddr,
697 (uint8_t *) & s->statistics, s->stats_size);
698 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
699 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
700 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
701 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
703 stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
704 stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
705 missing("CU dump statistical counters");
709 static void read_cb(EEPRO100State *s)
711 cpu_physical_memory_read(s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx));
712 s->tx.status = le16_to_cpu(s->tx.status);
713 s->tx.command = le16_to_cpu(s->tx.command);
714 s->tx.link = le32_to_cpu(s->tx.link);
715 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
716 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
719 static void tx_command(EEPRO100State *s)
721 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
722 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
723 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
726 uint32_t tbd_address = s->cb_address + 0x10;
728 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
729 tbd_array, tcb_bytes, s->tx.tbd_count));
731 if (tcb_bytes > 2600) {
732 logout("TCB byte count too large, using 2600\n");
735 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
737 ("illegal values of TBD array address and TCB byte count!\n");
739 assert(tcb_bytes <= sizeof(buf));
740 while (size < tcb_bytes) {
741 uint32_t tx_buffer_address = ldl_phys(tbd_address);
742 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
744 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
748 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
749 tx_buffer_address, tx_buffer_size));
750 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
751 cpu_physical_memory_read(tx_buffer_address, &buf[size],
753 size += tx_buffer_size;
755 if (tbd_array == 0xffffffff) {
756 /* Simplified mode. Was already handled by code above. */
759 uint8_t tbd_count = 0;
760 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
761 /* Extended Flexible TCB. */
762 for (; tbd_count < 2; tbd_count++) {
763 uint32_t tx_buffer_address = ldl_phys(tbd_address);
764 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
765 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
768 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
769 tx_buffer_address, tx_buffer_size));
770 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
771 cpu_physical_memory_read(tx_buffer_address, &buf[size],
773 size += tx_buffer_size;
774 if (tx_buffer_el & 1) {
779 tbd_address = tbd_array;
780 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
781 uint32_t tx_buffer_address = ldl_phys(tbd_address);
782 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
783 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
786 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
787 tx_buffer_address, tx_buffer_size));
788 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
789 cpu_physical_memory_read(tx_buffer_address, &buf[size],
791 size += tx_buffer_size;
792 if (tx_buffer_el & 1) {
797 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
798 qemu_send_packet(&s->nic->nc, buf, size);
799 s->statistics.tx_good_frames++;
800 /* Transmit with bad status would raise an CX/TNO interrupt.
801 * (82557 only). Emulation never has bad status. */
803 eepro100_cx_interrupt(s);
807 static void set_multicast_list(EEPRO100State *s)
809 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
811 memset(&s->mult[0], 0, sizeof(s->mult));
812 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
813 for (i = 0; i < multicast_count; i += 6) {
814 uint8_t multicast_addr[6];
815 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
816 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
817 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
818 assert(mcast_idx < 64);
819 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
823 static void action_command(EEPRO100State *s)
830 uint16_t ok_status = STATUS_OK;
831 s->cb_address = s->cu_base + s->cu_offset;
833 bit_el = ((s->tx.command & COMMAND_EL) != 0);
834 bit_s = ((s->tx.command & COMMAND_S) != 0);
835 bit_i = ((s->tx.command & COMMAND_I) != 0);
836 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
838 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
840 s->cu_offset = s->tx.link;
842 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
843 s->tx.status, s->tx.command, s->tx.link));
844 switch (s->tx.command & COMMAND_CMD) {
849 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
850 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
853 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
854 sizeof(s->configuration));
855 TRACE(OTHER, logout("configuration: %s\n",
856 nic_dump(&s->configuration[0], 16)));
857 TRACE(OTHER, logout("configuration: %s\n",
858 nic_dump(&s->configuration[16],
859 ARRAY_SIZE(s->configuration) - 16)));
860 if (s->configuration[20] & BIT(6)) {
861 TRACE(OTHER, logout("Multiple IA bit\n"));
864 case CmdMulticastList:
865 set_multicast_list(s);
869 missing("CmdTx: NC = 0");
876 TRACE(OTHER, logout("load microcode\n"));
877 /* Starting with offset 8, the command contains
878 * 64 dwords microcode which we just ignore here. */
881 TRACE(OTHER, logout("diagnose\n"));
882 /* Make sure error flag is not set. */
886 missing("undefined command");
890 /* Write new status. */
891 stw_phys(s->cb_address, s->tx.status | ok_status | STATUS_C);
893 /* CU completed action. */
894 eepro100_cx_interrupt(s);
897 /* CU becomes idle. Terminate command loop. */
898 set_cu_state(s, cu_idle);
899 eepro100_cna_interrupt(s);
902 /* CU becomes suspended. Terminate command loop. */
903 set_cu_state(s, cu_suspended);
904 eepro100_cna_interrupt(s);
907 /* More entries in list. */
908 TRACE(OTHER, logout("CU list with at least one more entry\n"));
911 TRACE(OTHER, logout("CU list empty\n"));
912 /* List is empty. Now CU is idle or suspended. */
915 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
923 cu_state = get_cu_state(s);
924 if (cu_state != cu_idle && cu_state != cu_suspended) {
925 /* Intel documentation says that CU must be idle or suspended
926 * for the CU start command. */
927 logout("unexpected CU state is %u\n", cu_state);
929 set_cu_state(s, cu_active);
930 s->cu_offset = s->pointer;
934 if (get_cu_state(s) != cu_suspended) {
935 logout("bad CU resume from CU state %u\n", get_cu_state(s));
936 /* Workaround for bad Linux eepro100 driver which resumes
937 * from idle state. */
939 missing("cu resume");
941 set_cu_state(s, cu_suspended);
943 if (get_cu_state(s) == cu_suspended) {
944 TRACE(OTHER, logout("CU resuming\n"));
945 set_cu_state(s, cu_active);
950 /* Load dump counters address. */
951 s->statsaddr = s->pointer;
952 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
955 /* Dump statistical counters. */
956 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
958 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
962 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
963 s->cu_base = s->pointer;
966 /* Dump and reset statistical counters. */
967 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
969 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
970 memset(&s->statistics, 0, sizeof(s->statistics));
973 /* CU static resume. */
974 missing("CU static resume");
977 missing("Undefined CU command");
981 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
989 if (get_ru_state(s) != ru_idle) {
990 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
992 assert(!"wrong RU state");
995 set_ru_state(s, ru_ready);
996 s->ru_offset = s->pointer;
997 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1001 if (get_ru_state(s) != ru_suspended) {
1002 logout("RU state is %u, should be %u\n", get_ru_state(s),
1005 assert(!"wrong RU state");
1008 set_ru_state(s, ru_ready);
1012 if (get_ru_state(s) == ru_ready) {
1013 eepro100_rnr_interrupt(s);
1015 set_ru_state(s, ru_idle);
1019 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1020 s->ru_base = s->pointer;
1023 logout("val=0x%02x (undefined RU command)\n", val);
1024 missing("Undefined SU command");
1028 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1030 eepro100_ru_command(s, val & 0x0f);
1031 eepro100_cu_command(s, val & 0xf0);
1033 TRACE(OTHER, logout("val=0x%02x\n", val));
1035 /* Clear command byte after command was accepted. */
1039 /*****************************************************************************
1043 ****************************************************************************/
1045 #define EEPROM_CS 0x02
1046 #define EEPROM_SK 0x01
1047 #define EEPROM_DI 0x04
1048 #define EEPROM_DO 0x08
1050 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1053 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1054 if (eeprom93xx_read(s->eeprom)) {
1059 TRACE(EEPROM, logout("val=0x%04x\n", val));
1063 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1065 TRACE(EEPROM, logout("val=0x%02x\n", val));
1067 /* mask unwriteable bits */
1069 val = SET_MASKED(val, 0x31, eeprom->value);
1072 int eecs = ((val & EEPROM_CS) != 0);
1073 int eesk = ((val & EEPROM_SK) != 0);
1074 int eedi = ((val & EEPROM_DI) != 0);
1075 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1078 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1080 s->pointer = le32_to_cpu(val);
1081 TRACE(OTHER, logout("val=0x%08x\n", val));
1084 /*****************************************************************************
1088 ****************************************************************************/
1090 #if defined(DEBUG_EEPRO100)
1091 static const char * const mdi_op_name[] = {
1098 static const char * const mdi_reg_name[] = {
1101 "PHY Identification (Word 1)",
1102 "PHY Identification (Word 2)",
1103 "Auto-Negotiation Advertisement",
1104 "Auto-Negotiation Link Partner Ability",
1105 "Auto-Negotiation Expansion"
1108 static const char *reg2name(uint8_t reg)
1110 static char buffer[10];
1111 const char *p = buffer;
1112 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1113 p = mdi_reg_name[reg];
1115 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1119 #endif /* DEBUG_EEPRO100 */
1121 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1124 memcpy(&val, &s->mem[0x10], sizeof(val));
1126 #ifdef DEBUG_EEPRO100
1127 uint8_t raiseint = (val & BIT(29)) >> 29;
1128 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1129 uint8_t phy = (val & BITS(25, 21)) >> 21;
1130 uint8_t reg = (val & BITS(20, 16)) >> 16;
1131 uint16_t data = (val & BITS(15, 0));
1133 /* Emulation takes no time to finish MDI transaction. */
1135 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1136 val, raiseint, mdi_op_name[opcode], phy,
1137 reg2name(reg), data));
1141 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1143 uint8_t raiseint = (val & BIT(29)) >> 29;
1144 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1145 uint8_t phy = (val & BITS(25, 21)) >> 21;
1146 uint8_t reg = (val & BITS(20, 16)) >> 16;
1147 uint16_t data = (val & BITS(15, 0));
1148 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1149 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1151 /* Unsupported PHY address. */
1153 logout("phy must be 1 but is %u\n", phy);
1156 } else if (opcode != 1 && opcode != 2) {
1157 /* Unsupported opcode. */
1158 logout("opcode must be 1 or 2 but is %u\n", opcode);
1160 } else if (reg > 6) {
1161 /* Unsupported register. */
1162 logout("register must be 0...6 but is %u\n", reg);
1165 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1166 val, raiseint, mdi_op_name[opcode], phy,
1167 reg2name(reg), data));
1171 case 0: /* Control Register */
1172 if (data & 0x8000) {
1173 /* Reset status and control registers to default. */
1174 s->mdimem[0] = eepro100_mdi_default[0];
1175 s->mdimem[1] = eepro100_mdi_default[1];
1176 data = s->mdimem[reg];
1178 /* Restart Auto Configuration = Normal Operation */
1182 case 1: /* Status Register */
1183 missing("not writable");
1184 data = s->mdimem[reg];
1186 case 2: /* PHY Identification Register (Word 1) */
1187 case 3: /* PHY Identification Register (Word 2) */
1188 missing("not implemented");
1190 case 4: /* Auto-Negotiation Advertisement Register */
1191 case 5: /* Auto-Negotiation Link Partner Ability Register */
1193 case 6: /* Auto-Negotiation Expansion Register */
1195 missing("not implemented");
1197 s->mdimem[reg] = data;
1198 } else if (opcode == 2) {
1201 case 0: /* Control Register */
1202 if (data & 0x8000) {
1203 /* Reset status and control registers to default. */
1204 s->mdimem[0] = eepro100_mdi_default[0];
1205 s->mdimem[1] = eepro100_mdi_default[1];
1208 case 1: /* Status Register */
1209 s->mdimem[reg] |= 0x0020;
1211 case 2: /* PHY Identification Register (Word 1) */
1212 case 3: /* PHY Identification Register (Word 2) */
1213 case 4: /* Auto-Negotiation Advertisement Register */
1215 case 5: /* Auto-Negotiation Link Partner Ability Register */
1216 s->mdimem[reg] = 0x41fe;
1218 case 6: /* Auto-Negotiation Expansion Register */
1219 s->mdimem[reg] = 0x0001;
1222 data = s->mdimem[reg];
1224 /* Emulation takes no time to finish MDI transaction.
1225 * Set MDI bit in SCB status register. */
1226 s->mem[SCBAck] |= 0x08;
1229 eepro100_mdi_interrupt(s);
1232 val = (val & 0xffff0000) + data;
1233 memcpy(&s->mem[0x10], &val, sizeof(val));
1236 /*****************************************************************************
1240 ****************************************************************************/
1242 #define PORT_SOFTWARE_RESET 0
1243 #define PORT_SELFTEST 1
1244 #define PORT_SELECTIVE_RESET 2
1246 #define PORT_SELECTION_MASK 3
1249 uint32_t st_sign; /* Self Test Signature */
1250 uint32_t st_result; /* Self Test Results */
1251 } eepro100_selftest_t;
1253 static uint32_t eepro100_read_port(EEPRO100State * s)
1258 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1260 val = le32_to_cpu(val);
1261 uint32_t address = (val & ~PORT_SELECTION_MASK);
1262 uint8_t selection = (val & PORT_SELECTION_MASK);
1263 switch (selection) {
1264 case PORT_SOFTWARE_RESET:
1268 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1269 eepro100_selftest_t data;
1270 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1271 data.st_sign = 0xffffffff;
1273 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1275 case PORT_SELECTIVE_RESET:
1276 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1277 nic_selective_reset(s);
1280 logout("val=0x%08x\n", val);
1281 missing("unknown port selection");
1285 /*****************************************************************************
1287 * General hardware emulation.
1289 ****************************************************************************/
1291 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1294 if (addr <= sizeof(s->mem) - sizeof(val)) {
1295 memcpy(&val, &s->mem[addr], sizeof(val));
1301 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1304 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1306 val = eepro100_read_command(s);
1310 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1313 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1316 val = eepro100_read_eeprom(s);
1318 case SCBpmdr: /* Power Management Driver Register */
1320 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1322 case SCBgstat: /* General Status Register */
1323 /* 100 Mbps full duplex, valid link */
1325 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1328 logout("addr=%s val=0x%02x\n", regname(addr), val);
1329 missing("unknown byte read");
1334 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1337 if (addr <= sizeof(s->mem) - sizeof(val)) {
1338 memcpy(&val, &s->mem[addr], sizeof(val));
1344 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1347 val = eepro100_read_eeprom(s);
1348 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1351 logout("addr=%s val=0x%04x\n", regname(addr), val);
1352 missing("unknown word read");
1357 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1360 if (addr <= sizeof(s->mem) - sizeof(val)) {
1361 memcpy(&val, &s->mem[addr], sizeof(val));
1366 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1370 val = eepro100_read_pointer(s);
1372 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1375 val = eepro100_read_port(s);
1376 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1379 val = eepro100_read_mdi(s);
1382 logout("addr=%s val=0x%08x\n", regname(addr), val);
1383 missing("unknown longword read");
1388 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1390 /* SCBStatus is readonly. */
1391 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1392 memcpy(&s->mem[addr], &val, sizeof(val));
1395 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1401 eepro100_acknowledge(s);
1404 eepro100_write_command(s, val);
1408 eepro100_swi_interrupt(s);
1410 eepro100_interrupt(s, 0);
1413 case SCBFlow: /* does not exist on 82557 */
1416 case SCBpmdr: /* does not exist on 82557 */
1417 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1420 eepro100_write_eeprom(s->eeprom, val);
1423 logout("addr=%s val=0x%02x\n", regname(addr), val);
1424 missing("unknown byte write");
1428 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1430 /* SCBStatus is readonly. */
1431 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1432 memcpy(&s->mem[addr], &val, sizeof(val));
1435 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1439 s->mem[SCBAck] = (val >> 8);
1440 eepro100_acknowledge(s);
1443 eepro100_write_command(s, val);
1444 eepro100_write1(s, SCBIntmask, val >> 8);
1447 eepro100_write_eeprom(s->eeprom, val);
1450 logout("addr=%s val=0x%04x\n", regname(addr), val);
1451 missing("unknown word write");
1455 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1457 if (addr <= sizeof(s->mem) - sizeof(val)) {
1458 memcpy(&s->mem[addr], &val, sizeof(val));
1463 eepro100_write_pointer(s, val);
1466 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1467 eepro100_write_port(s, val);
1470 eepro100_write_mdi(s, val);
1473 logout("addr=%s val=0x%08x\n", regname(addr), val);
1474 missing("unknown longword write");
1478 /*****************************************************************************
1482 ****************************************************************************/
1484 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1486 EEPRO100State *s = opaque;
1488 logout("addr=%s\n", regname(addr));
1490 return eepro100_read1(s, addr - s->region[1]);
1493 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1495 EEPRO100State *s = opaque;
1496 return eepro100_read2(s, addr - s->region[1]);
1499 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1501 EEPRO100State *s = opaque;
1502 return eepro100_read4(s, addr - s->region[1]);
1505 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1507 EEPRO100State *s = opaque;
1509 logout("addr=%s val=0x%02x\n", regname(addr), val);
1511 eepro100_write1(s, addr - s->region[1], val);
1514 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1516 EEPRO100State *s = opaque;
1517 eepro100_write2(s, addr - s->region[1], val);
1520 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1522 EEPRO100State *s = opaque;
1523 eepro100_write4(s, addr - s->region[1], val);
1526 /***********************************************************/
1527 /* PCI EEPRO100 definitions */
1529 static void pci_map(PCIDevice * pci_dev, int region_num,
1530 pcibus_t addr, pcibus_t size, int type)
1532 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1534 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1535 "size=0x%08"FMT_PCIBUS", type=%d\n",
1536 region_num, addr, size, type));
1538 assert(region_num == 1);
1539 register_ioport_write(addr, size, 1, ioport_write1, s);
1540 register_ioport_read(addr, size, 1, ioport_read1, s);
1541 register_ioport_write(addr, size, 2, ioport_write2, s);
1542 register_ioport_read(addr, size, 2, ioport_read2, s);
1543 register_ioport_write(addr, size, 4, ioport_write4, s);
1544 register_ioport_read(addr, size, 4, ioport_read4, s);
1546 s->region[region_num] = addr;
1549 /*****************************************************************************
1551 * Memory mapped I/O.
1553 ****************************************************************************/
1555 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1557 EEPRO100State *s = opaque;
1559 logout("addr=%s val=0x%02x\n", regname(addr), val);
1561 eepro100_write1(s, addr, val);
1564 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1566 EEPRO100State *s = opaque;
1568 logout("addr=%s val=0x%02x\n", regname(addr), val);
1570 eepro100_write2(s, addr, val);
1573 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1575 EEPRO100State *s = opaque;
1577 logout("addr=%s val=0x%02x\n", regname(addr), val);
1579 eepro100_write4(s, addr, val);
1582 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1584 EEPRO100State *s = opaque;
1586 logout("addr=%s\n", regname(addr));
1588 return eepro100_read1(s, addr);
1591 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1593 EEPRO100State *s = opaque;
1595 logout("addr=%s\n", regname(addr));
1597 return eepro100_read2(s, addr);
1600 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1602 EEPRO100State *s = opaque;
1604 logout("addr=%s\n", regname(addr));
1606 return eepro100_read4(s, addr);
1609 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1615 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1621 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1622 pcibus_t addr, pcibus_t size, int type)
1624 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1626 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1627 "size=0x%08"FMT_PCIBUS", type=%d\n",
1628 region_num, addr, size, type));
1630 assert(region_num == 0 || region_num == 2);
1632 /* Map control / status registers and flash. */
1633 cpu_register_physical_memory(addr, size, s->mmio_index);
1634 s->region[region_num] = addr;
1637 static int nic_can_receive(VLANClientState *nc)
1639 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1640 TRACE(RXTX, logout("%p\n", s));
1641 return get_ru_state(s) == ru_ready;
1643 return !eepro100_buffer_full(s);
1647 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1650 * - Magic packets should set bit 30 in power management driver register.
1651 * - Interesting packets should set bit 29 in power management driver register.
1653 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1654 uint16_t rfd_status = 0xa000;
1655 static const uint8_t broadcast_macaddr[6] =
1656 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1658 if (s->configuration[8] & 0x80) {
1659 /* CSMA is disabled. */
1660 logout("%p received while CSMA is disabled\n", s);
1662 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1663 /* Short frame and configuration byte 7/0 (discard short receive) set:
1664 * Short frame is discarded */
1665 logout("%p received short frame (%zu byte)\n", s, size);
1666 s->statistics.rx_short_frame_errors++;
1670 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1671 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1672 * Long frames are discarded. */
1673 logout("%p received long frame (%zu byte), ignored\n", s, size);
1675 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1676 /* Frame matches individual address. */
1677 /* TODO: check configuration byte 15/4 (ignore U/L). */
1678 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1679 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1680 /* Broadcast frame. */
1681 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1682 rfd_status |= 0x0002;
1683 } else if (buf[0] & 0x01) {
1684 /* Multicast frame. */
1685 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1686 if (s->configuration[21] & BIT(3)) {
1687 /* Multicast all bit is set, receive all multicast frames. */
1689 unsigned mcast_idx = compute_mcast_idx(buf);
1690 assert(mcast_idx < 64);
1691 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1692 /* Multicast frame is allowed in hash table. */
1693 } else if (s->configuration[15] & BIT(0)) {
1694 /* Promiscuous: receive all. */
1695 rfd_status |= 0x0004;
1697 TRACE(RXTX, logout("%p multicast ignored\n", s));
1701 /* TODO: Next not for promiscuous mode? */
1702 rfd_status |= 0x0002;
1703 } else if (s->configuration[15] & BIT(0)) {
1704 /* Promiscuous: receive all. */
1705 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1706 rfd_status |= 0x0004;
1707 } else if (s->configuration[20] & BIT(6)) {
1708 /* Multiple IA bit set. */
1709 unsigned mcast_idx = compute_mcast_idx(buf);
1710 assert(mcast_idx < 64);
1711 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1712 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1714 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1718 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1719 nic_dump(buf, size)));
1723 if (get_ru_state(s) != ru_ready) {
1724 /* No resources available. */
1725 logout("no resources, state=%u\n", get_ru_state(s));
1726 /* TODO: RNR interrupt only at first failed frame? */
1727 eepro100_rnr_interrupt(s);
1728 s->statistics.rx_resource_errors++;
1730 assert(!"no resources");
1736 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1737 offsetof(eepro100_rx_t, packet));
1738 uint16_t rfd_command = le16_to_cpu(rx.command);
1739 uint16_t rfd_size = le16_to_cpu(rx.size);
1741 if (size > rfd_size) {
1742 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1743 "(%zu bytes); data truncated\n", rfd_size, size);
1747 rfd_status |= 0x0080;
1749 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1750 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1751 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1753 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1754 /* Early receive interrupt not supported. */
1756 eepro100_er_interrupt(s);
1758 /* Receive CRC Transfer not supported. */
1759 if (s->configuration[18] & BIT(2)) {
1760 missing("Receive CRC Transfer");
1763 /* TODO: check stripping enable bit. */
1765 assert(!(s->configuration[17] & BIT(0)));
1767 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1768 offsetof(eepro100_rx_t, packet), buf, size);
1769 s->statistics.rx_good_frames++;
1770 eepro100_fr_interrupt(s);
1771 s->ru_offset = le32_to_cpu(rx.link);
1772 if (rfd_command & COMMAND_EL) {
1773 /* EL bit is set, so this was the last frame. */
1774 logout("receive: Running out of frames\n");
1775 set_ru_state(s, ru_suspended);
1777 if (rfd_command & COMMAND_S) {
1779 set_ru_state(s, ru_suspended);
1784 static const VMStateDescription vmstate_eepro100 = {
1786 .minimum_version_id = 2,
1787 .minimum_version_id_old = 2,
1788 .fields = (VMStateField []) {
1789 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1791 VMSTATE_BUFFER(mult, EEPRO100State),
1792 VMSTATE_BUFFER(mem, EEPRO100State),
1793 /* Save all members of struct between scb_stat and mem. */
1794 VMSTATE_UINT8(scb_stat, EEPRO100State),
1795 VMSTATE_UINT8(int_stat, EEPRO100State),
1796 VMSTATE_UNUSED(3*4),
1797 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1798 VMSTATE_UNUSED(19*4),
1799 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1800 /* The eeprom should be saved and restored by its own routines. */
1801 VMSTATE_UINT32(device, EEPRO100State),
1802 /* TODO check device. */
1803 VMSTATE_UINT32(pointer, EEPRO100State),
1804 VMSTATE_UINT32(cu_base, EEPRO100State),
1805 VMSTATE_UINT32(cu_offset, EEPRO100State),
1806 VMSTATE_UINT32(ru_base, EEPRO100State),
1807 VMSTATE_UINT32(ru_offset, EEPRO100State),
1808 VMSTATE_UINT32(statsaddr, EEPRO100State),
1809 /* Save eepro100_stats_t statistics. */
1810 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1811 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1812 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1813 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1814 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1815 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1816 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1817 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1818 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1819 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1820 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1821 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1822 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1823 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1824 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1825 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1826 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1827 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1828 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1829 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1830 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1831 /* Configuration bytes. */
1832 VMSTATE_BUFFER(configuration, EEPRO100State),
1833 VMSTATE_END_OF_LIST()
1837 static void nic_cleanup(VLANClientState *nc)
1839 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1844 static int pci_nic_uninit(PCIDevice *pci_dev)
1846 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1848 cpu_unregister_io_memory(s->mmio_index);
1849 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
1850 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
1851 qemu_del_vlan_client(&s->nic->nc);
1855 static NetClientInfo net_eepro100_info = {
1856 .type = NET_CLIENT_TYPE_NIC,
1857 .size = sizeof(NICState),
1858 .can_receive = nic_can_receive,
1859 .receive = nic_receive,
1860 .cleanup = nic_cleanup,
1863 static int e100_nic_init(PCIDevice *pci_dev)
1865 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1866 E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
1867 pci_dev->qdev.info);
1869 TRACE(OTHER, logout("\n"));
1871 s->device = e100_device->device;
1873 e100_pci_reset(s, e100_device);
1875 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1876 * i82559 and later support 64 or 256 word EEPROM. */
1877 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
1879 /* Handler for memory-mapped I/O */
1881 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1883 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1884 PCI_BASE_ADDRESS_SPACE_MEMORY |
1885 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1886 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1888 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1891 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1892 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1893 assert(s->region[1] == 0);
1897 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1898 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1900 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1901 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1903 qemu_register_reset(nic_reset, s);
1905 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1906 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1907 s->vmstate->name = s->nic->nc.model;
1908 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
1913 static E100PCIDeviceInfo e100_devices[] = {
1915 .pci.qdev.name = "i82550",
1916 .pci.qdev.desc = "Intel i82550 Ethernet",
1918 /* TODO: check device id. */
1919 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1920 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1922 /* TODO: check size of statistical counters. */
1924 /* TODO: check extended tcb support. */
1925 .has_extended_tcb_support = true,
1926 .power_management = true,
1928 .pci.qdev.name = "i82551",
1929 .pci.qdev.desc = "Intel i82551 Ethernet",
1931 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1932 /* Revision ID: 0x0f, 0x10. */
1934 /* TODO: check size of statistical counters. */
1936 .has_extended_tcb_support = true,
1937 .power_management = true,
1939 .pci.qdev.name = "i82557a",
1940 .pci.qdev.desc = "Intel i82557A Ethernet",
1942 .device_id = PCI_DEVICE_ID_INTEL_82557,
1944 .power_management = false,
1946 .pci.qdev.name = "i82557b",
1947 .pci.qdev.desc = "Intel i82557B Ethernet",
1949 .device_id = PCI_DEVICE_ID_INTEL_82557,
1951 .power_management = false,
1953 .pci.qdev.name = "i82557c",
1954 .pci.qdev.desc = "Intel i82557C Ethernet",
1956 .device_id = PCI_DEVICE_ID_INTEL_82557,
1958 .power_management = false,
1960 .pci.qdev.name = "i82558a",
1961 .pci.qdev.desc = "Intel i82558A Ethernet",
1963 .device_id = PCI_DEVICE_ID_INTEL_82557,
1966 .has_extended_tcb_support = true,
1967 .power_management = true,
1969 .pci.qdev.name = "i82558b",
1970 .pci.qdev.desc = "Intel i82558B Ethernet",
1972 .device_id = PCI_DEVICE_ID_INTEL_82557,
1975 .has_extended_tcb_support = true,
1976 .power_management = true,
1978 .pci.qdev.name = "i82559a",
1979 .pci.qdev.desc = "Intel i82559A Ethernet",
1981 .device_id = PCI_DEVICE_ID_INTEL_82557,
1984 .has_extended_tcb_support = true,
1985 .power_management = true,
1987 .pci.qdev.name = "i82559b",
1988 .pci.qdev.desc = "Intel i82559B Ethernet",
1990 .device_id = PCI_DEVICE_ID_INTEL_82557,
1993 .has_extended_tcb_support = true,
1994 .power_management = true,
1996 .pci.qdev.name = "i82559c",
1997 .pci.qdev.desc = "Intel i82559C Ethernet",
1999 .device_id = PCI_DEVICE_ID_INTEL_82557,
2003 /* TODO: Windows wants revision id 0x0c. */
2006 .has_extended_tcb_support = true,
2007 .power_management = true,
2009 .pci.qdev.name = "i82559er",
2010 .pci.qdev.desc = "Intel i82559ER Ethernet",
2012 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2015 .has_extended_tcb_support = true,
2016 .power_management = true,
2018 .pci.qdev.name = "i82562",
2019 .pci.qdev.desc = "Intel i82562 Ethernet",
2021 /* TODO: check device id. */
2022 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2023 /* TODO: wrong revision id. */
2026 .has_extended_tcb_support = true,
2027 .power_management = true,
2029 /* Toshiba Tecra 8200. */
2030 .pci.qdev.name = "i82801",
2031 .pci.qdev.desc = "Intel i82801 Ethernet",
2033 .device_id = 0x2449,
2036 .has_extended_tcb_support = true,
2037 .power_management = true,
2041 static Property e100_properties[] = {
2042 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2043 DEFINE_PROP_END_OF_LIST(),
2046 static void eepro100_register_devices(void)
2049 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2050 PCIDeviceInfo *pci_dev = &e100_devices[i].pci;
2051 switch (e100_devices[i].device_id) {
2052 case PCI_DEVICE_ID_INTEL_82551IT:
2053 pci_dev->romfile = "gpxe-eepro100-80861209.rom";
2055 case PCI_DEVICE_ID_INTEL_82557:
2056 pci_dev->romfile = "gpxe-eepro100-80861229.rom";
2059 pci_dev->romfile = "gpxe-eepro100-80862449.rom";
2062 pci_dev->init = e100_nic_init;
2063 pci_dev->exit = pci_nic_uninit;
2064 pci_dev->qdev.props = e100_properties;
2065 pci_dev->qdev.size = sizeof(EEPRO100State);
2066 pci_qdev_register(pci_dev);
2070 device_init(eepro100_register_devices)