hw/acpi/piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "qemu/osdep.h"
  22 #include "hw/hw.h"
  23 #include "hw/i386/pc.h"
  24 #include "hw/isa/apm.h"
  25 #include "hw/i2c/pm_smbus.h"
  26 #include "hw/pci/pci.h"
  27 #include "hw/acpi/acpi.h"
  28 #include "sysemu/sysemu.h"
  29 #include "qapi/error.h"
  30 #include "qemu/range.h"
  31 #include "exec/ioport.h"
  32 #include "hw/nvram/fw_cfg.h"
  33 #include "exec/address-spaces.h"
  34 #include "hw/acpi/piix4.h"
  35 #include "hw/acpi/pcihp.h"
  36 #include "hw/acpi/cpu_hotplug.h"
  37 #include "hw/acpi/cpu.h"
  38 #include "hw/hotplug.h"
  39 #include "hw/mem/pc-dimm.h"
  40 #include "hw/acpi/memory_hotplug.h"
  41 #include "hw/acpi/acpi_dev_interface.h"
  42 #include "hw/xen/xen.h"
  43 #include "qom/cpu.h"
  44
  45 #include "sysemu/hax.h"
  46
  47 #ifdef CONFIG_MARU
  48 #include "tizen/src/hw/maru_pm.h"
  49 #endif
  50
  51 //#define DEBUG
  52
  53 #ifdef DEBUG
  54 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  55 #else
  56 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  57 #endif
  58
  59 #define GPE_BASE 0xafe0
  60 #define GPE_LEN 4
  61
  62 struct pci_status {
  63     uint32_t up; /* deprecated, maintained for migration compatibility */
  64     uint32_t down;
  65 };
  66
  67 typedef struct PIIX4PMState {
  68     /*< private >*/
  69     PCIDevice parent_obj;
  70     /*< public >*/
  71
  72     MemoryRegion io;
  73     uint32_t io_base;
  74
  75     MemoryRegion io_gpe;
  76     ACPIREGS ar;
  77
  78     APMState apm;
  79
  80     PMSMBus smb;
  81     uint32_t smb_io_base;
  82
  83     qemu_irq irq;
  84     qemu_irq smi_irq;
  85     int smm_enabled;
  86     Notifier machine_ready;
  87     Notifier powerdown_notifier;
  88
  89     AcpiPciHpState acpi_pci_hotplug;
  90     bool use_acpi_pci_hotplug;
  91
  92     uint8_t disable_s3;
  93     uint8_t disable_s4;
  94     uint8_t s4_val;
  95
  96     bool cpu_hotplug_legacy;
  97     AcpiCpuHotplug gpe_cpu;
  98     CPUHotplugState cpuhp_state;
  99
 100     MemHotplugState acpi_memory_hotplug;
 101 } PIIX4PMState;
 102
 103 #define TYPE_PIIX4_PM "PIIX4_PM"
 104
 105 #define PIIX4_PM(obj) \
 106     OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
 107
 108 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 109                                            PCIBus *bus, PIIX4PMState *s);
 110
 111 #define ACPI_ENABLE 0xf1
 112 #define ACPI_DISABLE 0xf0
 113
 114 static void pm_tmr_timer(ACPIREGS *ar)
 115 {
 116     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 117     acpi_update_sci(&s->ar, s->irq);
 118 }
 119
 120 static void apm_ctrl_changed(uint32_t val, void *arg)
 121 {
 122     PIIX4PMState *s = arg;
 123     PCIDevice *d = PCI_DEVICE(s);
 124
 125     /* ACPI specs 3.0, 4.7.2.5 */
 126     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 127     if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
 128         return;
 129     }
 130
 131     if (d->config[0x5b] & (1 << 1)) {
 132         if (s->smi_irq) {
 133             qemu_irq_raise(s->smi_irq);
 134         }
 135     }
 136 }
 137
 138 static void pm_io_space_update(PIIX4PMState *s)
 139 {
 140     PCIDevice *d = PCI_DEVICE(s);
 141
 142     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
 143     s->io_base &= 0xffc0;
 144
 145     memory_region_transaction_begin();
 146     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
 147     memory_region_set_address(&s->io, s->io_base);
 148     memory_region_transaction_commit();
 149 }
 150
 151 static void smbus_io_space_update(PIIX4PMState *s)
 152 {
 153     PCIDevice *d = PCI_DEVICE(s);
 154
 155     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 156     s->smb_io_base &= 0xffc0;
 157
 158     memory_region_transaction_begin();
 159     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 160     memory_region_set_address(&s->smb.io, s->smb_io_base);
 161     memory_region_transaction_commit();
 162 }
 163
 164 static void pm_write_config(PCIDevice *d,
 165                             uint32_t address, uint32_t val, int len)
 166 {
 167     pci_default_write_config(d, address, val, len);
 168     if (range_covers_byte(address, len, 0x80) ||
 169         ranges_overlap(address, len, 0x40, 4)) {
 170         pm_io_space_update((PIIX4PMState *)d);
 171     }
 172     if (range_covers_byte(address, len, 0xd2) ||
 173         ranges_overlap(address, len, 0x90, 4)) {
 174         smbus_io_space_update((PIIX4PMState *)d);
 175     }
 176 }
 177
 178 static int vmstate_acpi_post_load(void *opaque, int version_id)
 179 {
 180     PIIX4PMState *s = opaque;
 181
 182     pm_io_space_update(s);
 183     return 0;
 184 }
 185
 186 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 187  {                                                                   \
 188      .name       = (stringify(_field)),                              \
 189      .version_id = 0,                                                \
 190      .info       = &vmstate_info_uint16,                             \
 191      .size       = sizeof(uint16_t),                                 \
 192      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 193      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 194  }
 195
 196 static const VMStateDescription vmstate_gpe = {
 197     .name = "gpe",
 198     .version_id = 1,
 199     .minimum_version_id = 1,
 200     .fields = (VMStateField[]) {
 201         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 202         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 203         VMSTATE_END_OF_LIST()
 204     }
 205 };
 206
 207 static const VMStateDescription vmstate_pci_status = {
 208     .name = "pci_status",
 209     .version_id = 1,
 210     .minimum_version_id = 1,
 211     .fields = (VMStateField[]) {
 212         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 213         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 214         VMSTATE_END_OF_LIST()
 215     }
 216 };
 217
 218 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
 219 {
 220     PIIX4PMState *s = opaque;
 221     int ret, i;
 222     uint16_t temp;
 223
 224     ret = pci_device_load(PCI_DEVICE(s), f);
 225     if (ret < 0) {
 226         return ret;
 227     }
 228     qemu_get_be16s(f, &s->ar.pm1.evt.sts);
 229     qemu_get_be16s(f, &s->ar.pm1.evt.en);
 230     qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
 231
 232     ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
 233     if (ret) {
 234         return ret;
 235     }
 236
 237     timer_get(f, s->ar.tmr.timer);
 238     qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
 239
 240     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
 241     for (i = 0; i < 3; i++) {
 242         qemu_get_be16s(f, &temp);
 243     }
 244
 245     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
 246     for (i = 0; i < 3; i++) {
 247         qemu_get_be16s(f, &temp);
 248     }
 249
 250     ret = vmstate_load_state(f, &vmstate_pci_status,
 251         &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
 252     return ret;
 253 }
 254
 255 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 256 {
 257     PIIX4PMState *s = opaque;
 258     return s->use_acpi_pci_hotplug;
 259 }
 260
 261 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
 262 {
 263     PIIX4PMState *s = opaque;
 264     return !s->use_acpi_pci_hotplug;
 265 }
 266
 267 static bool vmstate_test_use_memhp(void *opaque)
 268 {
 269     PIIX4PMState *s = opaque;
 270     return s->acpi_memory_hotplug.is_enabled;
 271 }
 272
 273 static const VMStateDescription vmstate_memhp_state = {
 274     .name = "piix4_pm/memhp",
 275     .version_id = 1,
 276     .minimum_version_id = 1,
 277     .minimum_version_id_old = 1,
 278     .needed = vmstate_test_use_memhp,
 279     .fields      = (VMStateField[]) {
 280         VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
 281         VMSTATE_END_OF_LIST()
 282     }
 283 };
 284
 285 static bool vmstate_test_use_cpuhp(void *opaque)
 286 {
 287     PIIX4PMState *s = opaque;
 288     return !s->cpu_hotplug_legacy;
 289 }
 290
 291 static int vmstate_cpuhp_pre_load(void *opaque)
 292 {
 293     Object *obj = OBJECT(opaque);
 294     object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort);
 295     return 0;
 296 }
 297
 298 static const VMStateDescription vmstate_cpuhp_state = {
 299     .name = "piix4_pm/cpuhp",
 300     .version_id = 1,
 301     .minimum_version_id = 1,
 302     .minimum_version_id_old = 1,
 303     .needed = vmstate_test_use_cpuhp,
 304     .pre_load = vmstate_cpuhp_pre_load,
 305     .fields      = (VMStateField[]) {
 306         VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState),
 307         VMSTATE_END_OF_LIST()
 308     }
 309 };
 310
 311 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 312  * To support incoming qemu-kvm 1.2 migration, change version_id
 313  * and minimum_version_id to 2 below (which breaks migration from
 314  * qemu 1.2).
 315  *
 316  */
 317 static const VMStateDescription vmstate_acpi = {
 318     .name = "piix4_pm",
 319     .version_id = 3,
 320     .minimum_version_id = 3,
 321     .minimum_version_id_old = 1,
 322     .load_state_old = acpi_load_old,
 323     .post_load = vmstate_acpi_post_load,
 324     .fields = (VMStateField[]) {
 325         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 326         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 327         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 328         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 329         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 330         VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
 331         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 332         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 333         VMSTATE_STRUCT_TEST(
 334             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 335             PIIX4PMState,
 336             vmstate_test_no_use_acpi_pci_hotplug,
 337             2, vmstate_pci_status,
 338             struct AcpiPciHpPciStatus),
 339         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 340                             vmstate_test_use_acpi_pci_hotplug),
 341         VMSTATE_END_OF_LIST()
 342     },
 343     .subsections = (const VMStateDescription*[]) {
 344          &vmstate_memhp_state,
 345          &vmstate_cpuhp_state,
 346          NULL
 347     }
 348 };
 349
 350 static void piix4_reset(void *opaque)
 351 {
 352     PIIX4PMState *s = opaque;
 353     PCIDevice *d = PCI_DEVICE(s);
 354     uint8_t *pci_conf = d->config;
 355
 356     pci_conf[0x58] = 0;
 357     pci_conf[0x59] = 0;
 358     pci_conf[0x5a] = 0;
 359     pci_conf[0x5b] = 0;
 360
 361     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 362     pci_conf[0x80] = 0;
 363
 364     if (!s->smm_enabled) {
 365         /* Mark SMM as already inited (until KVM supports SMM). */
 366         pci_conf[0x5B] = 0x02;
 367     }
 368     pm_io_space_update(s);
 369     acpi_pcihp_reset(&s->acpi_pci_hotplug);
 370 }
 371
 372 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 373 {
 374     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 375
 376     assert(s != NULL);
 377     acpi_pm1_evt_power_down(&s->ar);
 378 }
 379
 380 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
 381                                  DeviceState *dev, Error **errp)
 382 {
 383     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 384
 385     if (s->acpi_memory_hotplug.is_enabled &&
 386         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 387         if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
 388             nvdimm_acpi_plug_cb(hotplug_dev, dev);
 389         } else {
 390             acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug,
 391                                 dev, errp);
 392         }
 393     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 394         acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp);
 395     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 396         if (s->cpu_hotplug_legacy) {
 397             legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp);
 398         } else {
 399             acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
 400         }
 401     } else {
 402         error_setg(errp, "acpi: device plug request for not supported device"
 403                    " type: %s", object_get_typename(OBJECT(dev)));
 404     }
 405 }
 406
 407 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 408                                            DeviceState *dev, Error **errp)
 409 {
 410     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 411
 412     if (s->acpi_memory_hotplug.is_enabled &&
 413         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 414         acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug,
 415                                       dev, errp);
 416     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 417         acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev,
 418                                     errp);
 419     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
 420                !s->cpu_hotplug_legacy) {
 421         acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
 422     } else {
 423         error_setg(errp, "acpi: device unplug request for not supported device"
 424                    " type: %s", object_get_typename(OBJECT(dev)));
 425     }
 426 }
 427
 428 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
 429                                    DeviceState *dev, Error **errp)
 430 {
 431     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 432
 433     if (s->acpi_memory_hotplug.is_enabled &&
 434         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 435         acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
 436     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
 437                !s->cpu_hotplug_legacy) {
 438         acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
 439     } else {
 440         error_setg(errp, "acpi: device unplug for not supported device"
 441                    " type: %s", object_get_typename(OBJECT(dev)));
 442     }
 443 }
 444
 445 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque)
 446 {
 447     PIIX4PMState *s = opaque;
 448
 449     qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort);
 450 }
 451
 452 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 453 {
 454     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 455     PCIDevice *d = PCI_DEVICE(s);
 456     MemoryRegion *io_as = pci_address_space_io(d);
 457     uint8_t *pci_conf;
 458
 459     pci_conf = d->config;
 460     pci_conf[0x5f] = 0x10 |
 461         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 462     pci_conf[0x63] = 0x60;
 463     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 464         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 465
 466     if (s->use_acpi_pci_hotplug) {
 467         pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
 468     } else {
 469         piix4_update_bus_hotplug(d->bus, s);
 470     }
 471 }
 472
 473 static void piix4_pm_add_propeties(PIIX4PMState *s)
 474 {
 475     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 476     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 477     static const uint32_t gpe0_blk = GPE_BASE;
 478     static const uint32_t gpe0_blk_len = GPE_LEN;
 479     static const uint16_t sci_int = 9;
 480
 481     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 482                                   &acpi_enable_cmd, NULL);
 483     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 484                                   &acpi_disable_cmd, NULL);
 485     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 486                                   &gpe0_blk, NULL);
 487     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 488                                   &gpe0_blk_len, NULL);
 489     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 490                                   &sci_int, NULL);
 491     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 492                                   &s->io_base, NULL);
 493 }
 494
 495 static void piix4_pm_realize(PCIDevice *dev, Error **errp)
 496 {
 497     PIIX4PMState *s = PIIX4_PM(dev);
 498     uint8_t *pci_conf;
 499
 500     pci_conf = dev->config;
 501     pci_conf[0x06] = 0x80;
 502     pci_conf[0x07] = 0x02;
 503     pci_conf[0x09] = 0x00;
 504     pci_conf[0x3d] = 0x01; // interrupt pin 1
 505
 506     /* APM */
 507     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 508
 509     if (!s->smm_enabled) {
 510         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 511          * support SMM mode. */
 512         pci_conf[0x5B] = 0x02;
 513     }
 514
 515     /* XXX: which specification is used ? The i82731AB has different
 516        mappings */
 517     pci_conf[0x90] = s->smb_io_base | 1;
 518     pci_conf[0x91] = s->smb_io_base >> 8;
 519     pci_conf[0xd2] = 0x09;
 520     pm_smbus_init(DEVICE(dev), &s->smb);
 521     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 522     memory_region_add_subregion(pci_address_space_io(dev),
 523                                 s->smb_io_base, &s->smb.io);
 524
 525     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 526     memory_region_set_enabled(&s->io, false);
 527     memory_region_add_subregion(pci_address_space_io(dev),
 528                                 0, &s->io);
 529
 530     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 531     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 532     acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val);
 533     acpi_gpe_init(&s->ar, GPE_LEN);
 534 #ifdef CONFIG_MARU
 535     acpi_maru_pm_init(&s->ar, pm_tmr_timer);
 536 #endif
 537
 538     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 539     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 540
 541     s->machine_ready.notify = piix4_pm_machine_ready;
 542     qemu_add_machine_init_done_notifier(&s->machine_ready);
 543     qemu_register_reset(piix4_reset, s);
 544
 545     piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
 546
 547     piix4_pm_add_propeties(s);
 548 }
 549
 550 Object *piix4_pm_find(void)
 551 {
 552     bool ambig;
 553     Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
 554
 555     if (ambig || !o) {
 556         return NULL;
 557     }
 558     return o;
 559 }
 560
 561 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 562                       qemu_irq sci_irq, qemu_irq smi_irq,
 563                       int smm_enabled, DeviceState **piix4_pm)
 564 {
 565     DeviceState *dev;
 566     PIIX4PMState *s;
 567
 568     dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
 569     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
 570     if (piix4_pm) {
 571         *piix4_pm = dev;
 572     }
 573
 574     s = PIIX4_PM(dev);
 575     s->irq = sci_irq;
 576     s->smi_irq = smi_irq;
 577     s->smm_enabled = smm_enabled;
 578     if (xen_enabled()) {
 579         s->use_acpi_pci_hotplug = false;
 580     }
 581
 582     qdev_init_nofail(dev);
 583
 584     return s->smb.smbus;
 585 }
 586
 587 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 588 {
 589     PIIX4PMState *s = opaque;
 590     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 591
 592     PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
 593     return val;
 594 }
 595
 596 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 597                        unsigned width)
 598 {
 599     PIIX4PMState *s = opaque;
 600
 601     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 602     acpi_update_sci(&s->ar, s->irq);
 603
 604     PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
 605 }
 606
 607 static const MemoryRegionOps piix4_gpe_ops = {
 608     .read = gpe_readb,
 609     .write = gpe_writeb,
 610     .valid.min_access_size = 1,
 611     .valid.max_access_size = 4,
 612     .impl.min_access_size = 1,
 613     .impl.max_access_size = 1,
 614     .endianness = DEVICE_LITTLE_ENDIAN,
 615 };
 616
 617
 618 static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp)
 619 {
 620     PIIX4PMState *s = PIIX4_PM(obj);
 621
 622     return s->cpu_hotplug_legacy;
 623 }
 624
 625 static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp)
 626 {
 627     PIIX4PMState *s = PIIX4_PM(obj);
 628
 629     assert(!value);
 630     if (s->cpu_hotplug_legacy && value == false) {
 631         acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state,
 632                                    PIIX4_CPU_HOTPLUG_IO_BASE);
 633     }
 634     s->cpu_hotplug_legacy = value;
 635 }
 636
 637 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 638                                            PCIBus *bus, PIIX4PMState *s)
 639 {
 640     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 641                           "acpi-gpe0", GPE_LEN);
 642     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 643
 644     acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
 645                     s->use_acpi_pci_hotplug);
 646
 647     s->cpu_hotplug_legacy = true;
 648     object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy",
 649                              piix4_get_cpu_hotplug_legacy,
 650                              piix4_set_cpu_hotplug_legacy,
 651                              NULL);
 652     legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 653                                  PIIX4_CPU_HOTPLUG_IO_BASE);
 654
 655     if (s->acpi_memory_hotplug.is_enabled) {
 656         acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug);
 657     }
 658 }
 659
 660 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
 661 {
 662     PIIX4PMState *s = PIIX4_PM(adev);
 663
 664     acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
 665     if (!s->cpu_hotplug_legacy) {
 666         acpi_cpu_ospm_status(&s->cpuhp_state, list);
 667     }
 668 }
 669
 670 static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
 671 {
 672     PIIX4PMState *s = PIIX4_PM(adev);
 673
 674     acpi_send_gpe_event(&s->ar, s->irq, ev);
 675 }
 676
 677 static Property piix4_pm_properties[] = {
 678     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 679     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 680     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 681     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 682     DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
 683                      use_acpi_pci_hotplug, true),
 684     DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
 685                      acpi_memory_hotplug.is_enabled, true),
 686     DEFINE_PROP_END_OF_LIST(),
 687 };
 688
 689 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 690 {
 691     DeviceClass *dc = DEVICE_CLASS(klass);
 692     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 693     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 694     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
 695
 696     k->realize = piix4_pm_realize;
 697     k->config_write = pm_write_config;
 698     k->vendor_id = PCI_VENDOR_ID_INTEL;
 699     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 700     k->revision = 0x03;
 701     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 702     dc->desc = "PM";
 703     dc->vmsd = &vmstate_acpi;
 704     dc->props = piix4_pm_properties;
 705     /*
 706      * Reason: part of PIIX4 southbridge, needs to be wired up,
 707      * e.g. by mips_malta_init()
 708      */
 709     dc->cannot_instantiate_with_device_add_yet = true;
 710     dc->hotpluggable = false;
 711     hc->plug = piix4_device_plug_cb;
 712     hc->unplug_request = piix4_device_unplug_request_cb;
 713     hc->unplug = piix4_device_unplug_cb;
 714     adevc->ospm_status = piix4_ospm_status;
 715     adevc->send_event = piix4_send_gpe;
 716     adevc->madt_cpu = pc_madt_cpu_entry;
 717 }
 718
 719 static const TypeInfo piix4_pm_info = {
 720     .name          = TYPE_PIIX4_PM,
 721     .parent        = TYPE_PCI_DEVICE,
 722     .instance_size = sizeof(PIIX4PMState),
 723     .class_init    = piix4_pm_class_init,
 724     .interfaces = (InterfaceInfo[]) {
 725         { TYPE_HOTPLUG_HANDLER },
 726         { TYPE_ACPI_DEVICE_IF },
 727         { }
 728     }
 729 };
 730
 731 static void piix4_pm_register_types(void)
 732 {
 733     type_register_static(&piix4_pm_info);
 734 }
 735
 736 type_init(piix4_pm_register_types)