hw/acpi/piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "hw/hw.h"
  22 #include "hw/i386/pc.h"
  23 #include "hw/isa/apm.h"
  24 #include "hw/i2c/pm_smbus.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/acpi/acpi.h"
  27 #include "sysemu/sysemu.h"
  28 #include "sysemu/hax.h"
  29 #include "qemu/range.h"
  30 #include "exec/ioport.h"
  31 #include "hw/nvram/fw_cfg.h"
  32 #include "exec/address-spaces.h"
  33 #include "hw/acpi/piix4.h"
  34 #include "hw/acpi/pcihp.h"
  35 #include "hw/acpi/cpu_hotplug.h"
  36 #include "hw/hotplug.h"
  37 #include "hw/mem/pc-dimm.h"
  38 #include "hw/acpi/memory_hotplug.h"
  39 #include "hw/acpi/acpi_dev_interface.h"
  40 #include "hw/xen/xen.h"
  41
  42 #ifdef CONFIG_MARU
  43 #include "tizen/src/hw/maru_pm.h"
  44 #endif
  45
  46 //#define DEBUG
  47
  48 #ifdef DEBUG
  49 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  50 #else
  51 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  52 #endif
  53
  54 #define GPE_BASE 0xafe0
  55 #define GPE_LEN 4
  56
  57 struct pci_status {
  58     uint32_t up; /* deprecated, maintained for migration compatibility */
  59     uint32_t down;
  60 };
  61
  62 typedef struct PIIX4PMState {
  63     /*< private >*/
  64     PCIDevice parent_obj;
  65     /*< public >*/
  66
  67     MemoryRegion io;
  68     uint32_t io_base;
  69
  70     MemoryRegion io_gpe;
  71     ACPIREGS ar;
  72
  73     APMState apm;
  74
  75     PMSMBus smb;
  76     uint32_t smb_io_base;
  77
  78     qemu_irq irq;
  79     qemu_irq smi_irq;
  80     int smm_enabled;
  81     Notifier machine_ready;
  82     Notifier powerdown_notifier;
  83
  84     AcpiPciHpState acpi_pci_hotplug;
  85     bool use_acpi_pci_hotplug;
  86
  87     uint8_t disable_s3;
  88     uint8_t disable_s4;
  89     uint8_t s4_val;
  90
  91     AcpiCpuHotplug gpe_cpu;
  92
  93     MemHotplugState acpi_memory_hotplug;
  94 } PIIX4PMState;
  95
  96 #define TYPE_PIIX4_PM "PIIX4_PM"
  97
  98 #define PIIX4_PM(obj) \
  99     OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
 100
 101 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 102                                            PCIBus *bus, PIIX4PMState *s);
 103
 104 #define ACPI_ENABLE 0xf1
 105 #define ACPI_DISABLE 0xf0
 106
 107 static void pm_tmr_timer(ACPIREGS *ar)
 108 {
 109     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 110     acpi_update_sci(&s->ar, s->irq);
 111 }
 112
 113 static void apm_ctrl_changed(uint32_t val, void *arg)
 114 {
 115     PIIX4PMState *s = arg;
 116     PCIDevice *d = PCI_DEVICE(s);
 117
 118     /* ACPI specs 3.0, 4.7.2.5 */
 119     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 120     if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
 121         return;
 122     }
 123
 124     if (d->config[0x5b] & (1 << 1)) {
 125         if (s->smi_irq) {
 126             qemu_irq_raise(s->smi_irq);
 127         }
 128     }
 129 }
 130
 131 static void pm_io_space_update(PIIX4PMState *s)
 132 {
 133     PCIDevice *d = PCI_DEVICE(s);
 134
 135     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
 136     s->io_base &= 0xffc0;
 137
 138     memory_region_transaction_begin();
 139     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
 140     memory_region_set_address(&s->io, s->io_base);
 141     memory_region_transaction_commit();
 142 }
 143
 144 static void smbus_io_space_update(PIIX4PMState *s)
 145 {
 146     PCIDevice *d = PCI_DEVICE(s);
 147
 148     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 149     s->smb_io_base &= 0xffc0;
 150
 151     memory_region_transaction_begin();
 152     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 153     memory_region_set_address(&s->smb.io, s->smb_io_base);
 154     memory_region_transaction_commit();
 155 }
 156
 157 static void pm_write_config(PCIDevice *d,
 158                             uint32_t address, uint32_t val, int len)
 159 {
 160     pci_default_write_config(d, address, val, len);
 161     if (range_covers_byte(address, len, 0x80) ||
 162         ranges_overlap(address, len, 0x40, 4)) {
 163         pm_io_space_update((PIIX4PMState *)d);
 164     }
 165     if (range_covers_byte(address, len, 0xd2) ||
 166         ranges_overlap(address, len, 0x90, 4)) {
 167         smbus_io_space_update((PIIX4PMState *)d);
 168     }
 169 }
 170
 171 static int vmstate_acpi_post_load(void *opaque, int version_id)
 172 {
 173     PIIX4PMState *s = opaque;
 174
 175     pm_io_space_update(s);
 176     return 0;
 177 }
 178
 179 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 180  {                                                                   \
 181      .name       = (stringify(_field)),                              \
 182      .version_id = 0,                                                \
 183      .info       = &vmstate_info_uint16,                             \
 184      .size       = sizeof(uint16_t),                                 \
 185      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 186      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 187  }
 188
 189 static const VMStateDescription vmstate_gpe = {
 190     .name = "gpe",
 191     .version_id = 1,
 192     .minimum_version_id = 1,
 193     .fields = (VMStateField[]) {
 194         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 195         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 196         VMSTATE_END_OF_LIST()
 197     }
 198 };
 199
 200 static const VMStateDescription vmstate_pci_status = {
 201     .name = "pci_status",
 202     .version_id = 1,
 203     .minimum_version_id = 1,
 204     .fields = (VMStateField[]) {
 205         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 206         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 207         VMSTATE_END_OF_LIST()
 208     }
 209 };
 210
 211 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
 212 {
 213     PIIX4PMState *s = opaque;
 214     int ret, i;
 215     uint16_t temp;
 216
 217     ret = pci_device_load(PCI_DEVICE(s), f);
 218     if (ret < 0) {
 219         return ret;
 220     }
 221     qemu_get_be16s(f, &s->ar.pm1.evt.sts);
 222     qemu_get_be16s(f, &s->ar.pm1.evt.en);
 223     qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
 224
 225     ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
 226     if (ret) {
 227         return ret;
 228     }
 229
 230     timer_get(f, s->ar.tmr.timer);
 231     qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
 232
 233     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
 234     for (i = 0; i < 3; i++) {
 235         qemu_get_be16s(f, &temp);
 236     }
 237
 238     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
 239     for (i = 0; i < 3; i++) {
 240         qemu_get_be16s(f, &temp);
 241     }
 242
 243     ret = vmstate_load_state(f, &vmstate_pci_status,
 244         &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
 245     return ret;
 246 }
 247
 248 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 249 {
 250     PIIX4PMState *s = opaque;
 251     return s->use_acpi_pci_hotplug;
 252 }
 253
 254 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
 255 {
 256     PIIX4PMState *s = opaque;
 257     return !s->use_acpi_pci_hotplug;
 258 }
 259
 260 static bool vmstate_test_use_memhp(void *opaque)
 261 {
 262     PIIX4PMState *s = opaque;
 263     return s->acpi_memory_hotplug.is_enabled;
 264 }
 265
 266 static const VMStateDescription vmstate_memhp_state = {
 267     .name = "piix4_pm/memhp",
 268     .version_id = 1,
 269     .minimum_version_id = 1,
 270     .minimum_version_id_old = 1,
 271     .needed = vmstate_test_use_memhp,
 272     .fields      = (VMStateField[]) {
 273         VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
 274         VMSTATE_END_OF_LIST()
 275     }
 276 };
 277
 278 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 279  * To support incoming qemu-kvm 1.2 migration, change version_id
 280  * and minimum_version_id to 2 below (which breaks migration from
 281  * qemu 1.2).
 282  *
 283  */
 284 static const VMStateDescription vmstate_acpi = {
 285     .name = "piix4_pm",
 286     .version_id = 3,
 287     .minimum_version_id = 3,
 288     .minimum_version_id_old = 1,
 289     .load_state_old = acpi_load_old,
 290     .post_load = vmstate_acpi_post_load,
 291     .fields = (VMStateField[]) {
 292         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 293         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 294         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 295         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 296         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 297         VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
 298         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 299         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 300         VMSTATE_STRUCT_TEST(
 301             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 302             PIIX4PMState,
 303             vmstate_test_no_use_acpi_pci_hotplug,
 304             2, vmstate_pci_status,
 305             struct AcpiPciHpPciStatus),
 306         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 307                             vmstate_test_use_acpi_pci_hotplug),
 308         VMSTATE_END_OF_LIST()
 309     },
 310     .subsections = (const VMStateDescription*[]) {
 311          &vmstate_memhp_state,
 312          NULL
 313     }
 314 };
 315
 316 static void piix4_reset(void *opaque)
 317 {
 318     PIIX4PMState *s = opaque;
 319     PCIDevice *d = PCI_DEVICE(s);
 320     uint8_t *pci_conf = d->config;
 321
 322     pci_conf[0x58] = 0;
 323     pci_conf[0x59] = 0;
 324     pci_conf[0x5a] = 0;
 325     pci_conf[0x5b] = 0;
 326
 327     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 328     pci_conf[0x80] = 0;
 329
 330     if (!s->smm_enabled) {
 331         /* Mark SMM as already inited (until KVM supports SMM). */
 332         pci_conf[0x5B] = 0x02;
 333     }
 334     pm_io_space_update(s);
 335     acpi_pcihp_reset(&s->acpi_pci_hotplug);
 336 }
 337
 338 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 339 {
 340     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 341
 342     assert(s != NULL);
 343     acpi_pm1_evt_power_down(&s->ar);
 344 }
 345
 346 static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
 347                                  DeviceState *dev, Error **errp)
 348 {
 349     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 350
 351     if (s->acpi_memory_hotplug.is_enabled &&
 352         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 353         acpi_memory_plug_cb(&s->ar, s->irq, &s->acpi_memory_hotplug, dev, errp);
 354     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 355         acpi_pcihp_device_plug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev,
 356                                   errp);
 357     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
 358         acpi_cpu_plug_cb(&s->ar, s->irq, &s->gpe_cpu, dev, errp);
 359     } else {
 360         error_setg(errp, "acpi: device plug request for not supported device"
 361                    " type: %s", object_get_typename(OBJECT(dev)));
 362     }
 363 }
 364
 365 static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 366                                            DeviceState *dev, Error **errp)
 367 {
 368     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 369
 370     if (s->acpi_memory_hotplug.is_enabled &&
 371         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 372         acpi_memory_unplug_request_cb(&s->ar, s->irq, &s->acpi_memory_hotplug,
 373                                       dev, errp);
 374     } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
 375         acpi_pcihp_device_unplug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev,
 376                                     errp);
 377     } else {
 378         error_setg(errp, "acpi: device unplug request for not supported device"
 379                    " type: %s", object_get_typename(OBJECT(dev)));
 380     }
 381 }
 382
 383 static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
 384                                    DeviceState *dev, Error **errp)
 385 {
 386     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 387
 388     if (s->acpi_memory_hotplug.is_enabled &&
 389         object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
 390         acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
 391     } else {
 392         error_setg(errp, "acpi: device unplug for not supported device"
 393                    " type: %s", object_get_typename(OBJECT(dev)));
 394     }
 395 }
 396
 397 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque)
 398 {
 399     PIIX4PMState *s = opaque;
 400
 401     qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort);
 402 }
 403
 404 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 405 {
 406     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 407     PCIDevice *d = PCI_DEVICE(s);
 408     MemoryRegion *io_as = pci_address_space_io(d);
 409     uint8_t *pci_conf;
 410
 411     pci_conf = d->config;
 412     pci_conf[0x5f] = 0x10 |
 413         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 414     pci_conf[0x63] = 0x60;
 415     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 416         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 417
 418     if (s->use_acpi_pci_hotplug) {
 419         pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
 420     } else {
 421         piix4_update_bus_hotplug(d->bus, s);
 422     }
 423 }
 424
 425 static void piix4_pm_add_propeties(PIIX4PMState *s)
 426 {
 427     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 428     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 429     static const uint32_t gpe0_blk = GPE_BASE;
 430     static const uint32_t gpe0_blk_len = GPE_LEN;
 431     static const uint16_t sci_int = 9;
 432
 433     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 434                                   &acpi_enable_cmd, NULL);
 435     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 436                                   &acpi_disable_cmd, NULL);
 437     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 438                                   &gpe0_blk, NULL);
 439     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 440                                   &gpe0_blk_len, NULL);
 441     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 442                                   &sci_int, NULL);
 443     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 444                                   &s->io_base, NULL);
 445 }
 446
 447 static void piix4_pm_realize(PCIDevice *dev, Error **errp)
 448 {
 449     PIIX4PMState *s = PIIX4_PM(dev);
 450     uint8_t *pci_conf;
 451
 452     pci_conf = dev->config;
 453     pci_conf[0x06] = 0x80;
 454     pci_conf[0x07] = 0x02;
 455     pci_conf[0x09] = 0x00;
 456     pci_conf[0x3d] = 0x01; // interrupt pin 1
 457
 458     /* APM */
 459     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 460
 461     if (!s->smm_enabled) {
 462         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 463          * support SMM mode. */
 464         pci_conf[0x5B] = 0x02;
 465     }
 466
 467     /* XXX: which specification is used ? The i82731AB has different
 468        mappings */
 469     pci_conf[0x90] = s->smb_io_base | 1;
 470     pci_conf[0x91] = s->smb_io_base >> 8;
 471     pci_conf[0xd2] = 0x09;
 472     pm_smbus_init(DEVICE(dev), &s->smb);
 473     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 474     memory_region_add_subregion(pci_address_space_io(dev),
 475                                 s->smb_io_base, &s->smb.io);
 476
 477     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 478     memory_region_set_enabled(&s->io, false);
 479     memory_region_add_subregion(pci_address_space_io(dev),
 480                                 0, &s->io);
 481
 482     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 483     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 484     acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val);
 485     acpi_gpe_init(&s->ar, GPE_LEN);
 486 #ifdef CONFIG_MARU
 487     acpi_maru_pm_init(&s->ar, pm_tmr_timer);
 488 #endif
 489
 490     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 491     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 492
 493     s->machine_ready.notify = piix4_pm_machine_ready;
 494     qemu_add_machine_init_done_notifier(&s->machine_ready);
 495     qemu_register_reset(piix4_reset, s);
 496
 497     piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
 498
 499     piix4_pm_add_propeties(s);
 500 }
 501
 502 Object *piix4_pm_find(void)
 503 {
 504     bool ambig;
 505     Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
 506
 507     if (ambig || !o) {
 508         return NULL;
 509     }
 510     return o;
 511 }
 512
 513 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 514                       qemu_irq sci_irq, qemu_irq smi_irq,
 515                       int smm_enabled, DeviceState **piix4_pm)
 516 {
 517     DeviceState *dev;
 518     PIIX4PMState *s;
 519
 520     dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
 521     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
 522     if (piix4_pm) {
 523         *piix4_pm = dev;
 524     }
 525
 526     s = PIIX4_PM(dev);
 527     s->irq = sci_irq;
 528     s->smi_irq = smi_irq;
 529     s->smm_enabled = smm_enabled;
 530     if (xen_enabled()) {
 531         s->use_acpi_pci_hotplug = false;
 532     }
 533
 534     qdev_init_nofail(dev);
 535
 536     return s->smb.smbus;
 537 }
 538
 539 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 540 {
 541     PIIX4PMState *s = opaque;
 542     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 543
 544     PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
 545     return val;
 546 }
 547
 548 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 549                        unsigned width)
 550 {
 551     PIIX4PMState *s = opaque;
 552
 553     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 554     acpi_update_sci(&s->ar, s->irq);
 555
 556     PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
 557 }
 558
 559 static const MemoryRegionOps piix4_gpe_ops = {
 560     .read = gpe_readb,
 561     .write = gpe_writeb,
 562     .valid.min_access_size = 1,
 563     .valid.max_access_size = 4,
 564     .impl.min_access_size = 1,
 565     .impl.max_access_size = 1,
 566     .endianness = DEVICE_LITTLE_ENDIAN,
 567 };
 568
 569 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 570                                            PCIBus *bus, PIIX4PMState *s)
 571 {
 572     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 573                           "acpi-gpe0", GPE_LEN);
 574     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 575
 576     acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
 577                     s->use_acpi_pci_hotplug);
 578
 579     acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 580                           PIIX4_CPU_HOTPLUG_IO_BASE);
 581
 582     if (s->acpi_memory_hotplug.is_enabled) {
 583         acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug);
 584     }
 585 }
 586
 587 static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
 588 {
 589     PIIX4PMState *s = PIIX4_PM(adev);
 590
 591     acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
 592 }
 593
 594 static Property piix4_pm_properties[] = {
 595     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 596     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 597     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 598     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 599     DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
 600                      use_acpi_pci_hotplug, true),
 601     DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
 602                      acpi_memory_hotplug.is_enabled, true),
 603     DEFINE_PROP_END_OF_LIST(),
 604 };
 605
 606 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 607 {
 608     DeviceClass *dc = DEVICE_CLASS(klass);
 609     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 610     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 611     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
 612
 613     k->realize = piix4_pm_realize;
 614     k->config_write = pm_write_config;
 615     k->vendor_id = PCI_VENDOR_ID_INTEL;
 616     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 617     k->revision = 0x03;
 618     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 619     dc->desc = "PM";
 620     dc->vmsd = &vmstate_acpi;
 621     dc->props = piix4_pm_properties;
 622     /*
 623      * Reason: part of PIIX4 southbridge, needs to be wired up,
 624      * e.g. by mips_malta_init()
 625      */
 626     dc->cannot_instantiate_with_device_add_yet = true;
 627     dc->hotpluggable = false;
 628     hc->plug = piix4_device_plug_cb;
 629     hc->unplug_request = piix4_device_unplug_request_cb;
 630     hc->unplug = piix4_device_unplug_cb;
 631     adevc->ospm_status = piix4_ospm_status;
 632 }
 633
 634 static const TypeInfo piix4_pm_info = {
 635     .name          = TYPE_PIIX4_PM,
 636     .parent        = TYPE_PCI_DEVICE,
 637     .instance_size = sizeof(PIIX4PMState),
 638     .class_init    = piix4_pm_class_init,
 639     .interfaces = (InterfaceInfo[]) {
 640         { TYPE_HOTPLUG_HANDLER },
 641         { TYPE_ACPI_DEVICE_IF },
 642         { }
 643     }
 644 };
 645
 646 static void piix4_pm_register_types(void)
 647 {
 648     type_register_static(&piix4_pm_info);
 649 }
 650
 651 type_init(piix4_pm_register_types)