2 * Copyright © 2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #define PCI_CHIP_I810 0x7121
29 #define PCI_CHIP_I810_DC100 0x7123
30 #define PCI_CHIP_I810_E 0x7125
31 #define PCI_CHIP_I815 0x1132
33 #define PCI_CHIP_I830_M 0x3577
34 #define PCI_CHIP_845_G 0x2562
35 #define PCI_CHIP_I855_GM 0x3582
36 #define PCI_CHIP_I865_G 0x2572
38 #define PCI_CHIP_I915_G 0x2582
39 #define PCI_CHIP_E7221_G 0x258A
40 #define PCI_CHIP_I915_GM 0x2592
41 #define PCI_CHIP_I945_G 0x2772
42 #define PCI_CHIP_I945_GM 0x27A2
43 #define PCI_CHIP_I945_GME 0x27AE
45 #define PCI_CHIP_Q35_G 0x29B2
46 #define PCI_CHIP_G33_G 0x29C2
47 #define PCI_CHIP_Q33_G 0x29D2
49 #define PCI_CHIP_IGD_GM 0xA011
50 #define PCI_CHIP_IGD_G 0xA001
52 #define IS_IGDGM(devid) (devid == PCI_CHIP_IGD_GM)
53 #define IS_IGDG(devid) (devid == PCI_CHIP_IGD_G)
54 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
56 #define PCI_CHIP_I965_G 0x29A2
57 #define PCI_CHIP_I965_Q 0x2992
58 #define PCI_CHIP_I965_G_1 0x2982
59 #define PCI_CHIP_I946_GZ 0x2972
60 #define PCI_CHIP_I965_GM 0x2A02
61 #define PCI_CHIP_I965_GME 0x2A12
63 #define PCI_CHIP_GM45_GM 0x2A42
65 #define PCI_CHIP_IGD_E_G 0x2E02
66 #define PCI_CHIP_Q45_G 0x2E12
67 #define PCI_CHIP_G45_G 0x2E22
68 #define PCI_CHIP_G41_G 0x2E32
69 #define PCI_CHIP_B43_G 0x2E42
70 #define PCI_CHIP_B43_G1 0x2E92
72 #define PCI_CHIP_ILD_G 0x0042
73 #define PCI_CHIP_ILM_G 0x0046
75 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* Desktop */
76 #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
77 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
78 #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* Mobile */
79 #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
80 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
81 #define PCI_CHIP_SANDYBRIDGE_S 0x010A /* Server */
83 #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* Desktop */
84 #define PCI_CHIP_IVYBRIDGE_GT2 0x0162
85 #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */
86 #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
87 #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */
88 #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
90 #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
91 devid == PCI_CHIP_I915_GM || \
92 devid == PCI_CHIP_I945_GM || \
93 devid == PCI_CHIP_I945_GME || \
94 devid == PCI_CHIP_I965_GM || \
95 devid == PCI_CHIP_I965_GME || \
96 devid == PCI_CHIP_GM45_GM || \
98 devid == PCI_CHIP_ILM_G)
100 #define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
101 devid == PCI_CHIP_Q45_G || \
102 devid == PCI_CHIP_G45_G || \
103 devid == PCI_CHIP_G41_G || \
104 devid == PCI_CHIP_B43_G || \
105 devid == PCI_CHIP_B43_G1)
106 #define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
107 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
109 #define IS_ILD(devid) (devid == PCI_CHIP_ILD_G)
110 #define IS_ILM(devid) (devid == PCI_CHIP_ILM_G)
111 #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
113 #define IS_915(devid) (devid == PCI_CHIP_I915_G || \
114 devid == PCI_CHIP_E7221_G || \
115 devid == PCI_CHIP_I915_GM)
117 #define IS_945(devid) (devid == PCI_CHIP_I945_G || \
118 devid == PCI_CHIP_I945_GM || \
119 devid == PCI_CHIP_I945_GME || \
120 devid == PCI_CHIP_G33_G || \
121 devid == PCI_CHIP_Q33_G || \
122 devid == PCI_CHIP_Q35_G || IS_IGD(devid))
124 #define IS_GEN4(devid) (devid == PCI_CHIP_I965_G || \
125 devid == PCI_CHIP_I965_Q || \
126 devid == PCI_CHIP_I965_G_1 || \
127 devid == PCI_CHIP_I965_GM || \
128 devid == PCI_CHIP_I965_GME || \
129 devid == PCI_CHIP_I946_GZ || \
132 /* Compat macro for intel_decode.c */
133 #define IS_IRONLAKE(devid) IS_GEN5(devid)
135 #define IS_SNB_GT1(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
136 devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
137 devid == PCI_CHIP_SANDYBRIDGE_S)
139 #define IS_SNB_GT2(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
140 devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
141 devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
142 devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
144 #define IS_GEN6(devid) (IS_SNB_GT1(devid) || IS_SNB_GT2(devid))
146 #define IS_IVB_GT1(devid) (devid == PCI_CHIP_IVYBRIDGE_GT1 || \
147 devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
148 devid == PCI_CHIP_IVYBRIDGE_S_GT1)
150 #define IS_IVB_GT2(devid) (devid == PCI_CHIP_IVYBRIDGE_GT2 || \
151 devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \
152 devid == PCI_CHIP_IVYBRIDGE_S_GT2)
154 #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || IS_IVB_GT2(devid))
156 #define IS_GEN7(devid) IS_IVYBRIDGE(devid)
158 #define IS_965(devid) (IS_GEN4(devid) || \
164 #define IS_9XX(devid) (IS_915(devid) || \
168 #define IS_GEN3(devid) (IS_915(devid) || \
171 #define IS_GEN2(devid) (devid == PCI_CHIP_I830_M || \
172 devid == PCI_CHIP_845_G || \
173 devid == PCI_CHIP_I855_GM || \
174 devid == PCI_CHIP_I865_G)