1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "main/mtypes.h"
30 #include "main/context.h"
31 #include "main/enums.h"
32 #include "main/colormac.h"
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_context.h"
37 #include "intel_fbo.h"
38 #include "intel_reg.h"
39 #include "intel_regions.h"
40 #include "intel_batchbuffer.h"
41 #include "intel_mipmap_tree.h"
43 #define FILE_DEBUG_FLAG DEBUG_BLIT
45 static GLuint translate_raster_op(GLenum logicop)
48 case GL_CLEAR: return 0x00;
49 case GL_AND: return 0x88;
50 case GL_AND_REVERSE: return 0x44;
51 case GL_COPY: return 0xCC;
52 case GL_AND_INVERTED: return 0x22;
53 case GL_NOOP: return 0xAA;
54 case GL_XOR: return 0x66;
55 case GL_OR: return 0xEE;
56 case GL_NOR: return 0x11;
57 case GL_EQUIV: return 0x99;
58 case GL_INVERT: return 0x55;
59 case GL_OR_REVERSE: return 0xDD;
60 case GL_COPY_INVERTED: return 0x33;
61 case GL_OR_INVERTED: return 0xBB;
62 case GL_NAND: return 0x77;
63 case GL_SET: return 0xFF;
90 intelEmitCopyBlit(struct intel_context *intel,
93 drm_intel_bo *src_buffer,
97 drm_intel_bo *dst_buffer,
100 GLshort src_x, GLshort src_y,
101 GLshort dst_x, GLshort dst_y,
102 GLshort w, GLshort h,
105 GLuint CMD, BR13, pass = 0;
106 int dst_y2 = dst_y + h;
107 int dst_x2 = dst_x + w;
108 drm_intel_bo *aper_array[3];
111 if (dst_tiling != I915_TILING_NONE) {
112 if (dst_offset & 4095)
114 if (dst_tiling == I915_TILING_Y)
117 if (src_tiling != I915_TILING_NONE) {
118 if (src_offset & 4095)
120 if (src_tiling == I915_TILING_Y)
124 /* do space check before going any further */
126 aper_array[0] = intel->batch.bo;
127 aper_array[1] = dst_buffer;
128 aper_array[2] = src_buffer;
130 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
131 intel_batchbuffer_flush(intel);
140 intel_batchbuffer_require_space(intel, 8 * 4, true);
141 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
143 src_buffer, src_pitch, src_offset, src_x, src_y,
144 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
149 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
152 assert(src_pitch % 4 == 0);
153 assert(dst_pitch % 4 == 0);
155 /* For big formats (such as floating point), do the copy using 32bpp and
156 * multiply the coordinates.
159 assert(cpp % 4 == 0);
166 BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
171 CMD = XY_SRC_COPY_BLT_CMD;
174 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
181 if (dst_tiling != I915_TILING_NONE) {
185 if (src_tiling != I915_TILING_NONE) {
191 if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
195 assert(dst_x < dst_x2);
196 assert(dst_y < dst_y2);
200 OUT_BATCH(BR13 | (uint16_t)dst_pitch);
201 OUT_BATCH((dst_y << 16) | dst_x);
202 OUT_BATCH((dst_y2 << 16) | dst_x2);
203 OUT_RELOC_FENCED(dst_buffer,
204 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
206 OUT_BATCH((src_y << 16) | src_x);
207 OUT_BATCH((uint16_t)src_pitch);
208 OUT_RELOC_FENCED(src_buffer,
209 I915_GEM_DOMAIN_RENDER, 0,
213 intel_batchbuffer_emit_mi_flush(intel);
220 * Use blitting to clear the renderbuffers named by 'flags'.
221 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
222 * since that might include software renderbuffers or renderbuffers
223 * which we're clearing with triangles.
224 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear
227 intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
229 struct intel_context *intel = intel_context(ctx);
230 struct gl_framebuffer *fb = ctx->DrawBuffer;
231 GLuint clear_depth_value, clear_depth_mask;
232 GLint cx, cy, cw, ch;
233 GLbitfield fail_mask = 0;
237 * Compute values for clearing the buffers.
239 clear_depth_value = 0;
240 clear_depth_mask = 0;
241 if (mask & BUFFER_BIT_DEPTH) {
242 clear_depth_value = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
243 clear_depth_mask = XY_BLT_WRITE_RGB;
245 if (mask & BUFFER_BIT_STENCIL) {
246 clear_depth_value |= (ctx->Stencil.Clear & 0xff) << 24;
247 clear_depth_mask |= XY_BLT_WRITE_ALPHA;
252 cy = ctx->DrawBuffer->Height - fb->_Ymax;
255 cw = fb->_Xmax - fb->_Xmin;
256 ch = fb->_Ymax - fb->_Ymin;
258 if (cw == 0 || ch == 0)
261 /* Loop over all renderbuffers */
262 mask &= (1 << BUFFER_COUNT) - 1;
264 GLuint buf = _mesa_ffs(mask) - 1;
265 bool is_depth_stencil = buf == BUFFER_DEPTH || buf == BUFFER_STENCIL;
266 struct intel_renderbuffer *irb;
270 struct intel_region *region;
272 drm_intel_bo *aper_array[2];
276 irb = intel_get_renderbuffer(fb, buf);
277 if (irb && irb->mt) {
278 region = irb->mt->region;
282 fail_mask |= 1 << buf;
286 /* OK, clear this renderbuffer */
287 x1 = cx + irb->draw_x;
288 y1 = cy + irb->draw_y;
289 x2 = cx + cw + irb->draw_x;
290 y2 = cy + ch + irb->draw_y;
292 pitch = region->pitch;
295 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
297 region->bo, (pitch * cpp),
298 x1, y1, x2 - x1, y2 - y1);
301 CMD = XY_COLOR_BLT_CMD;
303 /* Setup the blit command */
305 if (is_depth_stencil) {
306 CMD |= clear_depth_mask;
309 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
313 assert(region->tiling != I915_TILING_Y);
316 if (region->tiling != I915_TILING_NONE) {
321 BR13 |= (pitch * cpp);
323 if (is_depth_stencil) {
324 clear_val = clear_depth_value;
327 GLfloat *color = ctx->Color.ClearColor.f;
329 _mesa_unclamped_float_rgba_to_ubyte(clear, color);
331 switch (intel_rb_format(irb)) {
332 case MESA_FORMAT_ARGB8888:
333 case MESA_FORMAT_XRGB8888:
334 clear_val = PACK_COLOR_8888(clear[3], clear[0],
337 case MESA_FORMAT_RGB565:
338 clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]);
340 case MESA_FORMAT_ARGB4444:
341 clear_val = PACK_COLOR_4444(clear[3], clear[0],
344 case MESA_FORMAT_ARGB1555:
345 clear_val = PACK_COLOR_1555(clear[3], clear[0],
349 clear_val = PACK_COLOR_8888(clear[3], clear[3],
353 fail_mask |= 1 << buf;
358 BR13 |= br13_for_cpp(cpp);
363 /* do space check before going any further */
364 aper_array[0] = intel->batch.bo;
365 aper_array[1] = region->bo;
367 if (drm_intel_bufmgr_check_aperture_space(aper_array,
368 ARRAY_SIZE(aper_array)) != 0) {
369 intel_batchbuffer_flush(intel);
375 OUT_BATCH((y1 << 16) | x1);
376 OUT_BATCH((y2 << 16) | x2);
377 OUT_RELOC_FENCED(region->bo,
378 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
380 OUT_BATCH(clear_val);
383 if (intel->always_flush_cache)
384 intel_batchbuffer_emit_mi_flush(intel);
386 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
387 mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
394 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
396 GLubyte *src_bits, GLuint src_size,
399 drm_intel_bo *dst_buffer,
402 GLshort x, GLshort y,
403 GLshort w, GLshort h,
406 int dwords = ALIGN(src_size, 8) / 4;
407 uint32_t opcode, br13, blit_cmd;
409 if (dst_tiling != I915_TILING_NONE) {
410 if (dst_offset & 4095)
412 if (dst_tiling == I915_TILING_Y)
416 assert( logic_op - GL_CLEAR >= 0 );
417 assert( logic_op - GL_CLEAR < 0x10 );
418 assert(dst_pitch > 0);
425 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
427 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
429 intel_batchbuffer_require_space(intel,
434 opcode = XY_SETUP_BLT_CMD;
436 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
438 if (dst_tiling != I915_TILING_NONE) {
439 opcode |= XY_DST_TILED;
444 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
445 br13 |= br13_for_cpp(cpp);
447 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
448 if (dst_tiling != I915_TILING_NONE)
449 blit_cmd |= XY_DST_TILED;
451 BEGIN_BATCH_BLT(8 + 3);
454 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
455 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
456 OUT_RELOC_FENCED(dst_buffer,
457 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
459 OUT_BATCH(0); /* bg */
460 OUT_BATCH(fg_color); /* fg */
461 OUT_BATCH(0); /* pattern base addr */
463 OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
464 OUT_BATCH((y << 16) | x);
465 OUT_BATCH(((y + h) << 16) | (x + w));
468 intel_batchbuffer_data(intel, src_bits, dwords * 4, true);
470 intel_batchbuffer_emit_mi_flush(intel);
475 /* We don't have a memmove-type blit like some other hardware, so we'll do a
476 * rectangular blit covering a large space, then emit 1-scanline blit at the
477 * end to cover the last if we need.
480 intel_emit_linear_blit(struct intel_context *intel,
481 drm_intel_bo *dst_bo,
482 unsigned int dst_offset,
483 drm_intel_bo *src_bo,
484 unsigned int src_offset,
487 GLuint pitch, height;
490 /* The pitch given to the GPU must be DWORD aligned, and
491 * we want width to match pitch. Max width is (1 << 15 - 1),
492 * rounding that down to the nearest DWORD is 1 << 15 - 4
494 pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
495 height = (pitch == 0) ? 1 : size / pitch;
496 ok = intelEmitCopyBlit(intel, 1,
497 pitch, src_bo, src_offset, I915_TILING_NONE,
498 pitch, dst_bo, dst_offset, I915_TILING_NONE,
501 pitch, height, /* w, h */
505 src_offset += pitch * height;
506 dst_offset += pitch * height;
507 size -= pitch * height;
508 assert (size < (1 << 15));
509 pitch = ALIGN(size, 4);
511 ok = intelEmitCopyBlit(intel, 1,
512 pitch, src_bo, src_offset, I915_TILING_NONE,
513 pitch, dst_bo, dst_offset, I915_TILING_NONE,
523 * Used to initialize the alpha value of an ARGB8888 teximage after
524 * loading it from an XRGB8888 source.
526 * This is very common with glCopyTexImage2D().
529 intel_set_teximage_alpha_to_one(struct gl_context *ctx,
530 struct intel_texture_image *intel_image)
532 struct intel_context *intel = intel_context(ctx);
533 unsigned int image_x, image_y;
534 uint32_t x1, y1, x2, y2;
537 drm_intel_bo *aper_array[2];
538 struct intel_region *region = intel_image->mt->region;
539 int width, height, depth;
542 intel_miptree_get_dimensions_for_image(&intel_image->base.Base,
543 &width, &height, &depth);
546 assert(intel_image->base.Base.TexFormat == MESA_FORMAT_ARGB8888);
548 /* get dest x/y in destination texture */
549 intel_miptree_get_image_offset(intel_image->mt,
550 intel_image->base.Base.Level,
551 intel_image->base.Base.Face,
557 x2 = image_x + width;
558 y2 = image_y + height;
560 pitch = region->pitch;
563 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
565 intel_image->mt->region->bo, (pitch * cpp),
566 x1, y1, x2 - x1, y2 - y1);
568 BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
569 CMD = XY_COLOR_BLT_CMD;
570 CMD |= XY_BLT_WRITE_ALPHA;
572 assert(region->tiling != I915_TILING_Y);
575 if (region->tiling != I915_TILING_NONE) {
580 BR13 |= (pitch * cpp);
582 /* do space check before going any further */
583 aper_array[0] = intel->batch.bo;
584 aper_array[1] = region->bo;
586 if (drm_intel_bufmgr_check_aperture_space(aper_array,
587 ARRAY_SIZE(aper_array)) != 0) {
588 intel_batchbuffer_flush(intel);
594 OUT_BATCH((y1 << 16) | x1);
595 OUT_BATCH((y2 << 16) | x2);
596 OUT_RELOC_FENCED(region->bo,
597 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
599 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
602 intel_batchbuffer_emit_mi_flush(intel);