1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_context.h"
29 #include "intel_batchbuffer.h"
30 #include "intel_buffer_objects.h"
31 #include "intel_decode.h"
32 #include "intel_reg.h"
33 #include "intel_bufmgr.h"
34 #include "intel_buffers.h"
36 struct cached_batch_item {
37 struct cached_batch_item *next;
42 static void clear_cache( struct intel_context *intel )
44 struct cached_batch_item *item = intel->batch.cached_items;
47 struct cached_batch_item *next = item->next;
52 intel->batch.cached_items = NULL;
56 intel_batchbuffer_init(struct intel_context *intel)
58 intel_batchbuffer_reset(intel);
60 if (intel->gen >= 6) {
61 /* We can't just use brw_state_batch to get a chunk of space for
62 * the gen6 workaround because it involves actually writing to
63 * the buffer, and the kernel doesn't let us write to the batch.
65 intel->batch.workaround_bo = drm_intel_bo_alloc(intel->bufmgr,
66 "pipe_control workaround",
72 intel_batchbuffer_reset(struct intel_context *intel)
74 if (intel->batch.last_bo != NULL) {
75 drm_intel_bo_unreference(intel->batch.last_bo);
76 intel->batch.last_bo = NULL;
78 intel->batch.last_bo = intel->batch.bo;
82 intel->batch.bo = drm_intel_bo_alloc(intel->bufmgr, "batchbuffer",
83 intel->maxBatchSize, 4096);
85 intel->batch.reserved_space = BATCH_RESERVED;
86 intel->batch.state_batch_offset = intel->batch.bo->size;
87 intel->batch.used = 0;
88 intel->batch.needs_sol_reset = false;
92 intel_batchbuffer_save_state(struct intel_context *intel)
94 intel->batch.saved.used = intel->batch.used;
95 intel->batch.saved.reloc_count =
96 drm_intel_gem_bo_get_reloc_count(intel->batch.bo);
100 intel_batchbuffer_reset_to_saved(struct intel_context *intel)
102 drm_intel_gem_bo_clear_relocs(intel->batch.bo, intel->batch.saved.reloc_count);
104 intel->batch.used = intel->batch.saved.used;
106 /* Cached batch state is dead, since we just cleared some unknown part of the
107 * batchbuffer. Assume that the caller resets any other state necessary.
113 intel_batchbuffer_free(struct intel_context *intel)
115 drm_intel_bo_unreference(intel->batch.last_bo);
116 drm_intel_bo_unreference(intel->batch.bo);
117 drm_intel_bo_unreference(intel->batch.workaround_bo);
122 /* TODO: Push this whole function into bufmgr.
125 do_flush_locked(struct intel_context *intel)
127 struct intel_batchbuffer *batch = &intel->batch;
130 ret = drm_intel_bo_subdata(batch->bo, 0, 4*batch->used, batch->map);
131 if (ret == 0 && batch->state_batch_offset != batch->bo->size) {
132 ret = drm_intel_bo_subdata(batch->bo,
133 batch->state_batch_offset,
134 batch->bo->size - batch->state_batch_offset,
135 (char *)batch->map + batch->state_batch_offset);
138 if (!intel->intelScreen->no_hw) {
141 if (intel->gen < 6 || !batch->is_blit) {
142 flags = I915_EXEC_RENDER;
144 flags = I915_EXEC_BLT;
147 if (batch->needs_sol_reset)
148 flags |= I915_EXEC_GEN7_SOL_RESET;
151 ret = drm_intel_bo_mrb_exec(batch->bo, 4*batch->used, NULL, 0, 0,
155 if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
156 drm_intel_bo_map(batch->bo, false);
157 intel_decode(batch->bo->virtual, batch->used,
159 intel->intelScreen->deviceID, true);
160 drm_intel_bo_unmap(batch->bo);
162 if (intel->vtbl.debug_batch != NULL)
163 intel->vtbl.debug_batch(intel);
167 fprintf(stderr, "intel_do_flush_locked failed: %s\n", strerror(-ret));
170 intel->vtbl.new_batch(intel);
176 _intel_batchbuffer_flush(struct intel_context *intel,
177 const char *file, int line)
181 if (intel->batch.used == 0)
184 if (intel->first_post_swapbuffers_batch == NULL) {
185 intel->first_post_swapbuffers_batch = intel->batch.bo;
186 drm_intel_bo_reference(intel->first_post_swapbuffers_batch);
189 if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
190 fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line,
191 4*intel->batch.used);
193 intel->batch.reserved_space = 0;
195 /* Mark the end of the buffer. */
196 intel_batchbuffer_emit_dword(intel, MI_BATCH_BUFFER_END);
197 if (intel->batch.used & 1) {
198 /* Round batchbuffer usage to 2 DWORDs. */
199 intel_batchbuffer_emit_dword(intel, MI_NOOP);
202 if (intel->vtbl.finish_batch)
203 intel->vtbl.finish_batch(intel);
205 intel_upload_finish(intel);
207 /* Check that we didn't just wrap our batchbuffer at a bad time. */
208 assert(!intel->no_batch_wrap);
210 ret = do_flush_locked(intel);
212 if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
213 fprintf(stderr, "waiting for idle\n");
214 drm_intel_bo_wait_rendering(intel->batch.bo);
219 intel_batchbuffer_reset(intel);
225 /* This is the only way buffers get added to the validate list.
228 intel_batchbuffer_emit_reloc(struct intel_context *intel,
229 drm_intel_bo *buffer,
230 uint32_t read_domains, uint32_t write_domain,
235 ret = drm_intel_bo_emit_reloc(intel->batch.bo, 4*intel->batch.used,
237 read_domains, write_domain);
242 * Using the old buffer offset, write in what the right data would be, in case
243 * the buffer doesn't move and we can short-circuit the relocation processing
246 intel_batchbuffer_emit_dword(intel, buffer->offset + delta);
252 intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel,
253 drm_intel_bo *buffer,
254 uint32_t read_domains,
255 uint32_t write_domain,
260 ret = drm_intel_bo_emit_reloc_fence(intel->batch.bo, 4*intel->batch.used,
262 read_domains, write_domain);
267 * Using the old buffer offset, write in what the right data would
268 * be, in case the buffer doesn't move and we can short-circuit the
269 * relocation processing in the kernel
271 intel_batchbuffer_emit_dword(intel, buffer->offset + delta);
277 intel_batchbuffer_data(struct intel_context *intel,
278 const void *data, GLuint bytes, bool is_blit)
280 assert((bytes & 3) == 0);
281 intel_batchbuffer_require_space(intel, bytes, is_blit);
282 __memcpy(intel->batch.map + intel->batch.used, data, bytes);
283 intel->batch.used += bytes >> 2;
287 intel_batchbuffer_cached_advance(struct intel_context *intel)
289 struct cached_batch_item **prev = &intel->batch.cached_items, *item;
290 uint32_t sz = (intel->batch.used - intel->batch.emit) * sizeof(uint32_t);
291 uint32_t *start = intel->batch.map + intel->batch.emit;
292 uint16_t op = *start >> 16;
298 old = intel->batch.map + item->header;
299 if (op == *old >> 16) {
300 if (item->size == sz && memcmp(old, start, sz) == 0) {
301 if (prev != &intel->batch.cached_items) {
303 item->next = intel->batch.cached_items;
304 intel->batch.cached_items = item;
306 intel->batch.used = intel->batch.emit;
315 item = malloc(sizeof(struct cached_batch_item));
319 item->next = intel->batch.cached_items;
320 intel->batch.cached_items = item;
324 item->header = intel->batch.emit;
328 * Restriction [DevSNB, DevIVB]:
330 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
331 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
332 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
333 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
334 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
335 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
336 * unless SW can otherwise guarantee that the pipeline from WM onwards is
337 * already flushed (e.g., via a preceding MI_FLUSH).
340 intel_emit_depth_stall_flushes(struct intel_context *intel)
342 assert(intel->gen >= 6 && intel->gen <= 7);
345 OUT_BATCH(_3DSTATE_PIPE_CONTROL);
346 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL);
347 OUT_BATCH(0); /* address */
348 OUT_BATCH(0); /* write data */
352 OUT_BATCH(_3DSTATE_PIPE_CONTROL);
353 OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH);
354 OUT_BATCH(0); /* address */
355 OUT_BATCH(0); /* write data */
359 OUT_BATCH(_3DSTATE_PIPE_CONTROL);
360 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL);
361 OUT_BATCH(0); /* address */
362 OUT_BATCH(0); /* write data */
367 * From the BSpec, volume 2a.03: VS Stage Input / State:
368 * "[DevIVB] A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
369 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
370 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
371 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
372 * to be sent before any combination of VS associated 3DSTATE."
375 gen7_emit_vs_workaround_flush(struct intel_context *intel)
377 assert(intel->gen == 7);
380 OUT_BATCH(_3DSTATE_PIPE_CONTROL);
381 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_IMMEDIATE);
382 OUT_RELOC(intel->batch.workaround_bo,
383 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
384 OUT_BATCH(0); /* write data */
389 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
390 * implementing two workarounds on gen6. From section 1.4.7.1
391 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
393 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
394 * produced by non-pipelined state commands), software needs to first
395 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
398 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
399 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
401 * And the workaround for these two requires this workaround first:
403 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
404 * BEFORE the pipe-control with a post-sync op and no write-cache
407 * And this last workaround is tricky because of the requirements on
408 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
411 * "1 of the following must also be set:
412 * - Render Target Cache Flush Enable ([12] of DW1)
413 * - Depth Cache Flush Enable ([0] of DW1)
414 * - Stall at Pixel Scoreboard ([1] of DW1)
415 * - Depth Stall ([13] of DW1)
416 * - Post-Sync Operation ([13] of DW1)
417 * - Notify Enable ([8] of DW1)"
419 * The cache flushes require the workaround flush that triggered this
420 * one, so we can't use it. Depth stall would trigger the same.
421 * Post-sync nonzero is what triggered this second workaround, so we
422 * can't use that one either. Notify enable is IRQs, which aren't
423 * really our business. That leaves only stall at scoreboard.
426 intel_emit_post_sync_nonzero_flush(struct intel_context *intel)
428 if (!intel->batch.need_workaround_flush)
432 OUT_BATCH(_3DSTATE_PIPE_CONTROL);
433 OUT_BATCH(PIPE_CONTROL_CS_STALL |
434 PIPE_CONTROL_STALL_AT_SCOREBOARD);
435 OUT_BATCH(0); /* address */
436 OUT_BATCH(0); /* write data */
440 OUT_BATCH(_3DSTATE_PIPE_CONTROL);
441 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
442 OUT_RELOC(intel->batch.workaround_bo,
443 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
444 OUT_BATCH(0); /* write data */
447 intel->batch.need_workaround_flush = false;
450 /* Emit a pipelined flush to either flush render and texture cache for
451 * reading from a FBO-drawn texture, or flush so that frontbuffer
452 * render appears on the screen in DRI1.
454 * This is also used for the always_flush_cache driconf debug option.
457 intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
459 if (intel->gen >= 6) {
460 if (intel->batch.is_blit) {
462 OUT_BATCH(MI_FLUSH_DW);
468 if (intel->gen == 6) {
469 /* Hardware workaround: SNB B-Spec says:
471 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
472 * Flush Enable =1, a PIPE_CONTROL with any non-zero
473 * post-sync-op is required.
475 intel_emit_post_sync_nonzero_flush(intel);
479 OUT_BATCH(_3DSTATE_PIPE_CONTROL);
480 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
481 PIPE_CONTROL_WRITE_FLUSH |
482 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
483 PIPE_CONTROL_VF_CACHE_INVALIDATE |
484 PIPE_CONTROL_TC_FLUSH |
485 PIPE_CONTROL_NO_WRITE |
486 PIPE_CONTROL_CS_STALL);
487 OUT_BATCH(0); /* write address */
488 OUT_BATCH(0); /* write data */
491 } else if (intel->gen >= 4) {
493 OUT_BATCH(_3DSTATE_PIPE_CONTROL |
494 PIPE_CONTROL_WRITE_FLUSH |
495 PIPE_CONTROL_NO_WRITE);
496 OUT_BATCH(0); /* write address */
497 OUT_BATCH(0); /* write data */
498 OUT_BATCH(0); /* write data */