gl/mesa/src/gallium/drivers/r300/compiler/radeon_opcodes.c

   1 /*
   2  * Copyright (C) 2009 Nicolai Haehnle.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_opcodes.h"
  29 #include "radeon_program.h"
  30
  31 #include "radeon_program_constants.h"
  32
  33 struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
  34         {
  35                 .Opcode = RC_OPCODE_NOP,
  36                 .Name = "NOP"
  37         },
  38         {
  39                 .Opcode = RC_OPCODE_ILLEGAL_OPCODE,
  40                 .Name = "ILLEGAL OPCODE"
  41         },
  42         {
  43                 .Opcode = RC_OPCODE_ABS,
  44                 .Name = "ABS",
  45                 .NumSrcRegs = 1,
  46                 .HasDstReg = 1,
  47                 .IsComponentwise = 1
  48         },
  49         {
  50                 .Opcode = RC_OPCODE_ADD,
  51                 .Name = "ADD",
  52                 .NumSrcRegs = 2,
  53                 .HasDstReg = 1,
  54                 .IsComponentwise = 1
  55         },
  56         {
  57                 .Opcode = RC_OPCODE_ARL,
  58                 .Name = "ARL",
  59                 .NumSrcRegs = 1,
  60                 .HasDstReg = 1
  61         },
  62         {
  63                 .Opcode = RC_OPCODE_CEIL,
  64                 .Name = "CEIL",
  65                 .NumSrcRegs = 1,
  66                 .HasDstReg = 1,
  67                 .IsComponentwise = 1
  68         },
  69         {
  70                 .Opcode = RC_OPCODE_CLAMP,
  71                 .Name = "CLAMP",
  72                 .NumSrcRegs = 3,
  73                 .HasDstReg = 1,
  74                 .IsComponentwise = 1
  75         },
  76         {
  77                 .Opcode = RC_OPCODE_CMP,
  78                 .Name = "CMP",
  79                 .NumSrcRegs = 3,
  80                 .HasDstReg = 1,
  81                 .IsComponentwise = 1
  82         },
  83         {
  84                 .Opcode = RC_OPCODE_CND,
  85                 .Name = "CND",
  86                 .NumSrcRegs = 3,
  87                 .HasDstReg = 1,
  88                 .IsComponentwise = 1
  89         },
  90         {
  91                 .Opcode = RC_OPCODE_COS,
  92                 .Name = "COS",
  93                 .NumSrcRegs = 1,
  94                 .HasDstReg = 1,
  95                 .IsStandardScalar = 1
  96         },
  97         {
  98                 .Opcode = RC_OPCODE_DDX,
  99                 .Name = "DDX",
 100                 .NumSrcRegs = 2,
 101                 .HasDstReg = 1,
 102                 .IsComponentwise = 1
 103         },
 104         {
 105                 .Opcode = RC_OPCODE_DDY,
 106                 .Name = "DDY",
 107                 .NumSrcRegs = 2,
 108                 .HasDstReg = 1,
 109                 .IsComponentwise = 1
 110         },
 111         {
 112                 .Opcode = RC_OPCODE_DP2,
 113                 .Name = "DP2",
 114                 .NumSrcRegs = 2,
 115                 .HasDstReg = 1
 116         },
 117         {
 118                 .Opcode = RC_OPCODE_DP3,
 119                 .Name = "DP3",
 120                 .NumSrcRegs = 2,
 121                 .HasDstReg = 1
 122         },
 123         {
 124                 .Opcode = RC_OPCODE_DP4,
 125                 .Name = "DP4",
 126                 .NumSrcRegs = 2,
 127                 .HasDstReg = 1
 128         },
 129         {
 130                 .Opcode = RC_OPCODE_DPH,
 131                 .Name = "DPH",
 132                 .NumSrcRegs = 2,
 133                 .HasDstReg = 1
 134         },
 135         {
 136                 .Opcode = RC_OPCODE_DST,
 137                 .Name = "DST",
 138                 .NumSrcRegs = 2,
 139                 .HasDstReg = 1
 140         },
 141         {
 142                 .Opcode = RC_OPCODE_EX2,
 143                 .Name = "EX2",
 144                 .NumSrcRegs = 1,
 145                 .HasDstReg = 1,
 146                 .IsStandardScalar = 1
 147         },
 148         {
 149                 .Opcode = RC_OPCODE_EXP,
 150                 .Name = "EXP",
 151                 .NumSrcRegs = 1,
 152                 .HasDstReg = 1
 153         },
 154         {
 155                 .Opcode = RC_OPCODE_FLR,
 156                 .Name = "FLR",
 157                 .NumSrcRegs = 1,
 158                 .HasDstReg = 1,
 159                 .IsComponentwise = 1
 160         },
 161         {
 162                 .Opcode = RC_OPCODE_FRC,
 163                 .Name = "FRC",
 164                 .NumSrcRegs = 1,
 165                 .HasDstReg = 1,
 166                 .IsComponentwise = 1
 167         },
 168         {
 169                 .Opcode = RC_OPCODE_KIL,
 170                 .Name = "KIL",
 171                 .NumSrcRegs = 1
 172         },
 173         {
 174                 .Opcode = RC_OPCODE_LG2,
 175                 .Name = "LG2",
 176                 .NumSrcRegs = 1,
 177                 .HasDstReg = 1,
 178                 .IsStandardScalar = 1
 179         },
 180         {
 181                 .Opcode = RC_OPCODE_LIT,
 182                 .Name = "LIT",
 183                 .NumSrcRegs = 1,
 184                 .HasDstReg = 1
 185         },
 186         {
 187                 .Opcode = RC_OPCODE_LOG,
 188                 .Name = "LOG",
 189                 .NumSrcRegs = 1,
 190                 .HasDstReg = 1
 191         },
 192         {
 193                 .Opcode = RC_OPCODE_LRP,
 194                 .Name = "LRP",
 195                 .NumSrcRegs = 3,
 196                 .HasDstReg = 1,
 197                 .IsComponentwise = 1
 198         },
 199         {
 200                 .Opcode = RC_OPCODE_MAD,
 201                 .Name = "MAD",
 202                 .NumSrcRegs = 3,
 203                 .HasDstReg = 1,
 204                 .IsComponentwise = 1
 205         },
 206         {
 207                 .Opcode = RC_OPCODE_MAX,
 208                 .Name = "MAX",
 209                 .NumSrcRegs = 2,
 210                 .HasDstReg = 1,
 211                 .IsComponentwise = 1
 212         },
 213         {
 214                 .Opcode = RC_OPCODE_MIN,
 215                 .Name = "MIN",
 216                 .NumSrcRegs = 2,
 217                 .HasDstReg = 1,
 218                 .IsComponentwise = 1
 219         },
 220         {
 221                 .Opcode = RC_OPCODE_MOV,
 222                 .Name = "MOV",
 223                 .NumSrcRegs = 1,
 224                 .HasDstReg = 1,
 225                 .IsComponentwise = 1
 226         },
 227         {
 228                 .Opcode = RC_OPCODE_MUL,
 229                 .Name = "MUL",
 230                 .NumSrcRegs = 2,
 231                 .HasDstReg = 1,
 232                 .IsComponentwise = 1
 233         },
 234         {
 235                 .Opcode = RC_OPCODE_POW,
 236                 .Name = "POW",
 237                 .NumSrcRegs = 2,
 238                 .HasDstReg = 1,
 239                 .IsStandardScalar = 1
 240         },
 241         {
 242                 .Opcode = RC_OPCODE_RCP,
 243                 .Name = "RCP",
 244                 .NumSrcRegs = 1,
 245                 .HasDstReg = 1,
 246                 .IsStandardScalar = 1
 247         },
 248         {
 249                 .Opcode = RC_OPCODE_ROUND,
 250                 .Name = "ROUND",
 251                 .NumSrcRegs = 1,
 252                 .HasDstReg = 1,
 253                 .IsComponentwise = 1
 254         },
 255         {
 256                 .Opcode = RC_OPCODE_RSQ,
 257                 .Name = "RSQ",
 258                 .NumSrcRegs = 1,
 259                 .HasDstReg = 1,
 260                 .IsStandardScalar = 1
 261         },
 262         {
 263                 .Opcode = RC_OPCODE_SCS,
 264                 .Name = "SCS",
 265                 .NumSrcRegs = 1,
 266                 .HasDstReg = 1
 267         },
 268         {
 269                 .Opcode = RC_OPCODE_SEQ,
 270                 .Name = "SEQ",
 271                 .NumSrcRegs = 2,
 272                 .HasDstReg = 1,
 273                 .IsComponentwise = 1
 274         },
 275         {
 276                 .Opcode = RC_OPCODE_SFL,
 277                 .Name = "SFL",
 278                 .NumSrcRegs = 0,
 279                 .HasDstReg = 1,
 280                 .IsComponentwise = 1
 281         },
 282         {
 283                 .Opcode = RC_OPCODE_SGE,
 284                 .Name = "SGE",
 285                 .NumSrcRegs = 2,
 286                 .HasDstReg = 1,
 287                 .IsComponentwise = 1
 288         },
 289         {
 290                 .Opcode = RC_OPCODE_SGT,
 291                 .Name = "SGT",
 292                 .NumSrcRegs = 2,
 293                 .HasDstReg = 1,
 294                 .IsComponentwise = 1
 295         },
 296         {
 297                 .Opcode = RC_OPCODE_SIN,
 298                 .Name = "SIN",
 299                 .NumSrcRegs = 1,
 300                 .HasDstReg = 1,
 301                 .IsStandardScalar = 1
 302         },
 303         {
 304                 .Opcode = RC_OPCODE_SLE,
 305                 .Name = "SLE",
 306                 .NumSrcRegs = 2,
 307                 .HasDstReg = 1,
 308                 .IsComponentwise = 1
 309         },
 310         {
 311                 .Opcode = RC_OPCODE_SLT,
 312                 .Name = "SLT",
 313                 .NumSrcRegs = 2,
 314                 .HasDstReg = 1,
 315                 .IsComponentwise = 1
 316         },
 317         {
 318                 .Opcode = RC_OPCODE_SNE,
 319                 .Name = "SNE",
 320                 .NumSrcRegs = 2,
 321                 .HasDstReg = 1,
 322                 .IsComponentwise = 1
 323         },
 324         {
 325                 .Opcode = RC_OPCODE_SSG,
 326                 .Name = "SSG",
 327                 .NumSrcRegs = 1,
 328                 .HasDstReg = 1,
 329                 .IsComponentwise = 1
 330         },
 331         {
 332                 .Opcode = RC_OPCODE_SUB,
 333                 .Name = "SUB",
 334                 .NumSrcRegs = 2,
 335                 .HasDstReg = 1,
 336                 .IsComponentwise = 1
 337         },
 338         {
 339                 .Opcode = RC_OPCODE_SWZ,
 340                 .Name = "SWZ",
 341                 .NumSrcRegs = 1,
 342                 .HasDstReg = 1,
 343                 .IsComponentwise = 1
 344         },
 345         {
 346                 .Opcode = RC_OPCODE_XPD,
 347                 .Name = "XPD",
 348                 .NumSrcRegs = 2,
 349                 .HasDstReg = 1
 350         },
 351         {
 352                 .Opcode = RC_OPCODE_TEX,
 353                 .Name = "TEX",
 354                 .HasTexture = 1,
 355                 .NumSrcRegs = 1,
 356                 .HasDstReg = 1
 357         },
 358         {
 359                 .Opcode = RC_OPCODE_TXB,
 360                 .Name = "TXB",
 361                 .HasTexture = 1,
 362                 .NumSrcRegs = 1,
 363                 .HasDstReg = 1
 364         },
 365         {
 366                 .Opcode = RC_OPCODE_TXD,
 367                 .Name = "TXD",
 368                 .HasTexture = 1,
 369                 .NumSrcRegs = 3,
 370                 .HasDstReg = 1
 371         },
 372         {
 373                 .Opcode = RC_OPCODE_TXL,
 374                 .Name = "TXL",
 375                 .HasTexture = 1,
 376                 .NumSrcRegs = 1,
 377                 .HasDstReg = 1
 378         },
 379         {
 380                 .Opcode = RC_OPCODE_TXP,
 381                 .Name = "TXP",
 382                 .HasTexture = 1,
 383                 .NumSrcRegs = 1,
 384                 .HasDstReg = 1
 385         },
 386         {
 387                 .Opcode = RC_OPCODE_IF,
 388                 .Name = "IF",
 389                 .IsFlowControl = 1,
 390                 .NumSrcRegs = 1
 391         },
 392         {
 393                 .Opcode = RC_OPCODE_ELSE,
 394                 .Name = "ELSE",
 395                 .IsFlowControl = 1,
 396                 .NumSrcRegs = 0
 397         },
 398         {
 399                 .Opcode = RC_OPCODE_ENDIF,
 400                 .Name = "ENDIF",
 401                 .IsFlowControl = 1,
 402                 .NumSrcRegs = 0
 403         },
 404         {
 405                 .Opcode = RC_OPCODE_BGNLOOP,
 406                 .Name = "BGNLOOP",
 407                 .IsFlowControl = 1,
 408                 .NumSrcRegs = 0
 409         },
 410         {
 411                 .Opcode = RC_OPCODE_BRK,
 412                 .Name = "BRK",
 413                 .IsFlowControl = 1,
 414                 .NumSrcRegs = 0
 415         },
 416         {
 417                 .Opcode = RC_OPCODE_ENDLOOP,
 418                 .Name = "ENDLOOP",
 419                 .IsFlowControl = 1,
 420                 .NumSrcRegs = 0,
 421         },
 422         {
 423                 .Opcode = RC_OPCODE_CONT,
 424                 .Name = "CONT",
 425                 .IsFlowControl = 1,
 426                 .NumSrcRegs = 0
 427         },
 428         {
 429                 .Opcode = RC_OPCODE_REPL_ALPHA,
 430                 .Name = "REPL_ALPHA",
 431                 .HasDstReg = 1
 432         },
 433         {
 434                 .Opcode = RC_OPCODE_BEGIN_TEX,
 435                 .Name = "BEGIN_TEX"
 436         },
 437         {
 438                 .Opcode = RC_OPCODE_KILP,
 439                 .Name = "KILP",
 440         }
 441 };
 442
 443 void rc_compute_sources_for_writemask(
 444                 const struct rc_instruction *inst,
 445                 unsigned int writemask,
 446                 unsigned int *srcmasks)
 447 {
 448         const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
 449         srcmasks[0] = 0;
 450         srcmasks[1] = 0;
 451         srcmasks[2] = 0;
 452
 453         if (opcode->Opcode == RC_OPCODE_KIL)
 454                 srcmasks[0] |= RC_MASK_XYZW;
 455         else if (opcode->Opcode == RC_OPCODE_IF)
 456                 srcmasks[0] |= RC_MASK_X;
 457
 458         if (!writemask)
 459                 return;
 460
 461         if (opcode->IsComponentwise) {
 462                 for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src)
 463                         srcmasks[src] |= writemask;
 464         } else if (opcode->IsStandardScalar) {
 465                 for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src)
 466                         srcmasks[src] |= writemask;
 467         } else {
 468                 switch(opcode->Opcode) {
 469                 case RC_OPCODE_ARL:
 470                         srcmasks[0] |= RC_MASK_X;
 471                         break;
 472                 case RC_OPCODE_DP2:
 473                         srcmasks[0] |= RC_MASK_XY;
 474                         srcmasks[1] |= RC_MASK_XY;
 475                         break;
 476                 case RC_OPCODE_DP3:
 477                 case RC_OPCODE_XPD:
 478                         srcmasks[0] |= RC_MASK_XYZ;
 479                         srcmasks[1] |= RC_MASK_XYZ;
 480                         break;
 481                 case RC_OPCODE_DP4:
 482                         srcmasks[0] |= RC_MASK_XYZW;
 483                         srcmasks[1] |= RC_MASK_XYZW;
 484                         break;
 485                 case RC_OPCODE_DPH:
 486                         srcmasks[0] |= RC_MASK_XYZ;
 487                         srcmasks[1] |= RC_MASK_XYZW;
 488                         break;
 489                 case RC_OPCODE_TXB:
 490                 case RC_OPCODE_TXP:
 491                 case RC_OPCODE_TXL:
 492                         srcmasks[0] |= RC_MASK_W;
 493                         /* Fall through */
 494                 case RC_OPCODE_TEX:
 495                         switch (inst->U.I.TexSrcTarget) {
 496                                 case RC_TEXTURE_1D:
 497                                         srcmasks[0] |= RC_MASK_X;
 498                                         break;
 499                                 case RC_TEXTURE_2D:
 500                                 case RC_TEXTURE_RECT:
 501                                 case RC_TEXTURE_1D_ARRAY:
 502                                         srcmasks[0] |= RC_MASK_XY;
 503                                         break;
 504                                 case RC_TEXTURE_3D:
 505                                 case RC_TEXTURE_CUBE:
 506                                 case RC_TEXTURE_2D_ARRAY:
 507                                         srcmasks[0] |= RC_MASK_XYZ;
 508                                         break;
 509                         }
 510                         break;
 511                 case RC_OPCODE_TXD:
 512                         switch (inst->U.I.TexSrcTarget) {
 513                                 case RC_TEXTURE_1D_ARRAY:
 514                                         srcmasks[0] |= RC_MASK_Y;
 515                                         /* Fall through. */
 516                                 case RC_TEXTURE_1D:
 517                                         srcmasks[0] |= RC_MASK_X;
 518                                         srcmasks[1] |= RC_MASK_X;
 519                                         srcmasks[2] |= RC_MASK_X;
 520                                         break;
 521                                 case RC_TEXTURE_2D_ARRAY:
 522                                         srcmasks[0] |= RC_MASK_Z;
 523                                         /* Fall through. */
 524                                 case RC_TEXTURE_2D:
 525                                 case RC_TEXTURE_RECT:
 526                                         srcmasks[0] |= RC_MASK_XY;
 527                                         srcmasks[1] |= RC_MASK_XY;
 528                                         srcmasks[2] |= RC_MASK_XY;
 529                                         break;
 530                                 case RC_TEXTURE_3D:
 531                                 case RC_TEXTURE_CUBE:
 532                                         srcmasks[0] |= RC_MASK_XYZ;
 533                                         srcmasks[1] |= RC_MASK_XYZ;
 534                                         srcmasks[2] |= RC_MASK_XYZ;
 535                                         break;
 536                         }
 537                         break;
 538                 case RC_OPCODE_DST:
 539                         srcmasks[0] |= RC_MASK_Y | RC_MASK_Z;
 540                         srcmasks[1] |= RC_MASK_Y | RC_MASK_W;
 541                         break;
 542                 case RC_OPCODE_EXP:
 543                 case RC_OPCODE_LOG:
 544                         srcmasks[0] |= RC_MASK_XY;
 545                         break;
 546                 case RC_OPCODE_LIT:
 547                         srcmasks[0] |= RC_MASK_X | RC_MASK_Y | RC_MASK_W;
 548                         break;
 549                 default:
 550                         break;
 551                 }
 552         }
 553 }