2 * This file is part of the flashrom project.
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include "programmer.h"
27 #define PCI_VENDOR_ID_NVIDIA 0x10de
29 /* Mask to restrict flash accesses to a 128kB memory window.
30 * FIXME: Is this size a one-fits-all or card dependent?
32 #define GFXNVIDIA_MEMMAP_MASK ((1 << 17) - 1)
33 #define GFXNVIDIA_MEMMAP_SIZE (16 * 1024 * 1024)
37 const struct pcidev_status gfx_nvidia[] = {
38 {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" },
39 {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" },
40 {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" },
41 {0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" },
42 {0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" },
43 {0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" },
44 {0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" },
45 {0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" },
46 {0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" },
47 {0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" },
48 {0x10de, 0x0103, NT, "NVIDIA", "Quadro" },
49 {0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" },
50 {0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" },
51 {0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" },
52 {0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" },
53 {0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" },
54 {0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" },
55 {0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" },
56 {0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" },
57 {0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" },
58 {0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" },
59 {0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" },
60 {0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" },
65 static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
67 static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
69 static const struct par_programmer par_programmer_gfxnvidia = {
70 .chip_readb = gfxnvidia_chip_readb,
71 .chip_readw = fallback_chip_readw,
72 .chip_readl = fallback_chip_readl,
73 .chip_readn = fallback_chip_readn,
74 .chip_writeb = gfxnvidia_chip_writeb,
75 .chip_writew = fallback_chip_writew,
76 .chip_writel = fallback_chip_writel,
77 .chip_writen = fallback_chip_writen,
80 static int gfxnvidia_shutdown(void *data)
82 physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE);
83 /* Flash interface access is disabled (and screen enabled) automatically
90 int gfxnvidia_init(void)
97 io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia);
99 io_base_addr += 0x300000;
100 msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);
102 nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE);
104 /* Must be done before rpci calls. */
105 if (register_shutdown(gfxnvidia_shutdown, NULL))
108 /* Allow access to flash interface (will disable screen). */
109 reg32 = pci_read_long(pcidev_dev, 0x50);
111 rpci_write_long(pcidev_dev, 0x50, reg32);
113 /* Write/erase doesn't work. */
114 programmer_may_write = 0;
115 register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL);
120 static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
123 pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
126 static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
129 return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));